H/W Address | Type | Name | VHDL/Verilog prefix | C prefix |
---|---|---|---|---|
0x0 | REG | Syscon reset register | sysc_rstr | RSTR |
0x1 | REG | GPIO Set/Readback Register | sysc_gpsr | GPSR |
0x2 | REG | GPIO Clear Register | sysc_gpcr | GPCR |
0x3 | REG | Hardware Feature Register | sysc_hwfr | HWFR |
0x4 | REG | Timer Control Register | sysc_tcr | TCR |
0x5 | REG | Timer Counter Value Register | sysc_tvr | TVR |
→ | rst_n_i | Syscon reset register: | ||
→ | clk_sys_i | sysc_rstr_trig_o[27:0] | ⇒ | |
⇒ | wb_adr_i[2:0] | sysc_rstr_trig_wr_o | → | |
⇒ | wb_dat_i[31:0] | sysc_rstr_rst_o | → | |
⇐ | wb_dat_o[31:0] | |||
→ | wb_cyc_i | GPIO Set/Readback Register: | ||
⇒ | wb_sel_i[3:0] | sysc_gpsr_led_stat_o | → | |
→ | wb_stb_i | sysc_gpsr_led_link_o | → | |
→ | wb_we_i | sysc_gpsr_fmc_scl_o | → | |
← | wb_ack_o | sysc_gpsr_fmc_scl_i | ← | |
← | wb_stall_o | sysc_gpsr_fmc_scl_load_o | → | |
sysc_gpsr_fmc_sda_o | → | |||
sysc_gpsr_fmc_sda_i | ← | |||
sysc_gpsr_fmc_sda_load_o | → | |||
sysc_gpsr_net_rst_o | → | |||
sysc_gpsr_btn1_i | ← | |||
sysc_gpsr_btn2_i | ← | |||
sysc_gpsr_sfp_det_i | ← | |||
sysc_gpsr_sfp_scl_o | → | |||
sysc_gpsr_sfp_scl_i | ← | |||
sysc_gpsr_sfp_scl_load_o | → | |||
sysc_gpsr_sfp_sda_o | → | |||
sysc_gpsr_sfp_sda_i | ← | |||
sysc_gpsr_sfp_sda_load_o | → | |||
GPIO Clear Register: | ||||
sysc_gpcr_led_stat_o | → | |||
sysc_gpcr_led_link_o | → | |||
sysc_gpcr_fmc_scl_o | → | |||
sysc_gpcr_fmc_sda_o | → | |||
sysc_gpcr_sfp_scl_o | → | |||
sysc_gpcr_sfp_sda_o | → | |||
Hardware Feature Register: | ||||
sysc_hwfr_memsize_i[3:0] | ⇐ | |||
Timer Control Register: | ||||
sysc_tcr_tdiv_i[11:0] | ⇐ | |||
sysc_tcr_enable_o | → | |||
Timer Counter Value Register: | ||||
sysc_tvr_i[31:0] | ⇐ |
HW prefix: | sysc_rstr |
HW address: | 0x0 |
C prefix: | RSTR |
C offset: | 0x0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||
- | - | - | RST | TRIG[27:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
TRIG[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
TRIG[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
TRIG[7:0] |
HW prefix: | sysc_gpsr |
HW address: | 0x1 |
C prefix: | GPSR |
C offset: | 0x4 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | SFP_SDA | SFP_SCL |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SFP_DET | BTN2 | BTN1 | NET_RST | FMC_SDA | FMC_SCL | LED_LINK | LED_STAT |
HW prefix: | sysc_gpcr |
HW address: | 0x2 |
C prefix: | GPCR |
C offset: | 0x8 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | SFP_SDA | SFP_SCL |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | FMC_SDA | FMC_SCL | LED_LINK | LED_STAT |
HW prefix: | sysc_hwfr |
HW address: | 0x3 |
C prefix: | HWFR |
C offset: | 0xc |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
- | - | - | - | MEMSIZE[3:0] |
HW prefix: | sysc_tcr |
HW address: | 0x4 |
C prefix: | TCR |
C offset: | 0x10 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ENABLE | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||
- | - | - | - | TDIV[11:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
TDIV[7:0] |
HW prefix: | sysc_tvr |
HW address: | 0x5 |
C prefix: | TVR |
C offset: | 0x14 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
TVR[31:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
TVR[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
TVR[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
TVR[7:0] |