wrsw_txtsu_wb

Shared TX Timestamping Unit (TXTSU)

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Interrupt disable register
3.2. Interrupt enable register
3.3. Interrupt mask register
3.4. Interrupt status register
3.5. FIFO 'Timestamp FIFO' data output register 0
3.6. FIFO 'Timestamp FIFO' data output register 1
3.7. FIFO 'Timestamp FIFO' data output register 2
3.8. FIFO 'Timestamp FIFO' control/status register
5. Interrupts
5.1. TXTSU fifo not-empty

1. Memory map summary

H/W Address	Type	Name	VHDL/Verilog prefix	C prefix
0x0	REG	Interrupt disable register	txtsu_eic_idr	EIC_IDR
0x1	REG	Interrupt enable register	txtsu_eic_ier	EIC_IER
0x2	REG	Interrupt mask register	txtsu_eic_imr	EIC_IMR
0x3	REG	Interrupt status register	txtsu_eic_isr	EIC_ISR
0x4	FIFOREG	FIFO 'Timestamp FIFO' data output register 0	txtsu_tsf_r0	TSF_R0
0x5	FIFOREG	FIFO 'Timestamp FIFO' data output register 1	txtsu_tsf_r1	TSF_R1
0x6	FIFOREG	FIFO 'Timestamp FIFO' data output register 2	txtsu_tsf_r2	TSF_R2
0x7	REG	FIFO 'Timestamp FIFO' control/status register	txtsu_tsf_csr	TSF_CSR

2. HDL symbol

→	rst_n_i	Timestamp FIFO:
→	clk_sys_i	txtsu_tsf_wr_req_i	←
⇒	wb_adr_i[2:0]	txtsu_tsf_wr_full_o	→
⇒	wb_dat_i[31:0]	txtsu_tsf_wr_empty_o	→
⇐	wb_dat_o[31:0]	txtsu_tsf_val_r_i[27:0]	⇐
→	wb_cyc_i	txtsu_tsf_val_f_i[3:0]	⇐
⇒	wb_sel_i[3:0]	txtsu_tsf_pid_i[4:0]	⇐
→	wb_stb_i	txtsu_tsf_fid_i[15:0]	⇐
→	wb_we_i	txtsu_tsf_incorrect_i	←
←	wb_ack_o
←	wb_stall_o	TXTSU fifo not-empty:
←	wb_int_o	irq_nempty_i	←

		FIFO 'Timestamp FIFO' data output register 0:

		FIFO 'Timestamp FIFO' data output register 1:

		FIFO 'Timestamp FIFO' data output register 2:

3. Register description

3.1. Interrupt disable register

HW prefix:	txtsu_eic_idr
HW address:	0x0
C prefix:	EIC_IDR
C offset:	0x0

Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	NEMPTY

NEMPTY [write-only]: TXTSU fifo not-empty
write 1: disable interrupt 'TXTSU fifo not-empty'
write 0: no effect

3.2. Interrupt enable register

HW prefix:	txtsu_eic_ier
HW address:	0x1
C prefix:	EIC_IER
C offset:	0x4

Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	NEMPTY

NEMPTY [write-only]: TXTSU fifo not-empty
write 1: enable interrupt 'TXTSU fifo not-empty'
write 0: no effect

3.3. Interrupt mask register

HW prefix:	txtsu_eic_imr
HW address:	0x2
C prefix:	EIC_IMR
C offset:	0x8

Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	NEMPTY

NEMPTY [read-only]: TXTSU fifo not-empty
read 1: interrupt 'TXTSU fifo not-empty' is enabled
read 0: interrupt 'TXTSU fifo not-empty' is disabled

3.4. Interrupt status register

HW prefix:	txtsu_eic_isr
HW address:	0x3
C prefix:	EIC_ISR
C offset:	0xc

Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	NEMPTY

NEMPTY [read/write]: TXTSU fifo not-empty
read 1: interrupt 'TXTSU fifo not-empty' is pending
read 0: interrupt not pending
write 1: clear interrupt 'TXTSU fifo not-empty'
write 0: no effect

3.5. FIFO 'Timestamp FIFO' data output register 0

HW prefix:	txtsu_tsf_r0
HW address:	0x4
C prefix:	TSF_R0
C offset:	0x10

31	30	29	28	27	26	25	24
VAL_F[3:0]				VAL_R[27:24]

23	22	21	20	19	18	17	16
VAL_R[23:16]

15	14	13	12	11	10	9	8
VAL_R[15:8]

7	6	5	4	3	2	1	0
VAL_R[7:0]

VAL_R [read-only]: Rising edge timestamp
VAL_F [read-only]: Falling edge timestamp
Timestamp value taken on falling clock edge (few LSBs)

3.6. FIFO 'Timestamp FIFO' data output register 1

HW prefix:	txtsu_tsf_r1
HW address:	0x5
C prefix:	TSF_R1
C offset:	0x14

31	30	29	28	27	26	25	24
FID[15:8]

23	22	21	20	19	18	17	16
FID[7:0]

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	PID[4:0]

PID [read-only]: Physical port ID
Identifier of the TXTSU port to which came the timestamp. There may be multiple timestamps sharing the same FID value for broadcast/multicast packets.
FID [read-only]: Frame ID
OOB Frame Identifier. Used to associate the timestamp value with transmitted packet.

3.7. FIFO 'Timestamp FIFO' data output register 2

HW prefix:	txtsu_tsf_r2
HW address:	0x6
C prefix:	TSF_R2
C offset:	0x18

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	INCORRECT

INCORRECT [read-only]: Timestamp (possibly) incorrect
1: This timestamp may be incorrect (generated during PPS adjustment)
0: Timestamp is correct.

3.8. FIFO 'Timestamp FIFO' control/status register

HW prefix:	txtsu_tsf_csr
HW address:	0x7
C prefix:	TSF_CSR
C offset:	0x1c

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	EMPTY	FULL

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
USEDW[7:0]

FULL [read-only]: FIFO full flag
1: FIFO 'Timestamp FIFO' is full
0: FIFO is not full
EMPTY [read-only]: FIFO empty flag
1: FIFO 'Timestamp FIFO' is empty
0: FIFO is not empty
USEDW [read-only]: FIFO counter
Number of data records currently being stored in FIFO 'Timestamp FIFO'

5. Interrupts

5.1. TXTSU fifo not-empty

HW prefix:	txtsu_nempty
C prefix:	NEMPTY
Trigger:	high level

Interrupt active when TXTSU shared FIFO contains any timestamps.

wrsw_txtsu_wb

Shared TX Timestamping Unit (TXTSU)

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