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-- Title          : Wishbone slave core for FMC-DIO-5chttla
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-- File           : wrsw_dio_wb.vhd
-- Author         : auto-generated by wbgen2 from wrsw_dio.wb
-- Created        : Fri Jul 27 17:57:07 2012
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dio.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;

entity wrsw_dio_wb is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(5 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    wb_int_o                                 : out    std_logic;
    clk_asyn_i                               : in     std_logic;
-- FIFO write request
    dio_tsf0_wr_req_i                        : in     std_logic;
-- FIFO full flag
    dio_tsf0_wr_full_o                       : out    std_logic;
-- FIFO empty flag
    dio_tsf0_wr_empty_o                      : out    std_logic;
    dio_tsf0_tag_seconds_i                   : in     std_logic_vector(31 downto 0);
    dio_tsf0_tag_secondsh_i                  : in     std_logic_vector(7 downto 0);
    dio_tsf0_tag_cycles_i                    : in     std_logic_vector(27 downto 0);
    irq_nempty_0_i                           : in     std_logic;
-- FIFO write request
    dio_tsf1_wr_req_i                        : in     std_logic;
-- FIFO full flag
    dio_tsf1_wr_full_o                       : out    std_logic;
-- FIFO empty flag
    dio_tsf1_wr_empty_o                      : out    std_logic;
    dio_tsf1_tag_seconds_i                   : in     std_logic_vector(31 downto 0);
    dio_tsf1_tag_secondsh_i                  : in     std_logic_vector(7 downto 0);
    dio_tsf1_tag_cycles_i                    : in     std_logic_vector(27 downto 0);
    irq_nempty_1_i                           : in     std_logic;
-- FIFO write request
    dio_tsf2_wr_req_i                        : in     std_logic;
-- FIFO full flag
    dio_tsf2_wr_full_o                       : out    std_logic;
-- FIFO empty flag
    dio_tsf2_wr_empty_o                      : out    std_logic;
    dio_tsf2_tag_seconds_i                   : in     std_logic_vector(31 downto 0);
    dio_tsf2_tag_secondsh_i                  : in     std_logic_vector(7 downto 0);
    dio_tsf2_tag_cycles_i                    : in     std_logic_vector(27 downto 0);
    irq_nempty_2_i                           : in     std_logic;
-- FIFO write request
    dio_tsf3_wr_req_i                        : in     std_logic;
-- FIFO full flag
    dio_tsf3_wr_full_o                       : out    std_logic;
-- FIFO empty flag
    dio_tsf3_wr_empty_o                      : out    std_logic;
    dio_tsf3_tag_seconds_i                   : in     std_logic_vector(31 downto 0);
    dio_tsf3_tag_secondsh_i                  : in     std_logic_vector(7 downto 0);
    dio_tsf3_tag_cycles_i                    : in     std_logic_vector(27 downto 0);
    irq_nempty_3_i                           : in     std_logic;
-- FIFO write request
    dio_tsf4_wr_req_i                        : in     std_logic;
-- FIFO full flag
    dio_tsf4_wr_full_o                       : out    std_logic;
-- FIFO empty flag
    dio_tsf4_wr_empty_o                      : out    std_logic;
    dio_tsf4_tag_seconds_i                   : in     std_logic_vector(31 downto 0);
    dio_tsf4_tag_secondsh_i                  : in     std_logic_vector(7 downto 0);
    dio_tsf4_tag_cycles_i                    : in     std_logic_vector(27 downto 0);
    irq_nempty_4_i                           : in     std_logic;
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
    dio_trig0_seconds_o                      : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
    dio_trigh0_seconds_o                     : out    std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to  trigger a pulse generation'
    dio_cyc0_cyc_o                           : out    std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
    dio_trig1_seconds_o                      : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
    dio_trigh1_seconds_o                     : out    std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to  trigger a pulse generation'
    dio_cyc1_cyc_o                           : out    std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
    dio_trig2_seconds_o                      : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
    dio_trigh2_seconds_o                     : out    std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to  trigger a pulse generation'
    dio_cyc2_cyc_o                           : out    std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
    dio_trig3_seconds_o                      : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
    dio_trigh3_seconds_o                     : out    std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to  trigger a pulse generation'
    dio_cyc3_cyc_o                           : out    std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
    dio_trig4_seconds_o                      : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
    dio_trigh4_seconds_o                     : out    std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to  trigger a pulse generation'
    dio_cyc4_cyc_o                           : out    std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'outmode' in reg: 'FMC-DIO output configuration register. '
    dio_out_mode_o                           : out    std_logic_vector(4 downto 0);
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
    dio_latch_time_ch0_o                     : out    std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
    dio_latch_time_ch1_o                     : out    std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
    dio_latch_time_ch2_o                     : out    std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
    dio_latch_time_ch3_o                     : out    std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
    dio_latch_time_ch4_o                     : out    std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO time trigger is ready to accept a new trigger generation request'
    dio_trig_rdy_i                           : in     std_logic_vector(4 downto 0);
    irq_trigger_ready_0_i                    : in     std_logic;
    irq_trigger_ready_1_i                    : in     std_logic;
    irq_trigger_ready_2_i                    : in     std_logic;
    irq_trigger_ready_3_i                    : in     std_logic;
    irq_trigger_ready_4_i                    : in     std_logic;
-- Port for std_logic_vector field: 'number of ticks field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse length'
    dio_prog0_pulse_length_o                 : out    std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse length'
    dio_prog1_pulse_length_o                 : out    std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse length'
    dio_prog2_pulse_length_o                 : out    std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse length'
    dio_prog3_pulse_length_o                 : out    std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse length'
    dio_prog4_pulse_length_o                 : out    std_logic_vector(27 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
    dio_pulse_imm_0_o                        : out    std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
    dio_pulse_imm_1_o                        : out    std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
    dio_pulse_imm_2_o                        : out    std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
    dio_pulse_imm_3_o                        : out    std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
    dio_pulse_imm_4_o                        : out    std_logic
  );
end wrsw_dio_wb;

architecture syn of wrsw_dio_wb is

signal dio_tsf0_rst_n                           : std_logic      ;
signal dio_tsf0_in_int                          : std_logic_vector(67 downto 0);
signal dio_tsf0_out_int                         : std_logic_vector(67 downto 0);
signal dio_tsf0_rdreq_int                       : std_logic      ;
signal dio_tsf0_rdreq_int_d0                    : std_logic      ;
signal dio_tsf1_rst_n                           : std_logic      ;
signal dio_tsf1_in_int                          : std_logic_vector(67 downto 0);
signal dio_tsf1_out_int                         : std_logic_vector(67 downto 0);
signal dio_tsf1_rdreq_int                       : std_logic      ;
signal dio_tsf1_rdreq_int_d0                    : std_logic      ;
signal dio_tsf2_rst_n                           : std_logic      ;
signal dio_tsf2_in_int                          : std_logic_vector(67 downto 0);
signal dio_tsf2_out_int                         : std_logic_vector(67 downto 0);
signal dio_tsf2_rdreq_int                       : std_logic      ;
signal dio_tsf2_rdreq_int_d0                    : std_logic      ;
signal dio_tsf3_rst_n                           : std_logic      ;
signal dio_tsf3_in_int                          : std_logic_vector(67 downto 0);
signal dio_tsf3_out_int                         : std_logic_vector(67 downto 0);
signal dio_tsf3_rdreq_int                       : std_logic      ;
signal dio_tsf3_rdreq_int_d0                    : std_logic      ;
signal dio_tsf4_rst_n                           : std_logic      ;
signal dio_tsf4_in_int                          : std_logic_vector(67 downto 0);
signal dio_tsf4_out_int                         : std_logic_vector(67 downto 0);
signal dio_tsf4_rdreq_int                       : std_logic      ;
signal dio_tsf4_rdreq_int_d0                    : std_logic      ;
signal dio_trig0_seconds_int                    : std_logic_vector(31 downto 0);
signal dio_trigh0_seconds_int                   : std_logic_vector(7 downto 0);
signal dio_cyc0_cyc_int                         : std_logic_vector(27 downto 0);
signal dio_trig1_seconds_int                    : std_logic_vector(31 downto 0);
signal dio_trigh1_seconds_int                   : std_logic_vector(7 downto 0);
signal dio_cyc1_cyc_int                         : std_logic_vector(27 downto 0);
signal dio_trig2_seconds_int                    : std_logic_vector(31 downto 0);
signal dio_trigh2_seconds_int                   : std_logic_vector(7 downto 0);
signal dio_cyc2_cyc_int                         : std_logic_vector(27 downto 0);
signal dio_trig3_seconds_int                    : std_logic_vector(31 downto 0);
signal dio_trigh3_seconds_int                   : std_logic_vector(7 downto 0);
signal dio_cyc3_cyc_int                         : std_logic_vector(27 downto 0);
signal dio_trig4_seconds_int                    : std_logic_vector(31 downto 0);
signal dio_trigh4_seconds_int                   : std_logic_vector(7 downto 0);
signal dio_cyc4_cyc_int                         : std_logic_vector(27 downto 0);
signal dio_out_mode_int                         : std_logic_vector(4 downto 0);
signal dio_latch_time_ch0_dly0                  : std_logic      ;
signal dio_latch_time_ch0_int                   : std_logic      ;
signal dio_latch_time_ch1_dly0                  : std_logic      ;
signal dio_latch_time_ch1_int                   : std_logic      ;
signal dio_latch_time_ch2_dly0                  : std_logic      ;
signal dio_latch_time_ch2_int                   : std_logic      ;
signal dio_latch_time_ch3_dly0                  : std_logic      ;
signal dio_latch_time_ch3_int                   : std_logic      ;
signal dio_latch_time_ch4_dly0                  : std_logic      ;
signal dio_latch_time_ch4_int                   : std_logic      ;
signal dio_prog0_pulse_length_int               : std_logic_vector(27 downto 0);
signal dio_prog1_pulse_length_int               : std_logic_vector(27 downto 0);
signal dio_prog2_pulse_length_int               : std_logic_vector(27 downto 0);
signal dio_prog3_pulse_length_int               : std_logic_vector(27 downto 0);
signal dio_prog4_pulse_length_int               : std_logic_vector(27 downto 0);
signal dio_pulse_imm_0_int                      : std_logic      ;
signal dio_pulse_imm_0_int_delay                : std_logic      ;
signal dio_pulse_imm_0_sync0                    : std_logic      ;
signal dio_pulse_imm_0_sync1                    : std_logic      ;
signal dio_pulse_imm_0_sync2                    : std_logic      ;
signal dio_pulse_imm_1_int                      : std_logic      ;
signal dio_pulse_imm_1_int_delay                : std_logic      ;
signal dio_pulse_imm_1_sync0                    : std_logic      ;
signal dio_pulse_imm_1_sync1                    : std_logic      ;
signal dio_pulse_imm_1_sync2                    : std_logic      ;
signal dio_pulse_imm_2_int                      : std_logic      ;
signal dio_pulse_imm_2_int_delay                : std_logic      ;
signal dio_pulse_imm_2_sync0                    : std_logic      ;
signal dio_pulse_imm_2_sync1                    : std_logic      ;
signal dio_pulse_imm_2_sync2                    : std_logic      ;
signal dio_pulse_imm_3_int                      : std_logic      ;
signal dio_pulse_imm_3_int_delay                : std_logic      ;
signal dio_pulse_imm_3_sync0                    : std_logic      ;
signal dio_pulse_imm_3_sync1                    : std_logic      ;
signal dio_pulse_imm_3_sync2                    : std_logic      ;
signal dio_pulse_imm_4_int                      : std_logic      ;
signal dio_pulse_imm_4_int_delay                : std_logic      ;
signal dio_pulse_imm_4_sync0                    : std_logic      ;
signal dio_pulse_imm_4_sync1                    : std_logic      ;
signal dio_pulse_imm_4_sync2                    : std_logic      ;
signal eic_idr_int                              : std_logic_vector(9 downto 0);
signal eic_idr_write_int                        : std_logic      ;
signal eic_ier_int                              : std_logic_vector(9 downto 0);
signal eic_ier_write_int                        : std_logic      ;
signal eic_imr_int                              : std_logic_vector(9 downto 0);
signal eic_isr_clear_int                        : std_logic_vector(9 downto 0);
signal eic_isr_status_int                       : std_logic_vector(9 downto 0);
signal eic_irq_ack_int                          : std_logic_vector(9 downto 0);
signal eic_isr_write_int                        : std_logic      ;
signal dio_tsf0_full_int                        : std_logic      ;
signal dio_tsf0_empty_int                       : std_logic      ;
signal dio_tsf0_usedw_int                       : std_logic_vector(7 downto 0);
signal dio_tsf1_full_int                        : std_logic      ;
signal dio_tsf1_empty_int                       : std_logic      ;
signal dio_tsf1_usedw_int                       : std_logic_vector(7 downto 0);
signal dio_tsf2_full_int                        : std_logic      ;
signal dio_tsf2_empty_int                       : std_logic      ;
signal dio_tsf2_usedw_int                       : std_logic_vector(7 downto 0);
signal dio_tsf3_full_int                        : std_logic      ;
signal dio_tsf3_empty_int                       : std_logic      ;
signal dio_tsf3_usedw_int                       : std_logic_vector(7 downto 0);
signal dio_tsf4_full_int                        : std_logic      ;
signal dio_tsf4_empty_int                       : std_logic      ;
signal dio_tsf4_usedw_int                       : std_logic_vector(7 downto 0);
signal irq_inputs_vector_int                    : std_logic_vector(9 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(5 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      dio_trig0_seconds_int <= "00000000000000000000000000000000";
      dio_trigh0_seconds_int <= "00000000";
      dio_cyc0_cyc_int <= "0000000000000000000000000000";
      dio_trig1_seconds_int <= "00000000000000000000000000000000";
      dio_trigh1_seconds_int <= "00000000";
      dio_cyc1_cyc_int <= "0000000000000000000000000000";
      dio_trig2_seconds_int <= "00000000000000000000000000000000";
      dio_trigh2_seconds_int <= "00000000";
      dio_cyc2_cyc_int <= "0000000000000000000000000000";
      dio_trig3_seconds_int <= "00000000000000000000000000000000";
      dio_trigh3_seconds_int <= "00000000";
      dio_cyc3_cyc_int <= "0000000000000000000000000000";
      dio_trig4_seconds_int <= "00000000000000000000000000000000";
      dio_trigh4_seconds_int <= "00000000";
      dio_cyc4_cyc_int <= "0000000000000000000000000000";
      dio_out_mode_int <= "00000";
      dio_latch_time_ch0_int <= '0';
      dio_latch_time_ch1_int <= '0';
      dio_latch_time_ch2_int <= '0';
      dio_latch_time_ch3_int <= '0';
      dio_latch_time_ch4_int <= '0';
      dio_prog0_pulse_length_int <= "0000000000000000000000000000";
      dio_prog1_pulse_length_int <= "0000000000000000000000000000";
      dio_prog2_pulse_length_int <= "0000000000000000000000000000";
      dio_prog3_pulse_length_int <= "0000000000000000000000000000";
      dio_prog4_pulse_length_int <= "0000000000000000000000000000";
      dio_pulse_imm_0_int <= '0';
      dio_pulse_imm_0_int_delay <= '0';
      dio_pulse_imm_1_int <= '0';
      dio_pulse_imm_1_int_delay <= '0';
      dio_pulse_imm_2_int <= '0';
      dio_pulse_imm_2_int_delay <= '0';
      dio_pulse_imm_3_int <= '0';
      dio_pulse_imm_3_int_delay <= '0';
      dio_pulse_imm_4_int <= '0';
      dio_pulse_imm_4_int_delay <= '0';
      eic_idr_write_int <= '0';
      eic_ier_write_int <= '0';
      eic_isr_write_int <= '0';
      dio_tsf0_rdreq_int <= '0';
      dio_tsf1_rdreq_int <= '0';
      dio_tsf2_rdreq_int <= '0';
      dio_tsf3_rdreq_int <= '0';
      dio_tsf4_rdreq_int <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          dio_latch_time_ch0_int <= '0';
          dio_latch_time_ch1_int <= '0';
          dio_latch_time_ch2_int <= '0';
          dio_latch_time_ch3_int <= '0';
          dio_latch_time_ch4_int <= '0';
          eic_idr_write_int <= '0';
          eic_ier_write_int <= '0';
          eic_isr_write_int <= '0';
          ack_in_progress <= '0';
        else
          dio_pulse_imm_0_int <= dio_pulse_imm_0_int_delay;
          dio_pulse_imm_0_int_delay <= '0';
          dio_pulse_imm_1_int <= dio_pulse_imm_1_int_delay;
          dio_pulse_imm_1_int_delay <= '0';
          dio_pulse_imm_2_int <= dio_pulse_imm_2_int_delay;
          dio_pulse_imm_2_int_delay <= '0';
          dio_pulse_imm_3_int <= dio_pulse_imm_3_int_delay;
          dio_pulse_imm_3_int_delay <= '0';
          dio_pulse_imm_4_int <= dio_pulse_imm_4_int_delay;
          dio_pulse_imm_4_int_delay <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(5 downto 0) is
          when "000000" => 
            if (wb_we_i = '1') then
              dio_trig0_seconds_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= dio_trig0_seconds_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000001" => 
            if (wb_we_i = '1') then
              dio_trigh0_seconds_int <= wrdata_reg(7 downto 0);
            end if;
            rddata_reg(7 downto 0) <= dio_trigh0_seconds_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000010" => 
            if (wb_we_i = '1') then
              dio_cyc0_cyc_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= dio_cyc0_cyc_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000011" => 
            if (wb_we_i = '1') then
              dio_trig1_seconds_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= dio_trig1_seconds_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000100" => 
            if (wb_we_i = '1') then
              dio_trigh1_seconds_int <= wrdata_reg(7 downto 0);
            end if;
            rddata_reg(7 downto 0) <= dio_trigh1_seconds_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000101" => 
            if (wb_we_i = '1') then
              dio_cyc1_cyc_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= dio_cyc1_cyc_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000110" => 
            if (wb_we_i = '1') then
              dio_trig2_seconds_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= dio_trig2_seconds_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000111" => 
            if (wb_we_i = '1') then
              dio_trigh2_seconds_int <= wrdata_reg(7 downto 0);
            end if;
            rddata_reg(7 downto 0) <= dio_trigh2_seconds_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001000" => 
            if (wb_we_i = '1') then
              dio_cyc2_cyc_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= dio_cyc2_cyc_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001001" => 
            if (wb_we_i = '1') then
              dio_trig3_seconds_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= dio_trig3_seconds_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001010" => 
            if (wb_we_i = '1') then
              dio_trigh3_seconds_int <= wrdata_reg(7 downto 0);
            end if;
            rddata_reg(7 downto 0) <= dio_trigh3_seconds_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001011" => 
            if (wb_we_i = '1') then
              dio_cyc3_cyc_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= dio_cyc3_cyc_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001100" => 
            if (wb_we_i = '1') then
              dio_trig4_seconds_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= dio_trig4_seconds_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001101" => 
            if (wb_we_i = '1') then
              dio_trigh4_seconds_int <= wrdata_reg(7 downto 0);
            end if;
            rddata_reg(7 downto 0) <= dio_trigh4_seconds_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001110" => 
            if (wb_we_i = '1') then
              dio_cyc4_cyc_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= dio_cyc4_cyc_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001111" => 
            if (wb_we_i = '1') then
              dio_out_mode_int <= wrdata_reg(4 downto 0);
            end if;
            rddata_reg(4 downto 0) <= dio_out_mode_int;
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010000" => 
            if (wb_we_i = '1') then
              dio_latch_time_ch0_int <= wrdata_reg(0);
              dio_latch_time_ch1_int <= wrdata_reg(1);
              dio_latch_time_ch2_int <= wrdata_reg(2);
              dio_latch_time_ch3_int <= wrdata_reg(3);
              dio_latch_time_ch4_int <= wrdata_reg(4);
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "010001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(4 downto 0) <= dio_trig_rdy_i;
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010010" => 
            if (wb_we_i = '1') then
              dio_prog0_pulse_length_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= dio_prog0_pulse_length_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010011" => 
            if (wb_we_i = '1') then
              dio_prog1_pulse_length_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= dio_prog1_pulse_length_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010100" => 
            if (wb_we_i = '1') then
              dio_prog2_pulse_length_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= dio_prog2_pulse_length_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010101" => 
            if (wb_we_i = '1') then
              dio_prog3_pulse_length_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= dio_prog3_pulse_length_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010110" => 
            if (wb_we_i = '1') then
              dio_prog4_pulse_length_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= dio_prog4_pulse_length_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010111" => 
            if (wb_we_i = '1') then
              dio_pulse_imm_0_int <= wrdata_reg(0);
              dio_pulse_imm_0_int_delay <= wrdata_reg(0);
              dio_pulse_imm_1_int <= wrdata_reg(1);
              dio_pulse_imm_1_int_delay <= wrdata_reg(1);
              dio_pulse_imm_2_int <= wrdata_reg(2);
              dio_pulse_imm_2_int_delay <= wrdata_reg(2);
              dio_pulse_imm_3_int <= wrdata_reg(3);
              dio_pulse_imm_3_int_delay <= wrdata_reg(3);
              dio_pulse_imm_4_int <= wrdata_reg(4);
              dio_pulse_imm_4_int_delay <= wrdata_reg(4);
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "011000" => 
            if (wb_we_i = '1') then
              eic_idr_write_int <= '1';
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011001" => 
            if (wb_we_i = '1') then
              eic_ier_write_int <= '1';
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(9 downto 0) <= eic_imr_int(9 downto 0);
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011011" => 
            if (wb_we_i = '1') then
              eic_isr_write_int <= '1';
            end if;
            rddata_reg(9 downto 0) <= eic_isr_status_int(9 downto 0);
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011100" => 
            if (wb_we_i = '1') then
            end if;
            if (dio_tsf0_rdreq_int_d0 = '0') then
              dio_tsf0_rdreq_int <= not dio_tsf0_rdreq_int;
            else
              rddata_reg(31 downto 0) <= dio_tsf0_out_int(31 downto 0);
              ack_in_progress <= '1';
              ack_sreg(0) <= '1';
            end if;
          when "011101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= dio_tsf0_out_int(39 downto 32);
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= dio_tsf0_out_int(67 downto 40);
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(16) <= dio_tsf0_full_int;
            rddata_reg(17) <= dio_tsf0_empty_int;
            rddata_reg(7 downto 0) <= dio_tsf0_usedw_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100000" => 
            if (wb_we_i = '1') then
            end if;
            if (dio_tsf1_rdreq_int_d0 = '0') then
              dio_tsf1_rdreq_int <= not dio_tsf1_rdreq_int;
            else
              rddata_reg(31 downto 0) <= dio_tsf1_out_int(31 downto 0);
              ack_in_progress <= '1';
              ack_sreg(0) <= '1';
            end if;
          when "100001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= dio_tsf1_out_int(39 downto 32);
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= dio_tsf1_out_int(67 downto 40);
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(16) <= dio_tsf1_full_int;
            rddata_reg(17) <= dio_tsf1_empty_int;
            rddata_reg(7 downto 0) <= dio_tsf1_usedw_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100100" => 
            if (wb_we_i = '1') then
            end if;
            if (dio_tsf2_rdreq_int_d0 = '0') then
              dio_tsf2_rdreq_int <= not dio_tsf2_rdreq_int;
            else
              rddata_reg(31 downto 0) <= dio_tsf2_out_int(31 downto 0);
              ack_in_progress <= '1';
              ack_sreg(0) <= '1';
            end if;
          when "100101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= dio_tsf2_out_int(39 downto 32);
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= dio_tsf2_out_int(67 downto 40);
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(16) <= dio_tsf2_full_int;
            rddata_reg(17) <= dio_tsf2_empty_int;
            rddata_reg(7 downto 0) <= dio_tsf2_usedw_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101000" => 
            if (wb_we_i = '1') then
            end if;
            if (dio_tsf3_rdreq_int_d0 = '0') then
              dio_tsf3_rdreq_int <= not dio_tsf3_rdreq_int;
            else
              rddata_reg(31 downto 0) <= dio_tsf3_out_int(31 downto 0);
              ack_in_progress <= '1';
              ack_sreg(0) <= '1';
            end if;
          when "101001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= dio_tsf3_out_int(39 downto 32);
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= dio_tsf3_out_int(67 downto 40);
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(16) <= dio_tsf3_full_int;
            rddata_reg(17) <= dio_tsf3_empty_int;
            rddata_reg(7 downto 0) <= dio_tsf3_usedw_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101100" => 
            if (wb_we_i = '1') then
            end if;
            if (dio_tsf4_rdreq_int_d0 = '0') then
              dio_tsf4_rdreq_int <= not dio_tsf4_rdreq_int;
            else
              rddata_reg(31 downto 0) <= dio_tsf4_out_int(31 downto 0);
              ack_in_progress <= '1';
              ack_sreg(0) <= '1';
            end if;
          when "101101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= dio_tsf4_out_int(39 downto 32);
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(27 downto 0) <= dio_tsf4_out_int(67 downto 40);
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(16) <= dio_tsf4_full_int;
            rddata_reg(17) <= dio_tsf4_empty_int;
            rddata_reg(7 downto 0) <= dio_tsf4_usedw_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Timestamp FIFO 0
  dio_tsf0_in_int(31 downto 0) <= dio_tsf0_tag_seconds_i;
  dio_tsf0_in_int(39 downto 32) <= dio_tsf0_tag_secondsh_i;
  dio_tsf0_in_int(67 downto 40) <= dio_tsf0_tag_cycles_i;
  dio_tsf0_rst_n <= rst_n_i;
  dio_tsf0_INST : wbgen2_fifo_sync
    generic map (
      g_size               => 256,
      g_width              => 68,
      g_usedw_size         => 8
    )
    port map (
      wr_req_i             => dio_tsf0_wr_req_i,
      wr_full_o            => dio_tsf0_wr_full_o,
      wr_empty_o           => dio_tsf0_wr_empty_o,
      rd_full_o            => dio_tsf0_full_int,
      rd_empty_o           => dio_tsf0_empty_int,
      rd_usedw_o           => dio_tsf0_usedw_int,
      rd_req_i             => dio_tsf0_rdreq_int,
      rst_n_i              => dio_tsf0_rst_n,
      clk_i                => clk_sys_i,
      wr_data_i            => dio_tsf0_in_int,
      rd_data_o            => dio_tsf0_out_int
    );
  
-- extra code for reg/fifo/mem: Timestamp FIFO 1
  dio_tsf1_in_int(31 downto 0) <= dio_tsf1_tag_seconds_i;
  dio_tsf1_in_int(39 downto 32) <= dio_tsf1_tag_secondsh_i;
  dio_tsf1_in_int(67 downto 40) <= dio_tsf1_tag_cycles_i;
  dio_tsf1_rst_n <= rst_n_i;
  dio_tsf1_INST : wbgen2_fifo_sync
    generic map (
      g_size               => 256,
      g_width              => 68,
      g_usedw_size         => 8
    )
    port map (
      wr_req_i             => dio_tsf1_wr_req_i,
      wr_full_o            => dio_tsf1_wr_full_o,
      wr_empty_o           => dio_tsf1_wr_empty_o,
      rd_full_o            => dio_tsf1_full_int,
      rd_empty_o           => dio_tsf1_empty_int,
      rd_usedw_o           => dio_tsf1_usedw_int,
      rd_req_i             => dio_tsf1_rdreq_int,
      rst_n_i              => dio_tsf1_rst_n,
      clk_i                => clk_sys_i,
      wr_data_i            => dio_tsf1_in_int,
      rd_data_o            => dio_tsf1_out_int
    );
  
-- extra code for reg/fifo/mem: Timestamp FIFO 2
  dio_tsf2_in_int(31 downto 0) <= dio_tsf2_tag_seconds_i;
  dio_tsf2_in_int(39 downto 32) <= dio_tsf2_tag_secondsh_i;
  dio_tsf2_in_int(67 downto 40) <= dio_tsf2_tag_cycles_i;
  dio_tsf2_rst_n <= rst_n_i;
  dio_tsf2_INST : wbgen2_fifo_sync
    generic map (
      g_size               => 256,
      g_width              => 68,
      g_usedw_size         => 8
    )
    port map (
      wr_req_i             => dio_tsf2_wr_req_i,
      wr_full_o            => dio_tsf2_wr_full_o,
      wr_empty_o           => dio_tsf2_wr_empty_o,
      rd_full_o            => dio_tsf2_full_int,
      rd_empty_o           => dio_tsf2_empty_int,
      rd_usedw_o           => dio_tsf2_usedw_int,
      rd_req_i             => dio_tsf2_rdreq_int,
      rst_n_i              => dio_tsf2_rst_n,
      clk_i                => clk_sys_i,
      wr_data_i            => dio_tsf2_in_int,
      rd_data_o            => dio_tsf2_out_int
    );
  
-- extra code for reg/fifo/mem: Timestamp FIFO 3
  dio_tsf3_in_int(31 downto 0) <= dio_tsf3_tag_seconds_i;
  dio_tsf3_in_int(39 downto 32) <= dio_tsf3_tag_secondsh_i;
  dio_tsf3_in_int(67 downto 40) <= dio_tsf3_tag_cycles_i;
  dio_tsf3_rst_n <= rst_n_i;
  dio_tsf3_INST : wbgen2_fifo_sync
    generic map (
      g_size               => 256,
      g_width              => 68,
      g_usedw_size         => 8
    )
    port map (
      wr_req_i             => dio_tsf3_wr_req_i,
      wr_full_o            => dio_tsf3_wr_full_o,
      wr_empty_o           => dio_tsf3_wr_empty_o,
      rd_full_o            => dio_tsf3_full_int,
      rd_empty_o           => dio_tsf3_empty_int,
      rd_usedw_o           => dio_tsf3_usedw_int,
      rd_req_i             => dio_tsf3_rdreq_int,
      rst_n_i              => dio_tsf3_rst_n,
      clk_i                => clk_sys_i,
      wr_data_i            => dio_tsf3_in_int,
      rd_data_o            => dio_tsf3_out_int
    );
  
-- extra code for reg/fifo/mem: Timestamp FIFO 4
  dio_tsf4_in_int(31 downto 0) <= dio_tsf4_tag_seconds_i;
  dio_tsf4_in_int(39 downto 32) <= dio_tsf4_tag_secondsh_i;
  dio_tsf4_in_int(67 downto 40) <= dio_tsf4_tag_cycles_i;
  dio_tsf4_rst_n <= rst_n_i;
  dio_tsf4_INST : wbgen2_fifo_sync
    generic map (
      g_size               => 256,
      g_width              => 68,
      g_usedw_size         => 8
    )
    port map (
      wr_req_i             => dio_tsf4_wr_req_i,
      wr_full_o            => dio_tsf4_wr_full_o,
      wr_empty_o           => dio_tsf4_wr_empty_o,
      rd_full_o            => dio_tsf4_full_int,
      rd_empty_o           => dio_tsf4_empty_int,
      rd_usedw_o           => dio_tsf4_usedw_int,
      rd_req_i             => dio_tsf4_rdreq_int,
      rst_n_i              => dio_tsf4_rst_n,
      clk_i                => clk_sys_i,
      wr_data_i            => dio_tsf4_in_int,
      rd_data_o            => dio_tsf4_out_int
    );
  
-- seconds field
  dio_trig0_seconds_o <= dio_trig0_seconds_int;
-- seconds field
  dio_trigh0_seconds_o <= dio_trigh0_seconds_int;
-- cycles field
  dio_cyc0_cyc_o <= dio_cyc0_cyc_int;
-- seconds field
  dio_trig1_seconds_o <= dio_trig1_seconds_int;
-- seconds field
  dio_trigh1_seconds_o <= dio_trigh1_seconds_int;
-- cycles field
  dio_cyc1_cyc_o <= dio_cyc1_cyc_int;
-- seconds field
  dio_trig2_seconds_o <= dio_trig2_seconds_int;
-- seconds field
  dio_trigh2_seconds_o <= dio_trigh2_seconds_int;
-- cycles field
  dio_cyc2_cyc_o <= dio_cyc2_cyc_int;
-- seconds field
  dio_trig3_seconds_o <= dio_trig3_seconds_int;
-- seconds field
  dio_trigh3_seconds_o <= dio_trigh3_seconds_int;
-- cycles field
  dio_cyc3_cyc_o <= dio_cyc3_cyc_int;
-- seconds field
  dio_trig4_seconds_o <= dio_trig4_seconds_int;
-- seconds field
  dio_trigh4_seconds_o <= dio_trigh4_seconds_int;
-- cycles field
  dio_cyc4_cyc_o <= dio_cyc4_cyc_int;
-- outmode
  dio_out_mode_o <= dio_out_mode_int;
-- Sincle-cycle strobe
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_latch_time_ch0_dly0 <= '0';
      dio_latch_time_ch0_o <= '0';
    elsif rising_edge(clk_sys_i) then
      dio_latch_time_ch0_dly0 <= dio_latch_time_ch0_int;
      dio_latch_time_ch0_o <= dio_latch_time_ch0_int and (not dio_latch_time_ch0_dly0);
    end if;
  end process;
  
  
-- Sincle-cycle strobe
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_latch_time_ch1_dly0 <= '0';
      dio_latch_time_ch1_o <= '0';
    elsif rising_edge(clk_sys_i) then
      dio_latch_time_ch1_dly0 <= dio_latch_time_ch1_int;
      dio_latch_time_ch1_o <= dio_latch_time_ch1_int and (not dio_latch_time_ch1_dly0);
    end if;
  end process;
  
  
-- Sincle-cycle strobe
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_latch_time_ch2_dly0 <= '0';
      dio_latch_time_ch2_o <= '0';
    elsif rising_edge(clk_sys_i) then
      dio_latch_time_ch2_dly0 <= dio_latch_time_ch2_int;
      dio_latch_time_ch2_o <= dio_latch_time_ch2_int and (not dio_latch_time_ch2_dly0);
    end if;
  end process;
  
  
-- Sincle-cycle strobe
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_latch_time_ch3_dly0 <= '0';
      dio_latch_time_ch3_o <= '0';
    elsif rising_edge(clk_sys_i) then
      dio_latch_time_ch3_dly0 <= dio_latch_time_ch3_int;
      dio_latch_time_ch3_o <= dio_latch_time_ch3_int and (not dio_latch_time_ch3_dly0);
    end if;
  end process;
  
  
-- Sincle-cycle strobe
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_latch_time_ch4_dly0 <= '0';
      dio_latch_time_ch4_o <= '0';
    elsif rising_edge(clk_sys_i) then
      dio_latch_time_ch4_dly0 <= dio_latch_time_ch4_int;
      dio_latch_time_ch4_o <= dio_latch_time_ch4_int and (not dio_latch_time_ch4_dly0);
    end if;
  end process;
  
  
-- trig_rdy field
-- number of ticks field for channel 0
  dio_prog0_pulse_length_o <= dio_prog0_pulse_length_int;
-- number of ticks field for channel 1
  dio_prog1_pulse_length_o <= dio_prog1_pulse_length_int;
-- number of ticks field for channel 2
  dio_prog2_pulse_length_o <= dio_prog2_pulse_length_int;
-- number of ticks field for channel 3
  dio_prog3_pulse_length_o <= dio_prog3_pulse_length_int;
-- number of ticks field for channel 4
  dio_prog4_pulse_length_o <= dio_prog4_pulse_length_int;
-- pulse_gen_now_0
  process (clk_asyn_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_pulse_imm_0_o <= '0';
      dio_pulse_imm_0_sync0 <= '0';
      dio_pulse_imm_0_sync1 <= '0';
      dio_pulse_imm_0_sync2 <= '0';
    elsif rising_edge(clk_asyn_i) then
      dio_pulse_imm_0_sync0 <= dio_pulse_imm_0_int;
      dio_pulse_imm_0_sync1 <= dio_pulse_imm_0_sync0;
      dio_pulse_imm_0_sync2 <= dio_pulse_imm_0_sync1;
      dio_pulse_imm_0_o <= dio_pulse_imm_0_sync2 and (not dio_pulse_imm_0_sync1);
    end if;
  end process;
  
  
-- pulse_gen_now_1
  process (clk_asyn_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_pulse_imm_1_o <= '0';
      dio_pulse_imm_1_sync0 <= '0';
      dio_pulse_imm_1_sync1 <= '0';
      dio_pulse_imm_1_sync2 <= '0';
    elsif rising_edge(clk_asyn_i) then
      dio_pulse_imm_1_sync0 <= dio_pulse_imm_1_int;
      dio_pulse_imm_1_sync1 <= dio_pulse_imm_1_sync0;
      dio_pulse_imm_1_sync2 <= dio_pulse_imm_1_sync1;
      dio_pulse_imm_1_o <= dio_pulse_imm_1_sync2 and (not dio_pulse_imm_1_sync1);
    end if;
  end process;
  
  
-- pulse_gen_now_2
  process (clk_asyn_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_pulse_imm_2_o <= '0';
      dio_pulse_imm_2_sync0 <= '0';
      dio_pulse_imm_2_sync1 <= '0';
      dio_pulse_imm_2_sync2 <= '0';
    elsif rising_edge(clk_asyn_i) then
      dio_pulse_imm_2_sync0 <= dio_pulse_imm_2_int;
      dio_pulse_imm_2_sync1 <= dio_pulse_imm_2_sync0;
      dio_pulse_imm_2_sync2 <= dio_pulse_imm_2_sync1;
      dio_pulse_imm_2_o <= dio_pulse_imm_2_sync2 and (not dio_pulse_imm_2_sync1);
    end if;
  end process;
  
  
-- pulse_gen_now_3
  process (clk_asyn_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_pulse_imm_3_o <= '0';
      dio_pulse_imm_3_sync0 <= '0';
      dio_pulse_imm_3_sync1 <= '0';
      dio_pulse_imm_3_sync2 <= '0';
    elsif rising_edge(clk_asyn_i) then
      dio_pulse_imm_3_sync0 <= dio_pulse_imm_3_int;
      dio_pulse_imm_3_sync1 <= dio_pulse_imm_3_sync0;
      dio_pulse_imm_3_sync2 <= dio_pulse_imm_3_sync1;
      dio_pulse_imm_3_o <= dio_pulse_imm_3_sync2 and (not dio_pulse_imm_3_sync1);
    end if;
  end process;
  
  
-- pulse_gen_now_4
  process (clk_asyn_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_pulse_imm_4_o <= '0';
      dio_pulse_imm_4_sync0 <= '0';
      dio_pulse_imm_4_sync1 <= '0';
      dio_pulse_imm_4_sync2 <= '0';
    elsif rising_edge(clk_asyn_i) then
      dio_pulse_imm_4_sync0 <= dio_pulse_imm_4_int;
      dio_pulse_imm_4_sync1 <= dio_pulse_imm_4_sync0;
      dio_pulse_imm_4_sync2 <= dio_pulse_imm_4_sync1;
      dio_pulse_imm_4_o <= dio_pulse_imm_4_sync2 and (not dio_pulse_imm_4_sync1);
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: Interrupt disable register
  eic_idr_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
  eic_ier_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
  eic_isr_clear_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
  eic_irq_controller_inst : wbgen2_eic
    generic map (
      g_num_interrupts     => 10,
      g_irq00_mode         => 3,
      g_irq01_mode         => 3,
      g_irq02_mode         => 3,
      g_irq03_mode         => 3,
      g_irq04_mode         => 3,
      g_irq05_mode         => 3,
      g_irq06_mode         => 3,
      g_irq07_mode         => 3,
      g_irq08_mode         => 3,
      g_irq09_mode         => 3,
      g_irq0a_mode         => 0,
      g_irq0b_mode         => 0,
      g_irq0c_mode         => 0,
      g_irq0d_mode         => 0,
      g_irq0e_mode         => 0,
      g_irq0f_mode         => 0,
      g_irq10_mode         => 0,
      g_irq11_mode         => 0,
      g_irq12_mode         => 0,
      g_irq13_mode         => 0,
      g_irq14_mode         => 0,
      g_irq15_mode         => 0,
      g_irq16_mode         => 0,
      g_irq17_mode         => 0,
      g_irq18_mode         => 0,
      g_irq19_mode         => 0,
      g_irq1a_mode         => 0,
      g_irq1b_mode         => 0,
      g_irq1c_mode         => 0,
      g_irq1d_mode         => 0,
      g_irq1e_mode         => 0,
      g_irq1f_mode         => 0
    )
    port map (
      clk_i                => clk_sys_i,
      rst_n_i              => rst_n_i,
      irq_i                => irq_inputs_vector_int,
      irq_ack_o            => eic_irq_ack_int,
      reg_imr_o            => eic_imr_int,
      reg_ier_i            => eic_ier_int,
      reg_ier_wr_stb_i     => eic_ier_write_int,
      reg_idr_i            => eic_idr_int,
      reg_idr_wr_stb_i     => eic_idr_write_int,
      reg_isr_o            => eic_isr_status_int,
      reg_isr_i            => eic_isr_clear_int,
      reg_isr_wr_stb_i     => eic_isr_write_int,
      wb_irq_o             => wb_int_o
    );
  
  irq_inputs_vector_int(0) <= irq_nempty_0_i;
  irq_inputs_vector_int(1) <= irq_nempty_1_i;
  irq_inputs_vector_int(2) <= irq_nempty_2_i;
  irq_inputs_vector_int(3) <= irq_nempty_3_i;
  irq_inputs_vector_int(4) <= irq_nempty_4_i;
  irq_inputs_vector_int(5) <= irq_trigger_ready_0_i;
  irq_inputs_vector_int(6) <= irq_trigger_ready_1_i;
  irq_inputs_vector_int(7) <= irq_trigger_ready_2_i;
  irq_inputs_vector_int(8) <= irq_trigger_ready_3_i;
  irq_inputs_vector_int(9) <= irq_trigger_ready_4_i;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 0
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_tsf0_rdreq_int_d0 <= '0';
    elsif rising_edge(clk_sys_i) then
      dio_tsf0_rdreq_int_d0 <= dio_tsf0_rdreq_int;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 0
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_tsf1_rdreq_int_d0 <= '0';
    elsif rising_edge(clk_sys_i) then
      dio_tsf1_rdreq_int_d0 <= dio_tsf1_rdreq_int;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 0
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_tsf2_rdreq_int_d0 <= '0';
    elsif rising_edge(clk_sys_i) then
      dio_tsf2_rdreq_int_d0 <= dio_tsf2_rdreq_int;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 0
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_tsf3_rdreq_int_d0 <= '0';
    elsif rising_edge(clk_sys_i) then
      dio_tsf3_rdreq_int_d0 <= dio_tsf3_rdreq_int;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 0
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dio_tsf4_rdreq_int_d0 <= '0';
    elsif rising_edge(clk_sys_i) then
      dio_tsf4_rdreq_int_d0 <= dio_tsf4_rdreq_int;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 2
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
