update submodules

0459bdfe · Grzegorz Daniluk · c67e374d · 0aafd085 · c3cddd41 · 0459bdfe
Commit 0459bdfe authored Jul 05, 2013 by Grzegorz Daniluk
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wr-cores ip_cores/wr-cores +1 -1

wr-switch-hdl ip_cores/wr-switch-hdl +1 -1

wr_nic_sdb_top.ucf top/spec/wr_nic_sdb_top.ucf +0 -1

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--- a/wr-cores @ 0aafd085
+++ b/wr-cores @ 0aafd085
-Subproject commit fd76aee4277f68116169e6a6fca232de28b752bf
+Subproject commit 0aafd085c14f0629a9ae4dce6e3efaacb48d8f43
--- a/wr-switch-hdl @ c3cddd41
+++ b/wr-switch-hdl @ c3cddd41
-Subproject commit ea1c71522755f7b58bf44d81a67b3c71e02cef8b
+Subproject commit c3cddd413f100f79cd4e686bb458858bed12d63c
--- a/top/spec/wr_nic_sdb_top.ucf
+++ b/top/spec/wr_nic_sdb_top.ucf
@@ -632,7 +632,6 @@ NET "fpga_pll_ref_clk_101_n_i" TNM_NET = fpga_pll_ref_clk_101_n_i;
 TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HIGH 50%;

 PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; 
-PIN "U_GTP/U_Rbclk_bufg_ch1.O" CLOCK_DEDICATED_ROUTE = FALSE;

 #Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09