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White Rabbit Network Interface Card
Commit 14344d2e authored by Benoit Rat's avatar Benoit Rat Committed by Miguel Jimenez Lopez
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dio: try to correct PPS output. 

We have remove all connections (input and output) of first channel to the DIO.
In the future we might re-add the input connection...
parent 4dfdcc30
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Showing with 49 additions and 22 deletions
modules/wrsw_dio/wrsw_dio.vhd
View file @ 14344d2e
......@@ -40,7 +40,7 @@ entity wrsw_dio is
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
-- dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
......@@ -97,7 +97,7 @@ architecture rtl of wrsw_dio is
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
-- dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
......@@ -142,7 +142,7 @@ U_WRAPPER_DIO : xwrsw_dio
rst_n_i => rst_n_i,
dio_clk_i => dio_clk_i,
dio_pps_i => dio_pps_i,
-- dio_pps_i => dio_pps_i,
dio_in_i => dio_in_i,
dio_out_o => dio_out_o,
dio_oe_n_o => dio_oe_n_o,
......
modules/wrsw_dio/xwrsw_dio.vhd
View file @ 14344d2e
......@@ -52,7 +52,7 @@ entity xwrsw_dio is
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
--dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
......@@ -621,11 +621,15 @@ begin
select dio_out_o(i) <=
gpio_out(c_IOMODE_NB*i) when "00", --GPIO out as also 4 bits per channel
dio_pulse(i) when "01",
dio_pps_i when "10",
--dio_pps_i when "10",
'1' when others; --Error output will stay at one (similar as GPIO set to one)
end generate gen_pio_assignment;
dio_led_bot_o <= gpio_out(28);
dio_led_bot_o <= dio_iomode_reg(c_IOMODE_NB*0+3) OR
dio_iomode_reg(c_IOMODE_NB*1+3) OR
dio_iomode_reg(c_IOMODE_NB*2+3) OR
dio_iomode_reg(c_IOMODE_NB*3+3) OR
dio_iomode_reg(c_IOMODE_NB*4+3);
dio_led_top_o <= gpio_out(27);
--gpio_in(29) <= dio_clk_i;
......
top/specdio/wr_nic_dio_top.ucf
View file @ 14344d2e
......@@ -591,10 +591,10 @@ NET "dio_p_i[1]" IOSTANDARD=LVDS_25;
NET "dio_n_i[1]" LOC =T11;
NET "dio_n_i[1]" IOSTANDARD=LVDS_25;
NET "dio_p_i[0]" LOC =C19;
NET "dio_p_i[0]" IOSTANDARD=LVDS_25;
NET "dio_n_i[0]" LOC =A19;
NET "dio_n_i[0]" IOSTANDARD=LVDS_25;
# NET "dio_p_i[0]" LOC =C19;
# NET "dio_p_i[0]" IOSTANDARD=LVDS_25;
# NET "dio_n_i[0]" LOC =A19;
# NET "dio_n_i[0]" IOSTANDARD=LVDS_25;
NET "dio_led_top_o" LOC= AA12;
NET "dio_led_top_o" IOSTANDARD=LVCMOS25;
......
top/specdio/wr_nic_dio_top.vhd
View file @ 14344d2e
......@@ -378,7 +378,7 @@ architecture rtl of wr_nic_dio_top is
rst_n_i : in std_logic;
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
--dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
......@@ -502,7 +502,7 @@ architecture rtl of wr_nic_dio_top is
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal pps : std_logic;
--signal pps : std_logic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
......@@ -516,9 +516,14 @@ architecture rtl of wr_nic_dio_top is
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal dio_clk : std_logic;
signal dio_in : std_logic_vector(4 downto 1);
signal dio_out : std_logic_vector(4 downto 1);
--first channel is reserved for PPS out
signal dio_out_pps : std_logic;
-- attribute iob: string;
-- attribute iob of dio_out_pps: signal is "true";
signal local_reset_n : std_logic;
signal button1_synced : std_logic_vector(2 downto 0);
......@@ -928,7 +933,7 @@ begin
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_seconds,
tm_cycles_o => tm_cycles,
pps_p_o => pps,
pps_p_o => dio_out_pps,
dio_o => open,
rst_aux_n_o => open
......@@ -1101,12 +1106,17 @@ begin
clk_ref_i => clk_125m_pllref,
rst_n_i => local_reset_n,
dio_clk_i => dio_clk,
dio_pps_i => pps,
dio_in_i => dio_in,
dio_out_o => dio_out,
dio_oe_n_o => dio_oe_n_o,
dio_term_en_o => dio_term_en_o,
dio_clk_i => dio_clk,
--dio_pps_i => dio_out_pps, --CHECK
--Connect only the last 4 channels to not disturb pps_out
--and keep generic dio_core
dio_in_i(0) => open,
dio_in_i(4 downto 1) => dio_in,
dio_out_o(0) => open,
dio_out_o(4 downto 1) => dio_out,
dio_oe_n_o(0) => open,
dio_oe_n_o(4 downto 1) => dio_oe_n_o(4 downto 1),
dio_term_en_o => dio_term_en_o,
dio_onewire_b => dio_onewire_b,
dio_sdn_n_o => dio_sdn_n_o,
......@@ -1132,7 +1142,7 @@ begin
-- TRIG3 => TRIG3,
);
gen_dio_iobufs : for i in 0 to 4 generate
gen_dio_iobufs : for i in 1 to 4 generate
U_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
......@@ -1149,6 +1159,19 @@ begin
OB => dio_n_o(i)
);
end generate gen_dio_iobufs;
-- first channel is reserved for PPS out only
dio_oe_n_o(0) <= '0';
U_obuf_pps : OBUFDS
port map (
I => dio_out_pps,
O => dio_p_o(0),
OB => dio_n_o(0)
);
--- end specific code for pps_out
U_input_buffer : IBUFDS
generic map (
DIFF_TERM => true)
......
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