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White Rabbit Network Interface Card
Commit 14715d17 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk Committed by Miguel Jimenez Lopez
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include/wbgen-regs: update nic-regs to match HDL

parent 45338156
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kernel/wbgen-regs/nic-regs.h
View file @ 14715d17
......@@ -43,6 +43,12 @@
/* definitions for field: Transmit enable in reg: NIC Control Register */
#define NIC_CR_TX_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Rx bandwidth throttling enable in reg: NIC Control Register */
#define NIC_CR_RXTHR_EN WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Software Reset in reg: NIC Control Register */
#define NIC_CR_SW_RST WBGEN2_GEN_MASK(31, 1)
/* definitions for register: NIC Status Register */
/* definitions for field: Buffer Not Available in reg: NIC Status Register */
......@@ -51,7 +57,27 @@
/* definitions for field: Frame Received in reg: NIC Status Register */
#define NIC_SR_REC WBGEN2_GEN_MASK(1, 1)
/* definitions for register: SW_Reset */
/* definitions for field: Transmission done in reg: NIC Status Register */
#define NIC_SR_TX_DONE WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmission error in reg: NIC Status Register */
#define NIC_SR_TX_ERROR WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Current TX descriptor in reg: NIC Status Register */
#define NIC_SR_CUR_TX_DESC_MASK WBGEN2_GEN_MASK(8, 3)
#define NIC_SR_CUR_TX_DESC_SHIFT 8
#define NIC_SR_CUR_TX_DESC_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define NIC_SR_CUR_TX_DESC_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: Current RX descriptor in reg: NIC Status Register */
#define NIC_SR_CUR_RX_DESC_MASK WBGEN2_GEN_MASK(16, 3)
#define NIC_SR_CUR_RX_DESC_SHIFT 16
#define NIC_SR_CUR_RX_DESC_W(value) WBGEN2_GEN_WRITE(value, 16, 3)
#define NIC_SR_CUR_RX_DESC_R(reg) WBGEN2_GEN_READ(reg, 16, 3)
/* definitions for register: NIC Current Rx Bandwidth Register */
/* definitions for register: NIC Max Rx Bandwidth Register */
/* definitions for register: TX Descriptor 1 register 1 */
......@@ -95,300 +121,6 @@
#define NIC_TX1_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX1_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 2 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX2_D1_TS_ID_SHIFT 16
#define NIC_TX2_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX2_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 2 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 2 register 2 */
#define NIC_TX2_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX2_D2_OFFSET_SHIFT 0
#define NIC_TX2_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX2_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 2 register 2 */
#define NIC_TX2_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX2_D2_LEN_SHIFT 16
#define NIC_TX2_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX2_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 2 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 2 register 3 */
#define NIC_TX2_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX2_D3_DPM_SHIFT 0
#define NIC_TX2_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX2_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 3 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX3_D1_TS_ID_SHIFT 16
#define NIC_TX3_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX3_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 3 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 3 register 2 */
#define NIC_TX3_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX3_D2_OFFSET_SHIFT 0
#define NIC_TX3_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX3_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 3 register 2 */
#define NIC_TX3_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX3_D2_LEN_SHIFT 16
#define NIC_TX3_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX3_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 3 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 3 register 3 */
#define NIC_TX3_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX3_D3_DPM_SHIFT 0
#define NIC_TX3_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX3_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 4 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX4_D1_TS_ID_SHIFT 16
#define NIC_TX4_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX4_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 4 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 4 register 2 */
#define NIC_TX4_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX4_D2_OFFSET_SHIFT 0
#define NIC_TX4_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX4_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 4 register 2 */
#define NIC_TX4_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX4_D2_LEN_SHIFT 16
#define NIC_TX4_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX4_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 4 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 4 register 3 */
#define NIC_TX4_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX4_D3_DPM_SHIFT 0
#define NIC_TX4_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX4_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 5 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX5_D1_TS_ID_SHIFT 16
#define NIC_TX5_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX5_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 5 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 5 register 2 */
#define NIC_TX5_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX5_D2_OFFSET_SHIFT 0
#define NIC_TX5_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX5_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 5 register 2 */
#define NIC_TX5_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX5_D2_LEN_SHIFT 16
#define NIC_TX5_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX5_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 5 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 5 register 3 */
#define NIC_TX5_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX5_D3_DPM_SHIFT 0
#define NIC_TX5_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX5_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 6 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX6_D1_TS_ID_SHIFT 16
#define NIC_TX6_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX6_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 6 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 6 register 2 */
#define NIC_TX6_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX6_D2_OFFSET_SHIFT 0
#define NIC_TX6_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX6_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 6 register 2 */
#define NIC_TX6_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX6_D2_LEN_SHIFT 16
#define NIC_TX6_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX6_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 6 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 6 register 3 */
#define NIC_TX6_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX6_D3_DPM_SHIFT 0
#define NIC_TX6_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX6_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 7 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX7_D1_TS_ID_SHIFT 16
#define NIC_TX7_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX7_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 7 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 7 register 2 */
#define NIC_TX7_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX7_D2_OFFSET_SHIFT 0
#define NIC_TX7_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX7_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 7 register 2 */
#define NIC_TX7_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX7_D2_LEN_SHIFT 16
#define NIC_TX7_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX7_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 7 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 7 register 3 */
#define NIC_TX7_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX7_D3_DPM_SHIFT 0
#define NIC_TX7_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX7_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 8 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX8_D1_TS_ID_SHIFT 16
#define NIC_TX8_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX8_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 8 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 8 register 2 */
#define NIC_TX8_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX8_D2_OFFSET_SHIFT 0
#define NIC_TX8_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX8_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 8 register 2 */
#define NIC_TX8_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX8_D2_LEN_SHIFT 16
#define NIC_TX8_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX8_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 8 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 8 register 3 */
#define NIC_TX8_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX8_D3_DPM_SHIFT 0
#define NIC_TX8_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX8_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: RX Descriptor 1 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 1 register 1 */
......@@ -437,342 +169,6 @@
#define NIC_RX1_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX1_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 2 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX2_D1_PORT_SHIFT 8
#define NIC_RX2_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX2_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 2 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 2 register 2 */
#define NIC_RX2_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX2_D2_TS_R_SHIFT 0
#define NIC_RX2_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX2_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 2 register 2 */
#define NIC_RX2_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX2_D2_TS_F_SHIFT 28
#define NIC_RX2_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX2_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 2 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 2 register 3 */
#define NIC_RX2_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX2_D3_OFFSET_SHIFT 0
#define NIC_RX2_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX2_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 2 register 3 */
#define NIC_RX2_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX2_D3_LEN_SHIFT 16
#define NIC_RX2_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX2_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 3 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX3_D1_PORT_SHIFT 8
#define NIC_RX3_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX3_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 3 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 3 register 2 */
#define NIC_RX3_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX3_D2_TS_R_SHIFT 0
#define NIC_RX3_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX3_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 3 register 2 */
#define NIC_RX3_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX3_D2_TS_F_SHIFT 28
#define NIC_RX3_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX3_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 3 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 3 register 3 */
#define NIC_RX3_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX3_D3_OFFSET_SHIFT 0
#define NIC_RX3_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX3_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 3 register 3 */
#define NIC_RX3_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX3_D3_LEN_SHIFT 16
#define NIC_RX3_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX3_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 4 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX4_D1_PORT_SHIFT 8
#define NIC_RX4_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX4_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 4 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 4 register 2 */
#define NIC_RX4_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX4_D2_TS_R_SHIFT 0
#define NIC_RX4_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX4_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 4 register 2 */
#define NIC_RX4_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX4_D2_TS_F_SHIFT 28
#define NIC_RX4_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX4_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 4 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 4 register 3 */
#define NIC_RX4_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX4_D3_OFFSET_SHIFT 0
#define NIC_RX4_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX4_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 4 register 3 */
#define NIC_RX4_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX4_D3_LEN_SHIFT 16
#define NIC_RX4_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX4_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 5 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX5_D1_PORT_SHIFT 8
#define NIC_RX5_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX5_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 5 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 5 register 2 */
#define NIC_RX5_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX5_D2_TS_R_SHIFT 0
#define NIC_RX5_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX5_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 5 register 2 */
#define NIC_RX5_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX5_D2_TS_F_SHIFT 28
#define NIC_RX5_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX5_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 5 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 5 register 3 */
#define NIC_RX5_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX5_D3_OFFSET_SHIFT 0
#define NIC_RX5_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX5_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 5 register 3 */
#define NIC_RX5_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX5_D3_LEN_SHIFT 16
#define NIC_RX5_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX5_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 6 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX6_D1_PORT_SHIFT 8
#define NIC_RX6_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX6_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 6 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 6 register 2 */
#define NIC_RX6_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX6_D2_TS_R_SHIFT 0
#define NIC_RX6_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX6_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 6 register 2 */
#define NIC_RX6_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX6_D2_TS_F_SHIFT 28
#define NIC_RX6_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX6_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 6 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 6 register 3 */
#define NIC_RX6_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX6_D3_OFFSET_SHIFT 0
#define NIC_RX6_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX6_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 6 register 3 */
#define NIC_RX6_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX6_D3_LEN_SHIFT 16
#define NIC_RX6_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX6_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 7 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX7_D1_PORT_SHIFT 8
#define NIC_RX7_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX7_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 7 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 7 register 2 */
#define NIC_RX7_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX7_D2_TS_R_SHIFT 0
#define NIC_RX7_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX7_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 7 register 2 */
#define NIC_RX7_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX7_D2_TS_F_SHIFT 28
#define NIC_RX7_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX7_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 7 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 7 register 3 */
#define NIC_RX7_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX7_D3_OFFSET_SHIFT 0
#define NIC_RX7_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX7_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 7 register 3 */
#define NIC_RX7_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX7_D3_LEN_SHIFT 16
#define NIC_RX7_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX7_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 8 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX8_D1_PORT_SHIFT 8
#define NIC_RX8_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX8_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 8 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 8 register 2 */
#define NIC_RX8_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX8_D2_TS_R_SHIFT 0
#define NIC_RX8_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX8_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 8 register 2 */
#define NIC_RX8_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX8_D2_TS_F_SHIFT 28
#define NIC_RX8_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX8_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 8 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 8 register 3 */
#define NIC_RX8_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX8_D3_OFFSET_SHIFT 0
#define NIC_RX8_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX8_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 8 register 3 */
#define NIC_RX8_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX8_D3_LEN_SHIFT 16
#define NIC_RX8_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX8_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Interrupt disable register */
/* definitions for field: Receive Complete in reg: Interrupt disable register */
......@@ -781,11 +177,8 @@
/* definitions for field: Transmit Complete in reg: Interrupt disable register */
#define NIC_EIC_IDR_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt disable register */
#define NIC_EIC_IDR_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt disable register */
#define NIC_EIC_IDR_TXERR WBGEN2_GEN_MASK(3, 1)
#define NIC_EIC_IDR_TXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt enable register */
......@@ -795,11 +188,8 @@
/* definitions for field: Transmit Complete in reg: Interrupt enable register */
#define NIC_EIC_IER_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt enable register */
#define NIC_EIC_IER_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt enable register */
#define NIC_EIC_IER_TXERR WBGEN2_GEN_MASK(3, 1)
#define NIC_EIC_IER_TXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt mask register */
......@@ -809,11 +199,8 @@
/* definitions for field: Transmit Complete in reg: Interrupt mask register */
#define NIC_EIC_IMR_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt mask register */
#define NIC_EIC_IMR_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt mask register */
#define NIC_EIC_IMR_TXERR WBGEN2_GEN_MASK(3, 1)
#define NIC_EIC_IMR_TXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt status register */
......@@ -823,25 +210,26 @@
/* definitions for field: Transmit Complete in reg: Interrupt status register */
#define NIC_EIC_ISR_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt status register */
#define NIC_EIC_ISR_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt status register */
#define NIC_EIC_ISR_TXERR WBGEN2_GEN_MASK(3, 1)
/* definitions for RAM: TX/RX Buffers */
#define NIC_MEM_BASE 0x00008000 /* base address */
#define NIC_MEM_BYTES 0x00008000 /* size in bytes */
#define NIC_MEM_WORDS 0x00002000 /* size in 32-bit words, 32-bit aligned */
#define NIC_EIC_ISR_TXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for RAM: TX descriptors mem */
#define NIC_DTX_BASE 0x00000080 /* base address */
#define NIC_DTX_BYTES 0x00000080 /* size in bytes */
#define NIC_DTX_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: RX descriptors mem */
#define NIC_DRX_BASE 0x00000100 /* base address */
#define NIC_DRX_BYTES 0x00000080 /* size in bytes */
#define NIC_DRX_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
PACKED struct NIC_WB {
/* [0x0]: REG NIC Control Register */
uint32_t CR;
/* [0x4]: REG NIC Status Register */
uint32_t SR;
/* [0x8]: REG SW_Reset */
uint32_t RESET;
/* padding to: 4 words */
uint32_t __padding_0[1];
/* [0x8]: REG NIC Current Rx Bandwidth Register */
uint32_t RXBW;
/* [0xc]: REG NIC Max Rx Bandwidth Register */
uint32_t MAXRXBW;
/* [0x10]: REG TX Descriptor 1 register 1 */
uint32_t TX1_D1;
/* [0x14]: REG TX Descriptor 1 register 2 */
......@@ -849,139 +237,31 @@ PACKED struct NIC_WB {
/* [0x18]: REG TX Descriptor 1 register 3 */
uint32_t TX1_D3;
/* padding to: 8 words */
uint32_t __padding_1[1];
/* [0x20]: REG TX Descriptor 2 register 1 */
uint32_t TX2_D1;
/* [0x24]: REG TX Descriptor 2 register 2 */
uint32_t TX2_D2;
/* [0x28]: REG TX Descriptor 2 register 3 */
uint32_t TX2_D3;
/* padding to: 12 words */
uint32_t __padding_2[1];
/* [0x30]: REG TX Descriptor 3 register 1 */
uint32_t TX3_D1;
/* [0x34]: REG TX Descriptor 3 register 2 */
uint32_t TX3_D2;
/* [0x38]: REG TX Descriptor 3 register 3 */
uint32_t TX3_D3;
/* padding to: 16 words */
uint32_t __padding_3[1];
/* [0x40]: REG TX Descriptor 4 register 1 */
uint32_t TX4_D1;
/* [0x44]: REG TX Descriptor 4 register 2 */
uint32_t TX4_D2;
/* [0x48]: REG TX Descriptor 4 register 3 */
uint32_t TX4_D3;
/* padding to: 20 words */
uint32_t __padding_4[1];
/* [0x50]: REG TX Descriptor 5 register 1 */
uint32_t TX5_D1;
/* [0x54]: REG TX Descriptor 5 register 2 */
uint32_t TX5_D2;
/* [0x58]: REG TX Descriptor 5 register 3 */
uint32_t TX5_D3;
/* padding to: 24 words */
uint32_t __padding_5[1];
/* [0x60]: REG TX Descriptor 6 register 1 */
uint32_t TX6_D1;
/* [0x64]: REG TX Descriptor 6 register 2 */
uint32_t TX6_D2;
/* [0x68]: REG TX Descriptor 6 register 3 */
uint32_t TX6_D3;
/* padding to: 28 words */
uint32_t __padding_6[1];
/* [0x70]: REG TX Descriptor 7 register 1 */
uint32_t TX7_D1;
/* [0x74]: REG TX Descriptor 7 register 2 */
uint32_t TX7_D2;
/* [0x78]: REG TX Descriptor 7 register 3 */
uint32_t TX7_D3;
/* padding to: 32 words */
uint32_t __padding_7[1];
/* [0x80]: REG TX Descriptor 8 register 1 */
uint32_t TX8_D1;
/* [0x84]: REG TX Descriptor 8 register 2 */
uint32_t TX8_D2;
/* [0x88]: REG TX Descriptor 8 register 3 */
uint32_t TX8_D3;
/* padding to: 36 words */
uint32_t __padding_8[1];
/* [0x90]: REG RX Descriptor 1 register 1 */
uint32_t __padding_0[1];
/* [0x20]: REG RX Descriptor 1 register 1 */
uint32_t RX1_D1;
/* [0x94]: REG RX Descriptor 1 register 2 */
/* [0x24]: REG RX Descriptor 1 register 2 */
uint32_t RX1_D2;
/* [0x98]: REG RX Descriptor 1 register 3 */
/* [0x28]: REG RX Descriptor 1 register 3 */
uint32_t RX1_D3;
/* padding to: 40 words */
uint32_t __padding_9[1];
/* [0xa0]: REG RX Descriptor 2 register 1 */
uint32_t RX2_D1;
/* [0xa4]: REG RX Descriptor 2 register 2 */
uint32_t RX2_D2;
/* [0xa8]: REG RX Descriptor 2 register 3 */
uint32_t RX2_D3;
/* padding to: 44 words */
uint32_t __padding_10[1];
/* [0xb0]: REG RX Descriptor 3 register 1 */
uint32_t RX3_D1;
/* [0xb4]: REG RX Descriptor 3 register 2 */
uint32_t RX3_D2;
/* [0xb8]: REG RX Descriptor 3 register 3 */
uint32_t RX3_D3;
/* padding to: 48 words */
uint32_t __padding_11[1];
/* [0xc0]: REG RX Descriptor 4 register 1 */
uint32_t RX4_D1;
/* [0xc4]: REG RX Descriptor 4 register 2 */
uint32_t RX4_D2;
/* [0xc8]: REG RX Descriptor 4 register 3 */
uint32_t RX4_D3;
/* padding to: 52 words */
uint32_t __padding_12[1];
/* [0xd0]: REG RX Descriptor 5 register 1 */
uint32_t RX5_D1;
/* [0xd4]: REG RX Descriptor 5 register 2 */
uint32_t RX5_D2;
/* [0xd8]: REG RX Descriptor 5 register 3 */
uint32_t RX5_D3;
/* padding to: 56 words */
uint32_t __padding_13[1];
/* [0xe0]: REG RX Descriptor 6 register 1 */
uint32_t RX6_D1;
/* [0xe4]: REG RX Descriptor 6 register 2 */
uint32_t RX6_D2;
/* [0xe8]: REG RX Descriptor 6 register 3 */
uint32_t RX6_D3;
/* padding to: 60 words */
uint32_t __padding_14[1];
/* [0xf0]: REG RX Descriptor 7 register 1 */
uint32_t RX7_D1;
/* [0xf4]: REG RX Descriptor 7 register 2 */
uint32_t RX7_D2;
/* [0xf8]: REG RX Descriptor 7 register 3 */
uint32_t RX7_D3;
/* padding to: 64 words */
uint32_t __padding_15[1];
/* [0x100]: REG RX Descriptor 8 register 1 */
uint32_t RX8_D1;
/* [0x104]: REG RX Descriptor 8 register 2 */
uint32_t RX8_D2;
/* [0x108]: REG RX Descriptor 8 register 3 */
uint32_t RX8_D3;
/* padding to: 72 words */
uint32_t __padding_16[5];
/* [0x120]: REG Interrupt disable register */
/* padding to: 16 words */
uint32_t __padding_1[5];
/* [0x40]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x124]: REG Interrupt enable register */
/* [0x44]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x128]: REG Interrupt mask register */
/* [0x48]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x12c]: REG Interrupt status register */
/* [0x4c]: REG Interrupt status register */
uint32_t EIC_ISR;
/* padding to: 8192 words */
uint32_t __padding_17[8116];
/* [0x8000 - 0xffff]: RAM TX/RX Buffers, 8192 32-bit words, 32-bit aligned, word-addressable */
uint32_t MEM [8192];
/* padding to: 32 words */
uint32_t __padding_2[12];
/* [0x80 - 0xff]: RAM TX descriptors mem, 32 32-bit words, 32-bit aligned, word-addressable */
uint32_t DTX [32];
/* padding to: 64 words */
uint32_t __padding_3[32];
/* [0x100 - 0x17f]: RAM RX descriptors mem, 32 32-bit words, 32-bit aligned, word-addressable */
uint32_t DRX [32];
};
#endif
kernel/wbgen-regs/nic-regs.wb
View file @ 14715d17
......@@ -36,9 +36,6 @@ top = peripheral {
* With EMPTY set to 0, the frame can now be copied from the NIC's memory and stats can be updated \
* Set READY bit to 1 \
\
Todo \
~~~~ \
* Descriptors in RAM, not as registers. wbgen2 doesn't support this yet. Working on it. \
Known issues \
~~~~~~~~~~~ \
* Only 32-bit aligned addresses are supported";
......@@ -47,377 +44,446 @@ top = peripheral {
prefix = "nic";
reg {
name = "NIC Control Register";
prefix = "CR";
field {
name = "Receive enable";
description = "Enables the NIC to receive data";
prefix = "rx_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Transmit enable";
description = "Enables the NIC to transmit data. When reset, the internal transmit pointer points to the first entry in the TX descriptor pool";
prefix = "tx_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
name = "NIC Control Register";
prefix = "CR";
field {
name = "Receive enable";
description = "Enables the NIC to receive data";
prefix = "rx_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Transmit enable";
description = "Enables the NIC to transmit data. When reset, the internal transmit pointer points to the first entry in the TX descriptor pool";
prefix = "tx_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rx bandwidth throttling enable";
description = "Enables bandwidth throttling for received traffic. \
This is to prevent blocking ARM CPU with interrupts coming from NIC";
prefix = "rxthr_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Software Reset";
description = "write 1: reset the NIC, zero all registers and reset the state of the module \
write 0: no effect";
prefix = "sw_rst";
size = 1;
align = 31;
type = MONOSTABLE;
};
};
reg {
name = "NIC Status Register";
prefix = "SR";
field {
name = "Buffer Not Available";
prefix = "bna";
description = "No buffers were available when receiving a packet.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
load = LOAD_EXT;
};
field {
name = "Frame Received";
prefix = "rec";
description = "One or more frames have been received.\
Cleared by writing a one to this bit";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
name = "NIC Status Register";
prefix = "SR";
field {
name = "Buffer Not Available";
prefix = "bna";
description = "No buffers were available when receiving a packet.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
load = LOAD_EXT;
};
field {
name = "Frame Received";
prefix = "rec";
description = "One or more frames have been received.\
Cleared by writing a one to this bit";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Transmission done";
prefix = "tx_done";
description = "read 1: All non-empty TX descriptors have been transmitted\
read 0: Transmission in progress\
write 1: Clears the flag\
write 0: No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Transmission error";
prefix = "tx_error";
description = "read 1: A TX error occured and the transmission was stopped. CUR_TX_DESC is pointing the TX descriptor for which the error occured\
read 0: No TX error\
write 1: Clears the flag\
write 0: No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
align = 8;
name = "Current TX descriptor";
size = 3;
prefix = "cur_TX_Desc";
description = "Index of the currently handled TX descriptor";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
align = 8;
name = "Current RX descriptor";
size = 3;
prefix = "cur_RX_DESC";
description = "Index of the currently handled RX descriptor";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "SW_Reset";
description = "Writing to this register resets the NIC, zeroing all registers and resetting the state of the module";
prefix = "reset";
field {
name = "Software reset";
type = PASS_THROUGH;
size = 32;
};
name = "NIC Current Rx Bandwidth Register";
prefix = "RXBW";
field {
name = "Bytes-per-second";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
load = LOAD_EXT;
};
};
irq {
name = "Receive Complete";
prefix = "rcomp";
description = "A frame has been stored in memory.";
trigger = LEVEL_1;
reg {
name = "NIC Max Rx Bandwidth Register";
prefix = "MAXRXBW";
field {
name = "KBytes-per-second";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
irq {
name = "Transmit Complete";
prefix = "tcomp";
description = "Frame successfully transmitted";
trigger = LEVEL_1;
name = "Receive Complete";
prefix = "rcomp";
ack_line = true;
description = "A frame has been stored in memory.";
trigger = LEVEL_1;
};
irq {
name = "Receive Error";
prefix = "rxerr";
description = "Receive Error";
trigger = LEVEL_1;
name = "Transmit Complete";
prefix = "tcomp";
ack_line = true;
mask_line = true;
description = "Frame successfully transmitted";
trigger = LEVEL_1;
};
irq {
name = "Transmit Error";
prefix = "txerr";
trigger = LEVEL_1;
name = "Transmit Error";
prefix = "txerr";
ack_line = true;
mask_line = true;
trigger = LEVEL_1;
};
-- ram {
-- name = "TX descriptors mem";
-- prefix = "dtx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
-- ram {
-- name = "RX descriptors mem";
-- prefix = "drx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
ram {
name = "TX/RX Buffers";
prefix = "mem";
-- 8192 * 32 = 32Kb
size = 8192;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
ram {
name = "TX descriptors mem";
prefix = "dtx";
size = 32;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
ram {
name = "RX descriptors mem";
prefix = "drx";
size = 32;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
-- ram {
-- name = "TX/RX Buffers";
-- prefix = "mem";
-- -- 8192 * 32 = 32Kb
-- size = 8192;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
};
};
TX_desc_template =
{
TX_desc_template = {
reg {
name = "TX Descriptor %d register 1";
reg {
name = "TX Descriptor %d register 1";
description = "1st part of TX descriptor header. ";
prefix = "tx%d_d1";
align = 4;
field {
name = "Ready";
prefix = "ready";
description = "0 - The descriptor and buffer can be manipulated. \
1 - The device owns the descriptor and will set the bit to 0 after transmission";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Error";
prefix = "error";
description = "1 - an error occured during transmission of this descriptor.\
0 - transmission was successful";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Timestamp Enable";
description = "Set to 1 if the frame has to be timestamped by the endpoint. The NIC will then generate a TX OOB block on its WRF source, containing the value of TS_ID from the descriptor. ";
prefix = "ts_e";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Pad Enable";
prefix = "pad_e";
description = "When set, short frames (< 60 bytes) are padded with zeros to 60 bytes. This doesn't include the CRC field (so the final frame length will be 64 bytes)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
-- todo: Errors: add some more, e.g. Retry Count, Retry Limit exceeded...
field {
name = "Timestamp Frame Identifier";
prefix = "ts_id";
description = "Frame Identifier - a 16-bit value which must be unique in reasonably long time period. It's used to match the TX timestamps coming from different physical ports with the timestamped packets.";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
description = "1st part of TX descriptor header. ";
prefix = "tx%d_d1";
reg {
name = "TX Descriptor %d register 2";
prefix = "tx%d_d2";
field {
name = "offset in RAM--in bytes, must be aligned to 32-bit boundary";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2)";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
align = 4;
reg {
name = "TX Descriptor %d register 3";
prefix = "tx%d_d3";
field {
prefix = "DPM";
name = "Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet.";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
field {
name = "Ready";
prefix = "ready";
description = "0 - The descriptor and buffer can be manipulated. \
1 - The device owns the descriptor and will set the bit to 0 after transmission";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Error";
prefix = "error";
description = "1 - an error occured during transmission of this descriptor.\
0 - transmission was successful";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Timestamp Enable";
description = "Set to 1 if the frame has to be timestamped by the endpoint. The NIC will then generate a TX OOB block on its WRF source, containing the value of TS_ID from the descriptor. ";
prefix = "ts_e";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Pad Enable";
prefix = "pad_e";
description = "When set, short frames (< 60 bytes) are padded with zeros to 60 bytes. This doesn't include the CRC field (so the final frame length will be 64 bytes)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
-- todo: Errors: add some more, e.g. Retry Count, Retry Limit exceeded...
field {
name = "Timestamp Frame Identifier";
prefix = "ts_id";
description = "Frame Identifier - a 16-bit value which must be unique in reasonably long time period. It's used to match the TX timestamps coming from different physical ports with the timestamped packets.";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX Descriptor %d register 2";
prefix = "tx%d_d2";
field {
name = "offset in RAM--in bytes, must be aligned to 32-bit boundary";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2)";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX Descriptor %d register 3";
prefix = "tx%d_d3";
field {
prefix = "DPM";
name = "Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet.";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
RX_desc_template = {
reg {
align=4;
name = "RX Descriptor %d register 1";
description = "Descriptor of an RX frame buffer";
prefix = "rx%d_d1";
field {
name = "Empty";
prefix = "empty";
description = "0 - Reception (or failure) has occurred on this buffer. The NIC cannot operate on the until this bit is set to 1. \
1 - The buffer is ready to be filled in with data by the NIC";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Error";
prefix = "error";
description = "Set when the the received frame contains an error (an error was indicated by the remote WRF source)";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block.";
prefix = "port";
type = SLV;
size = 6;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Got RX Timestamp";
prefix = "GOT_TS";
description = "1 - there is a valid RX timestamp present in the TS field,\
0 - no RX timestamp";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
reg {
align=4;
name = "RX Descriptor %d register 1";
description = "Descriptor of an RX frame buffer";
prefix = "rx%d_d1";
field {
name = "Empty";
prefix = "empty";
description = "0 - Reception (or failure) has occurred on this buffer. The NIC cannot operate on the until this bit is set to 1. \
1 - The buffer is ready to be filled in with data by the NIC";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
field {
name = "RX Timestamp (possibly) incorrect";
prefix = "TS_INCORRECT";
align = 15;
description = "1 - there is a risk that the timestamp in RX_D2 is invalid, because it was taken during counter adjustment,\
0 - RX timestamp OK.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
field {
name = "Error";
prefix = "error";
description = "Set when the the received frame contains an error (an error was indicated by the remote WRF source)";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block.";
prefix = "port";
type = SLV;
size = 6;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
reg {
name = "RX Descriptor %d register 2";
prefix = "rx%d_d2";
field {
name = "RX_TS_R";
prefix = "TS_R";
description = "Value of the RX timestamp (rising edge bits)";
size = 28;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX_TS_F";
prefix = "TS_F";
description = "Value of the RX timestamp (falling edge bits)";
size = 4;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
field {
name = "Got RX Timestamp";
prefix = "GOT_TS";
description = "1 - there is a valid RX timestamp present in the TS field,\
0 - no RX timestamp";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
reg {
name = "RX Descriptor %d register 3";
prefix = "rx%d_d3";
field {
name = "Offset in packet RAM (in bytes, 32-bit aligned)";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet.";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
field {
name = "RX Timestamp (possibly) incorrect";
prefix = "TS_INCORRECT";
align = 15;
description = "1 - there is a risk that the timestamp in RX_D2 is invalid, because it was taken during counter adjustment,\
0 - RX timestamp OK.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "RX Descriptor %d register 2";
prefix = "rx%d_d2";
field {
name = "RX_TS_R";
prefix = "TS_R";
description = "Value of the RX timestamp (rising edge bits)";
size = 28;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX_TS_F";
prefix = "TS_F";
description = "Value of the RX timestamp (falling edge bits)";
size = 4;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "RX Descriptor %d register 3";
prefix = "rx%d_d3";
field {
name = "Offset in packet RAM (in bytes, 32-bit aligned)";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet.";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
function generate_descriptors(n)
local i;
local i;
for i=1,n do
local T=deepcopy(TX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
print(r.name)
end, T);
for i=1,n do
local T=deepcopy(TX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
print(r.name)
end, T);
table_join(periph, T);
end
table_join(periph, T);
end
for i=1,n do
local T=deepcopy(RX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
end, T);
for i=1,n do
local T=deepcopy(RX_desc_template);
table_join(periph, T);
end
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
end, T);
table_join(periph, T);
end
end
generate_descriptors(8);
generate_descriptors(1);
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