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W
White Rabbit Network Interface Card
Commit 14715d17 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk Committed by Miguel Jimenez Lopez
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include/wbgen-regs: update nic-regs to match HDL

parent 45338156
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kernel/wbgen-regs/nic-regs.h
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kernel/wbgen-regs/nic-regs.wb
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......@@ -36,9 +36,6 @@ top = peripheral {
* With EMPTY set to 0, the frame can now be copied from the NIC's memory and stats can be updated \
* Set READY bit to 1 \
\
Todo \
~~~~ \
* Descriptors in RAM, not as registers. wbgen2 doesn't support this yet. Working on it. \
Known issues \
~~~~~~~~~~~ \
* Only 32-bit aligned addresses are supported";
......@@ -66,6 +63,25 @@ top = peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Rx bandwidth throttling enable";
description = "Enables bandwidth throttling for received traffic. \
This is to prevent blocking ARM CPU with interrupts coming from NIC";
prefix = "rxthr_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Software Reset";
description = "write 1: reset the NIC, zero all registers and reset the state of the module \
write 0: no effect";
prefix = "sw_rst";
size = 1;
align = 31;
type = MONOSTABLE;
};
};
reg {
......@@ -92,23 +108,88 @@ top = peripheral {
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Transmission done";
prefix = "tx_done";
description = "read 1: All non-empty TX descriptors have been transmitted\
read 0: Transmission in progress\
write 1: Clears the flag\
write 0: No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Transmission error";
prefix = "tx_error";
description = "read 1: A TX error occured and the transmission was stopped. CUR_TX_DESC is pointing the TX descriptor for which the error occured\
read 0: No TX error\
write 1: Clears the flag\
write 0: No effect";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
align = 8;
name = "Current TX descriptor";
size = 3;
prefix = "cur_TX_Desc";
description = "Index of the currently handled TX descriptor";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
align = 8;
name = "Current RX descriptor";
size = 3;
prefix = "cur_RX_DESC";
description = "Index of the currently handled RX descriptor";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "SW_Reset";
description = "Writing to this register resets the NIC, zeroing all registers and resetting the state of the module";
prefix = "reset";
name = "NIC Current Rx Bandwidth Register";
prefix = "RXBW";
field {
name = "Software reset";
type = PASS_THROUGH;
name = "Bytes-per-second";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
load = LOAD_EXT;
};
};
reg {
name = "NIC Max Rx Bandwidth Register";
prefix = "MAXRXBW";
field {
name = "KBytes-per-second";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
irq {
name = "Receive Complete";
prefix = "rcomp";
ack_line = true;
description = "A frame has been stored in memory.";
trigger = LEVEL_1;
};
......@@ -116,58 +197,54 @@ top = peripheral {
irq {
name = "Transmit Complete";
prefix = "tcomp";
ack_line = true;
mask_line = true;
description = "Frame successfully transmitted";
trigger = LEVEL_1;
};
irq {
name = "Receive Error";
prefix = "rxerr";
description = "Receive Error";
trigger = LEVEL_1;
};
irq {
name = "Transmit Error";
prefix = "txerr";
ack_line = true;
mask_line = true;
trigger = LEVEL_1;
};
-- ram {
-- name = "TX descriptors mem";
-- prefix = "dtx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
-- ram {
-- name = "RX descriptors mem";
-- prefix = "drx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
ram {
name = "TX/RX Buffers";
prefix = "mem";
-- 8192 * 32 = 32Kb
size = 8192;
name = "TX descriptors mem";
prefix = "dtx";
size = 32;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
ram {
name = "RX descriptors mem";
prefix = "drx";
size = 32;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
TX_desc_template =
{
-- ram {
-- name = "TX/RX Buffers";
-- prefix = "mem";
-- -- 8192 * 32 = 32Kb
-- size = 8192;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
};
TX_desc_template = {
reg {
name = "TX Descriptor %d register 1";
......@@ -185,7 +262,6 @@ TX_desc_template =
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
......@@ -196,7 +272,6 @@ TX_desc_template =
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
......@@ -328,11 +403,8 @@ RX_desc_template = {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "RX Descriptor %d register 2";
prefix = "rx%d_d2";
......@@ -358,10 +430,10 @@ RX_desc_template = {
};
};
reg {
name = "RX Descriptor %d register 3";
prefix = "rx%d_d3";
field {
name = "Offset in packet RAM (in bytes, 32-bit aligned)";
prefix = "offset";
......@@ -382,8 +454,8 @@ RX_desc_template = {
load = LOAD_EXT;
};
};
};
};
function generate_descriptors(n)
......@@ -392,21 +464,18 @@ function generate_descriptors(n)
for i=1,n do
local T=deepcopy(TX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
print(r.name)
end, T);
table_join(periph, T);
end
for i=1,n do
local T=deepcopy(RX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
......@@ -415,9 +484,6 @@ function generate_descriptors(n)
table_join(periph, T);
end
end
generate_descriptors(8);
generate_descriptors(1);
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