Commit 15206f77 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk Committed by Miguel Jimenez Lopez

add HWIU support to libswitchhw

parent dfa4f1ca
/*
Register definitions for slave core: WR Switch Hardware Info Unit
* File : hwiu-regs.h
* Author : auto-generated by wbgen2 from wrsw_hwiu.wb
* Created : Wed Jun 5 10:49:31 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_hwiu.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_HWIU_WB
#define __WBGEN2_REGDEFS_WRSW_HWIU_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Address of the register in reg: Control Register */
#define HWIU_CR_ADR_MASK WBGEN2_GEN_MASK(0, 16)
#define HWIU_CR_ADR_SHIFT 0
#define HWIU_CR_ADR_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define HWIU_CR_ADR_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Read error in reg: Control Register */
#define HWIU_CR_RD_ERR WBGEN2_GEN_MASK(30, 1)
/* definitions for field: Read register value in reg: Control Register */
#define HWIU_CR_RD_EN WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Value of the requested register */
PACKED struct HWIU_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
/* [0x4]: REG Value of the requested register */
uint32_t REG_VAL;
};
#endif
-- -*- Mode: LUA; tab-width: 2 -*-
-- White-Rabbit Hardware Debugging Unit
-- author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
--
-- Use wbgen2 to generate code, documentation and more.
-- wbgen2 is available at:
-- http://www.ohwr.org/projects/wishbone-gen
--
peripheral {
name = "WR Switch Hardware Info Unit";
description = "The module provides basic info about the gateware version. It can be also used for reading registers inside WR Switch Gateware after connecting them to optional dbg input.";
hdl_entity = "hwiu_wishbone_slave";
prefix = "hwiu";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Address of the register";
description = "Which register (among those connected to HWDU) will be read";
prefix = "ADR";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Read error";
description = "read 1: read error, provided address is out of range \
read 0: read done successfully";
prefix = "RD_ERR";
type = BIT;
align = 30;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Read register value";
description = "write 1: read the content \
write 0: no effect \
read 1: reading in progress \
read 0: reading done, register value available";
prefix = "RD_EN";
type = BIT;
align = 31;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Value of the requested register";
description = "The value of the register under ADR from the Control Register";
prefix = "REG_VAL";
field {
name = "register value";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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