Skip to content

W
White Rabbit Network Interface Card
Commit 6abde584 authored by Benoit Rat's avatar Benoit Rat
Browse files
Options

top: adding spec generic reset

parent dd91c8e5
Hide whitespace changes
Inline Side-by-side
Showing with 78 additions and 7 deletions
top/spec/Manifest.py
View file @ 6abde584
files = ["wr_nic_sdb_top.vhd", "wr_nic_sdb_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd" ]
files = ["wr_nic_sdb_top.vhd", "wr_nic_sdb_top.ucf", "spec_reset_gen.vhd", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd" ]
modules = { "local" : [ "../../" ] }
top/spec/spec_reset_gen.vhd 0 → 100644
View file @ 6abde584
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity spec_reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end spec_reset_gen;
architecture behavioral of spec_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
top/spec/wr_nic_sdb_top.vhd
View file @ 6abde584
......@@ -28,8 +28,9 @@
-- 2012-02-08 1.0 greg.d Created
-- 2012-02-20 1.1 greg.d added GN4124 to wrsw_nic DMA connection
-- 2012-03-10 1.2 rafa.r added dio_core
-- 2012-06-25 1.3 jdiaz New dio_functionality
-- 2012-07-06 1.4 jdiaz Updating of files and integration test
-- 2012-06-25 1.3 jdiaz New dio_functionality
-- 2012-07-06 1.4 jdiaz Updating of files and integration test
-- 2012-07-06 1.5 ben.r Adding PPS to dio & reset
-------------------------------------------------------------------------------
-- TODO:
-- testing
......@@ -311,6 +312,14 @@ architecture rtl of wr_nic_sdb_top is
);
end component; -- gn4124_core
-- Generic Reset (PCIe & Standalone)
component spec_reset_gen
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
-- NIC
component xwrsw_nic
......@@ -445,6 +454,7 @@ architecture rtl of wr_nic_sdb_top is
signal p2l_pll_locked : std_logic;
-- Reset
signal rst_a : std_logic;
signal rst : std_logic;
-- DMA wishbone bus -- NOT IN USE
......@@ -637,8 +647,12 @@ begin
CLKFBIN => pllout_clk_fb_dmtd,
CLKIN => clk_20m_vcxo_buf); -- 20 MHz
local_reset_n <= L_RST_N;
U_Reset_Gen : spec_reset_gen
port map (
clk_sys_i => clk_sys,
rst_pcie_n_a_i => L_RST_N,
rst_button_n_a_i => button1_i,
rst_n_o => local_reset_n);
cmp_clk_sys_buf : BUFG
port map (
......@@ -718,12 +732,14 @@ begin
master_o => cbar_master_o
);
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
rst <= not(L_RST_N);
------------------------------------------------------------------------------
-- Gennun Core
------------------------------------------------------------------------------
U_Gennum_Core : gn4124_core
port map
(
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment