top: Added Etherbone support.

- Added Etherbone core as wishbone master in top crossbar. - Added a multiplexer to connect Etherbone and Nic core to wr-core. - Connected wr-core to Etherbone configuration space to access Etherbone registers. - wrc.ram: Updated with Etherbone support. (Old: wrc_without_etherbone.ram) - wrc.ram: Updated ep_pfilter for Etherbone packets. You can see this configuration in extra folder.

top: Added Etherbone support.
- Added Etherbone core as wishbone master in top crossbar. - Added a multiplexer to connect Etherbone and Nic core to wr-core. - Connected wr-core to Etherbone configuration space to access Etherbone registers. - wrc.ram: Updated with Etherbone support. (Old: wrc_without_etherbone.ram) - wrc.ram: Updated ep_pfilter for Etherbone packets. You can see this configuration in extra folder.
7738ceef · Miguel Jimenez Lopez · f61f09d7 · 7738ceef · 7738ceef · 7738ceef
Commit 7738ceef authored Oct 31, 2013 by Miguel Jimenez Lopez
5 changed files
--- a/extra/wrpc-sw/ep_pfilter.c
+++ b/extra/wrpc-sw/ep_pfilter.c
+/*
+ * This work is part of the White Rabbit project
+ *
+ * Copyright (C) 2011 CERN (www.cern.ch)
+ * Copyright (C) 2012 GSI (www.gsi.de)
+ * Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ * Author: Wesley W. Terpstra <w.terpstra@gsi.de>
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+
+/* Endpoint Packet Filter/Classifier driver
+
+   A little explanation: The WR core needs to classify the incoming packets into
+   two (or more categories):
+   - PTP, ARP, DHCP packets, which should go to the WRCore CPU packet queue (mini-nic)
+   - Other packets matching user's provided pattern, which shall go to the external fabric
+     port - for example to Etherbone, host network controller, etc.
+   - packets to be dropped (used neither by the WR Core or the user application)
+
+  WR Endpoint (WR MAC) inside the WR Core therefore contains a simple microprogrammable
+  packet filter/classifier. The classifier processes the incoming packet, and assigns it
+  to one of 8 classes (an 8-bit word, where each bit corresponds to a particular class) or
+  eventually drops it. Hardware implementation of the unit is a simple VLIW processor with
+  32 single-bit registers (0 - 31). The registers are organized as follows:
+  - 0: don't touch (always 0)
+  - 1 - 22: general purpose registers
+  - 23: drop packet flag: if 1 at the end of the packet processing, the packet will be dropped.
+  - 24..31: packet class (class 0 = reg 24, class 7 = reg 31).
+
+  Program memory has 64 36-bit words. Packet filtering program is restarted every time a new packet comes.
+  There are 5 possible instructions:
+
+  1. CMP offset, value, mask, oper, Rd:
+  ------------------------------------------
+
+  * Rd = Rd oper ((((uint16_t *)packet) [offset] & mask) == value)
+
+  Examples:
+  * CMP 3, 0xcafe, 0xffff, MOV, Rd
+  will compare the 3rd word of the packet (bytes 6, 7) against 0xcafe and if the words are equal,
+  1 will be written to Rd register.
+
+  * CMP 4, 0xbabe, 0xffff, AND, Rd
+  will do the same with the 4th word and write to Rd its previous value ANDed with the result
+  of the comparison. Effectively, Rd now will be 1 only if bytes [6..9] of the payload contain word
+  0xcafebabe.
+
+  Note that the mask value is nibble-granular. That means you can choose a particular
+  set of nibbles within a word to be compared, but not an arbitrary set of bits (e.g. 0xf00f, 0xff00
+  and 0xf0f0 masks are ok, but 0x8001 is wrong.
+
+  2. BTST offset, bit_number, oper, Rd
+  ------------------------------------------
+
+  * Rd = Rd oper (((uint16_t *)packet) [offset] & (1<<bit_number) ? 1 : 0)
+
+  Examples:
+  * BTST 3, 10, MOV, 11
+  will write 1 to reg 11 if the 10th bit in the 3rd word of the packet is set (and 0 if it's clear)
+
+  3. Logic opearations:
+  -----------------------------------------
+  * LOGIC2 Rd, Ra, OPER Rb - 2 argument logic (Rd = Ra OPER Rb). If the operation is MOV or NOT, Ra is
+  taken as the source register.
+
+  * LOGIC3 Rd, Ra, OPER Rb, OPER2, Rc - 3 argument logic Rd = (Ra OPER Rb) OPER2 Rc.
+
+  4. Misc
+  -----------------------------------------
+  FIN instruction terminates the program.
+  NOP executes a dummy instruction (LOGIC2 0, 0, AND, 0)
+
+  IMPORTANT:
+  - the program counter is advanved each time a 16-bit words of the packet arrives.
+  - the CPU doesn't have any interlocks to simplify the HW, so you can't compare the
+    10th word when  PC = 2. Max comparison offset is always equal to the address of the instruction.
+  - Code may contain up to 64 operations, but it must classify shorter packets faster than in
+    32 instructions (there's no flow throttling)
+*/
+
+#include <stdio.h>
+
+#include "board.h"
+#include <endpoint.h>
+#include <hw/endpoint_regs.h>
+
+#define PFILTER_MAX_CODE_SIZE      32
+
+#define pfilter_dbg(x, ...) /* nothing */
+
+extern volatile struct EP_WB *EP;
+
+static const uint64_t PF_MODE_LOGIC = (1ULL << 34);
+static const uint64_t PF_MODE_CMP = 0ULL;
+
+static int code_pos;
+static uint64_t code_buf[32];
+
+/* begins assembling a new packet filter program */
+static void pfilter_new()
+{
+	code_pos = 0;
+}
+
+static void check_size()
+{
+	if (code_pos == PFILTER_MAX_CODE_SIZE - 1) {
+		pfilter_dbg("microcode: code too big (max size: %d)\n",
+			    PFILTER_MAX_CODE_SIZE);
+	}
+}
+
+static void check_reg_range(int val, int minval, int maxval, char *name)
+{
+	if (val < minval || val > maxval) {
+		pfilter_dbg("microcode: %s register out of range (%d to %d)",
+			    name, minval, maxval);
+	}
+}
+
+static void pfilter_cmp(int offset, int value, int mask, pfilter_op_t op,
+			int rd)
+{
+	uint64_t ir;
+
+	check_size();
+
+	if (offset > code_pos)
+		pfilter_dbg
+		    ("microcode: comparison offset is bigger than current PC. Insert some nops before comparing");
+
+	check_reg_range(rd, 1, 15, "ra/rd");
+
+	ir = (PF_MODE_CMP | ((uint64_t) offset << 7)
+	      | ((mask & 0x1) ? (1ULL << 29) : 0)
+	      | ((mask & 0x10) ? (1ULL << 30) : 0)
+	      | ((mask & 0x100) ? (1ULL << 31) : 0)
+	      | ((mask & 0x1000) ? (1ULL << 32) : 0))
+	    | op | (rd << 3);
+
+	ir = ir | ((uint64_t) value & 0xffffULL) << 13;
+
+	code_buf[code_pos++] = ir;
+}
+
+static void pfilter_nop()
+{
+	uint64_t ir;
+	check_size();
+	ir = PF_MODE_LOGIC;
+	code_buf[code_pos++] = ir;
+}
+
+  // rd  = ra op rb
+static void pfilter_logic2(int rd, int ra, pfilter_op_t op, int rb)
+{
+	uint64_t ir;
+	check_size();
+	check_reg_range(ra, 0, 31, "ra");
+	check_reg_range(rb, 0, 31, "rb");
+	check_reg_range(rd, 1, 31, "rd");
+
+	ir = ((uint64_t) ra << 8) | ((uint64_t) rb << 13) |
+	    (((uint64_t) rd & 0xf) << 3) | (((uint64_t) rd & 0x10) ? (1ULL << 7)
+					    : 0) | (uint64_t) op;
+	ir = ir | PF_MODE_LOGIC | (3ULL << 23);
+	code_buf[code_pos++] = ir;
+}
+
+static void pfilter_logic3(int rd, int ra, pfilter_op_t op, int rb,
+			   pfilter_op_t op2, int rc)
+{
+	uint64_t ir;
+	check_size();
+	check_reg_range(ra, 0, 31, "ra");
+	check_reg_range(rb, 0, 31, "rb");
+	check_reg_range(rc, 0, 31, "rc");
+	check_reg_range(rd, 1, 31, "rd");
+
+	ir = (ra << 8) | (rb << 13) | (rc << 18) | ((rd & 0xf) << 3) |
+	    ((rd & 0x10) ? (1 << 7) : 0) | op;
+	ir = ir | PF_MODE_LOGIC | (op2 << 23);
+	code_buf[code_pos++] = ir;
+}
+
+/* Terminates the microcode, loads it to the endpoint and enables the pfilter */
+static void pfilter_load()
+{
+	int i;
+	code_buf[code_pos++] = (1ULL << 35);	// insert FIN instruction
+
+	EP->PFCR0 = 0;		// disable pfilter
+
+	for (i = 0; i < code_pos; i++) {
+		uint32_t cr0, cr1;
+		cr1 = EP_PFCR1_MM_DATA_LSB_W(code_buf[i] & 0xfff);
+		cr0 =
+		    EP_PFCR0_MM_ADDR_W(i) | EP_PFCR0_MM_DATA_MSB_W(code_buf[i]
+								   >> 12) |
+		    EP_PFCR0_MM_WRITE_MASK;
+
+		EP->PFCR1 = cr1;
+		EP->PFCR0 = cr0;
+	}
+
+	EP->PFCR0 = EP_PFCR0_ENABLE;
+}
+
+/* sample packet filter initialization:
+- redirects broadcasts and PTP packets to the WR Core
+- redirects unicasts addressed to self with ethertype 0xa0a0 to the external fabric */
+
+#define R_CLASS(x) (24 + x)
+#define R_DROP 23
+
+void pfilter_init_default()
+{
+	 pfilter_new();
+        pfilter_nop();
+        pfilter_cmp(0, 0xffff, 0xffff, MOV, 1);
+        pfilter_cmp(1, 0xffff, 0xffff, AND, 1);
+        pfilter_cmp(2, 0xffff, 0xffff, AND, 1); /* r1 = 1 when dst mac is broadcast */
+        pfilter_cmp(0, 0x011b, 0xffff, MOV, 2); 
+        pfilter_cmp(1, 0x1900, 0xffff, AND, 2);
+        pfilter_cmp(2, 0x0000, 0xffff, AND, 2); /* r2 = 1 when dst mac is PTP multicast (01:1b:19:00:00:00) */
+        pfilter_cmp(0, EP->MACH & 0xffff, 0xffff, MOV, 3); 
+        pfilter_cmp(1, EP->MACL >> 16, 0xffff, AND, 3);
+        pfilter_cmp(2, EP->MACL & 0xffff, 0xffff, AND, 3); /* r3 = 1 when the packet is unicast to our own MAC */
+        pfilter_cmp(6, 0x0800, 0xffff, MOV, 4); /* r4 = 1 when ethertype = IPv4 */ 
+        pfilter_cmp(6, 0x88f7, 0xffff, MOV, 5); /* r5 = 1 when ethertype = PTPv2 */
+        pfilter_cmp(6, 0x0806, 0xffff, MOV, 6); /* r6 = 1 when ethertype = ARP */
+
+        /* Ethernet = 14 bytes, Offset to type in IP: 8 bytes = 22/2 = 11 */
+        pfilter_cmp(11,0x0001, 0x00ff, MOV, 7); /* r7 = 1 when IP type = ICMP */
+        pfilter_cmp(11,0x0011, 0x00ff, MOV, 8); /* r8 = 1 when IP type = UDP */
+        pfilter_cmp(11,0x0006,0x00ff,MOV,9); /* r9 = 1 when IP type = TCP */
+        
+        pfilter_logic3(10,  3, OR,   0, AND, 4); /* r10 = IP(unicast) */
+        pfilter_logic3(11,  1, OR,   3, AND, 4); /* r11 = IP(unicast+broadcast) */
+        
+        pfilter_logic3(14,  1, AND,  6, OR,  5); /* r14 = ARP(broadcast) or PTPv2 */
+        pfilter_logic3(15, 10, AND,  7, OR, 14); /* r15 = ICMP/IP(unicast) or ARP(broadcast) or PTPv2 */
+        
+        /* Ethernet = 14 bytes, IPv4 = 20 bytes, offset to dport: 2 = 36/2 = 18 */
+        pfilter_cmp(18, 0x0044, 0xffff, MOV, 14); /* r14 = 1 when dport = BOOTPC */
+        pfilter_cmp(18,0xebd0,0xffff,MOV,6); /* r6 = 1 when dport = ETHERBONE */ 
+        pfilter_logic3(14, 14, AND, 8, AND, 11);  /* r14 = BOOTP/UDP/IP(unicast|broadcast) */
+        pfilter_logic2(15,14, OR, 15);   /* r15 = BOOTP/UDP/IP(unicast|broadcast) or ICMP/IP(unicast) or ARP(broadcast) or PTPv2 */
+
+        pfilter_cmp(21,0x4e6f,0xffff,MOV,9); /* r9 = 1 when magic number = ETHERBONE */
+        pfilter_logic2(6,6,AND,9);
+
+        // ASIGN CLASSES
+        
+        pfilter_logic2(R_CLASS(0), 15, MOV, 0); /* class 0: ICMP/IP(unicast) or ARP(broadcast) or PTPv2 => PTP LM32 core */
+
+        /* ETHERBONE ASIGN CLASS */
+        /* ----------------------------------------------------------------------------------- */
+
+        pfilter_logic2(R_CLASS(5), 6, OR, 0); /* class 5: Etherbone packet => Etherbone Core */
+
+        /* ----------------------------------------------------------------------------------- */
+
+        pfilter_logic2(R_CLASS(7),0,NOT,0);             /* class 7: enables by default to NIC */
+
+
+        pfilter_load();
+
+
+
+}
--- a/syn/specdio/wr_nic_dio.xise
+++ b/syn/specdio/wr_nic_dio.xise
--- a/syn/specdio/wrc.ram
+++ b/syn/specdio/wrc.ram
--- a/syn/specdio/wrc_without_etherbone.ram
+++ b/syn/specdio/wrc_without_etherbone.ram
--- a/top/specdio/wr_nic_dio_top.vhd
+++ b/top/specdio/wr_nic_dio_top.vhd
@@ -82,7 +82,7 @@ use work.gencores_pkg.all;
 use work.wrcore_pkg.all;
 use work.wr_fabric_pkg.all;
 use work.wr_xilinx_pkg.all;
--use work.etherbone_pkg.all;
+use work.etherbone_pkg.all;

 --library UNISIM;
 --use UNISIM.vcomponents.all;
@@ -351,6 +351,26 @@ architecture rtl of wr_nic_dio_top is
      );
  end component;

+  -- Etherbone core
+
+ -- component eb_ethernet_slave
+ --  generic(
+ --   g_sdb_address    : std_logic_vector(63 downto 0);
+ --   g_timeout_cycles : natural;
+ --   g_mtu            : natural);
+ --  port(
+ --   clk_i       : in  std_logic;
+ --   nRst_i      : in  std_logic;
+ --   snk_i       : in  t_wrf_sink_in;
+ --   snk_o       : out t_wrf_sink_out;
+ --   src_o       : out t_wrf_source_out;
+ --   src_i       : in  t_wrf_source_in;
+ --   cfg_slave_o : out t_wishbone_slave_out;
+ --   cfg_slave_i : in  t_wishbone_slave_in;
+ --   master_o    : out t_wishbone_master_out;
+ --   master_i    : in  t_wishbone_master_in);
+ -- end component;
+
  component xwrsw_tx_tsu
    generic (
      g_num_ports           : integer                        := 10;
@@ -542,16 +562,43 @@ architecture rtl of wr_nic_dio_top is
  signal tm_time_valid : std_logic;
  signal tm_seconds    : std_logic_vector(39 downto 0);
  signal tm_cycles     : std_logic_vector(27 downto 0);
+  
+  -------------------
+  -- Etherbone
+  -------------------
+  
+  signal etherbone_cfg_in  : t_wishbone_slave_in; 
+  signal etherbone_cfg_out : t_wishbone_slave_out;
+	
+  ------------------------
+  -- to wr-core's fabric
+  ------------------------
+	
+  signal ep_src_out : t_wrf_source_out;
+  signal ep_src_in  : t_wrf_source_in;
+  signal ep_snk_out : t_wrf_sink_out;
+  signal ep_snk_in  : t_wrf_sink_in;
+  
+  -----------------------------------
+  -- To multiplexer (Etherbone/NIC)
+  -----------------------------------
+   
+  signal mux_src_out : t_wrf_source_out_array(1 downto 0);
+  signal mux_src_in  : t_wrf_source_in_array(1 downto 0);
+  signal mux_snk_out : t_wrf_sink_out_array(1 downto 0);
+  signal mux_snk_in  : t_wrf_sink_in_array(1 downto 0);
+  signal mux_class   : t_wrf_mux_class(1 downto 0);
+

  -- DIO core
  --signal wb_irq_data_fifo_dio : std_logic; -- T.B.DELETED
  -------------------
  -- NIC
  -------------------
-  signal nic_src_out : t_wrf_source_out;
-  signal nic_src_in  : t_wrf_source_in;
-  signal nic_snk_out : t_wrf_sink_out;
-  signal nic_snk_in  : t_wrf_sink_in;
+--  signal nic_src_out : t_wrf_source_out;
+--  signal nic_src_in  : t_wrf_source_in;
+--  signal nic_snk_out : t_wrf_sink_out;
+--  signal nic_snk_in  : t_wrf_sink_in;
  signal nic_dma_in  : t_wishbone_slave_in;
  signal nic_dma_out : t_wishbone_slave_out;
  signal csr_ack     : std_logic;
@@ -573,8 +620,8 @@ architecture rtl of wr_nic_dio_top is

  constant c_topbar_sdb_address : t_wishbone_address := x"00063000";

-  signal cbar_slave_i  : t_wishbone_slave_in;
-  signal cbar_slave_o  : t_wishbone_slave_out;
+  signal cbar_slave_i  : t_wishbone_slave_in_array(1 downto 0);
+  signal cbar_slave_o  : t_wishbone_slave_out_array(1 downto 0);
  signal cbar_master_i : t_wishbone_master_in_array(4 downto 0);
  signal cbar_master_o : t_wishbone_master_out_array(4 downto 0);

@@ -719,7 +766,7 @@ begin
  ------------------------------------------------------------------------------
  WB_TOP_INTERCON : xwb_sdb_crossbar
    generic map(
-      g_num_masters => 1,
+      g_num_masters => 2,
      g_num_slaves  => 5,
      g_registered  => true,
      g_wraparound  => true,
@@ -730,8 +777,8 @@ begin
      clk_sys_i  => clk_sys,
      rst_n_i    => local_reset_n,
      -- Master connections
-      slave_i(0) => cbar_slave_i,
-      slave_o(0) => cbar_slave_o,
+      slave_i => cbar_slave_i,
+      slave_o => cbar_slave_o,
      -- Slave conenctions
      master_i   => cbar_master_i,
      master_o   => cbar_master_o
@@ -799,14 +846,14 @@ begin
      -- CSR wishbone interface (master pipelined)
      csr_clk_i   => clk_sys,
      csr_adr_o   => cbar_slave_adr_words,
-      csr_dat_o   => cbar_slave_i.dat,
-      csr_sel_o   => cbar_slave_i.sel,
-      csr_stb_o   => cbar_slave_i.stb,
-      csr_we_o    => cbar_slave_i.we,
-      csr_cyc_o   => cbar_slave_i.cyc,
-      csr_dat_i   => cbar_slave_o.dat,
+      csr_dat_o   => cbar_slave_i(0).dat,
+      csr_sel_o   => cbar_slave_i(0).sel,
+      csr_stb_o   => cbar_slave_i(0).stb,
+      csr_we_o    => cbar_slave_i(0).we,
+      csr_cyc_o   => cbar_slave_i(0).cyc,
+      csr_dat_i   => cbar_slave_o(0).dat,
      csr_ack_i   => csr_ack,
-      csr_stall_i => cbar_slave_o.stall,
+      csr_stall_i => cbar_slave_o(0).stall,

      ---------------------------------------------------------
      -- L2P DMA Interface (Pipelined Wishbone master)
@@ -823,11 +870,11 @@ begin
      --dma_stall_i => dma_stall
      );                

-  csr_ack <= (cbar_slave_o.ack or cbar_slave_o.err);
+  csr_ack <= (cbar_slave_o(0).ack or cbar_slave_o(0).err);

  -- From words to bytes. TODO: change to adapter block
-  cbar_slave_i.adr (18 downto 0)  <= cbar_slave_adr_words(16 downto 0) & "00";
-  cbar_slave_i.adr (31 downto 19) <= (others => '0');  -- SPEC memory space is 1 MB
+  cbar_slave_i(0).adr (18 downto 0)  <= cbar_slave_adr_words(16 downto 0) & "00";
+  cbar_slave_i(0).adr (31 downto 19) <= (others => '0');  -- SPEC memory space is 1 MB

  ---------------------------------------------
  --   Miscelaneous stuff (i2c, onewire, etc..)
@@ -867,7 +914,8 @@ begin
      g_dpram_initf               => "wrc.ram",  --Path to the lm32 file (wrc.ram) of the wrpc_sw repository
      g_dpram_size                => 90112/4,  -- 20480, it is the old value, it does not fit anymore 
      g_interface_mode            => PIPELINED,
-      g_address_granularity       => BYTE)
+      g_address_granularity       => BYTE,
+		g_aux_sdb                 	 => c_etherbone_sdb)
    port map (
      clk_sys_i  => clk_sys,
      clk_dmtd_i => clk_dmtd,
@@ -918,10 +966,15 @@ begin
      slave_i => cbar_master_o(0),  --cbar_slave_i, --
      slave_o => cbar_master_i(0),  --cbar_slave_o, --

-      wrf_src_o => nic_snk_in,
-      wrf_src_i => nic_snk_out,
-      wrf_snk_o => nic_src_in,
-      wrf_snk_i => nic_src_out,
+--      wrf_src_o => nic_snk_in,
+--      wrf_src_i => nic_snk_out,
+--      wrf_snk_o => nic_src_in,
+--      wrf_snk_i => nic_src_out,
+
+      wrf_src_o => ep_snk_in,
+      wrf_src_i => ep_snk_out,
+      wrf_snk_o => ep_src_in,
+      wrf_snk_i => ep_src_out,

      timestamps_o     => wrpc_ts_o,
      timestamps_ack_i => wrpc_ts_ack_i,
@@ -936,8 +989,32 @@ begin
      pps_p_o              => dio_out_pps,

      dio_o       => open,
-      rst_aux_n_o => open
+      rst_aux_n_o => open,
+
+
+      aux_master_o => etherbone_cfg_in,
+      aux_master_i => etherbone_cfg_out
      );
+		
+		
+  -------------------------------------
+  -- Etherbone core
+  -------------------------------------
+		
+  Etherbone : eb_ethernet_slave
+    generic map (
+      g_sdb_address => x"0000000000063000")
+    port map (
+      clk_i       => clk_sys,
+      nRst_i      => local_reset_n, 
+      src_o       => mux_src_out(0), 
+      src_i       => mux_src_in(0),
+      snk_o       => mux_snk_out(0),
+      snk_i       => mux_snk_in(0),
+      cfg_slave_o => etherbone_cfg_out,
+      cfg_slave_i => etherbone_cfg_in,
+      master_o    => cbar_slave_i(1),
+      master_i    => cbar_slave_o(1));

  -------------------------------------
  -- NIC
@@ -950,11 +1027,16 @@ begin
    port map(
      clk_sys_i => clk_sys,
      rst_n_i   => local_reset_n,
+		
+		snk_i => mux_snk_in(1),
+		snk_o => mux_snk_out(1),
+		src_i => mux_src_in(1),
+		src_o => mux_src_out(1),

-      snk_i => nic_snk_in,
-      snk_o => nic_snk_out,
-      src_i => nic_src_in,
-      src_o => nic_src_out,
+--      snk_i => nic_snk_in,
+--      snk_o => nic_snk_out,
+--      src_i => nic_src_in,
+--      src_o => nic_src_out,

      rtu_dst_port_mask_o => open,
      rtu_prio_o          => open,
@@ -1180,6 +1262,31 @@ begin
      I  => dio_clk_p_i,
      IB => dio_clk_n_i
      );
+		
+-----------------------------------------------------------------------------
+-- WBP MUX
+-----------------------------------------------------------------------------
+
+    U_WBP_Mux : xwrf_mux
+      generic map(
+        g_muxed_ports => 2)
+      port map (
+        clk_sys_i   => clk_sys,
+        rst_n_i     => local_reset_n,
+        ep_src_o    => ep_src_out,
+        ep_src_i    => ep_src_in,
+        ep_snk_o    => ep_snk_out,
+        ep_snk_i    => ep_snk_in,
+        mux_src_o   => mux_snk_in,
+        mux_src_i   => mux_snk_out,
+        mux_snk_o   => mux_src_in,
+        mux_snk_i   => mux_src_out,
+        mux_class_i => mux_class);
+ 		
+ 		
+mux_class(0)  <= x"20";
+mux_class(1)  <= x"80";
+


 -- .............................................