vic-eic interrupts tested, debugged with python scripts

7a337d4c · Javier Díaz · 00ce30b6 · 7a337d4c · 7a337d4c · 7a337d4c
Commit 7a337d4c authored Jul 12, 2012 by Javier Díaz
13 changed files
--- a/Manifest.py
+++ b/Manifest.py
@@ -8,3 +8,5 @@ modules =  {"local" :
    "git" : "git://ohwr.org/hdl-core-lib/wr-cores.git::wishbonized",
    "svn" : "http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl"
    }
--- a/doc/wr-nic.mkd
+++ b/doc/wr-nic.mkd
--- a/modules/wrsw_dio/Manifest.py
+++ b/modules/wrsw_dio/Manifest.py
 files = ["wrsw_dio_wb.vhd",
-	"wrsw_dio.vhd",
+	      "xwrsw_dio.vhd",
 	      "pulse_gen_pl.vhd",
         "immed_pulse_counter.vhd",	
 	      "dummy_time.vhd" ]

--- a/modules/wrsw_dio/wrsw_dio.vhd
+++ b/modules/wrsw_dio/wrsw_dio.vhd
@@ -25,7 +25,11 @@
 -- 2012-03-08  0.2      Javier.d        Added wrsw_dio_wb
 -- 2012-07-05  0.3		Javier.d        Midified wrsw_dio_wb, modified interface
 -------------------------------------------------------------------------------
+--     Memory map:
+--       0x000: DIO-ONEWIRE
+--       0x100: DIO-I2C
+--       0x200: DIO-GPIO
+--       0x300: DIO-REGISTERS
 -- WARNING: only pipelined mode is supported (Intercon is pipelined only) - T.W.
 library ieee;
@@ -83,13 +87,13 @@ architecture rtl of wrsw_dio is
  -------------------------------------------------------------------------------
  -- Component only for debugging (in order to generate seconds time) 
  -------------------------------------------------------------------------------
--  component dummy_time is
+  component dummy_time is
--    port(
+    port(
--      clk_sys       : in std_logic;
+      clk_sys       : in std_logic;
--      rst_n         : in std_logic; 
+      rst_n         : in std_logic; 
--      tm_utc        : out std_logic_vector(39 downto 0);
+      tm_utc        : out std_logic_vector(39 downto 0);
--      tm_cycles     : out std_logic_vector(27 downto 0));
+      tm_cycles     : out std_logic_vector(27 downto 0));
--  end component;	
+  end component;	
  -------------------------------------------------------------------------------
  -- PULSE GENERATOR which produces a 1-tick-long pulse in its
@@ -387,12 +391,16 @@ architecture rtl of wrsw_dio is
  signal cbar_master_in   : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0);
  signal cbar_master_out  : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
+  signal slave_bypass_i   : t_wishbone_slave_in;
+  signal slave_bypass_o   : t_wishbone_slave_out;
  -- DIO related signals
  signal dio_pulse           : std_logic_vector(4 downto 0);
  signal dio_pulse_prog      : std_logic_vector(4 downto 0);
  signal dio_pulse_immed     : std_logic_vector(4 downto 0);
  signal dio_pulse_immed_stb : std_logic_vector(4 downto 0);
  signal dio_out_mode        : std_logic_vector(4 downto 0);
+  signal wb_dio_irq          : std_logic;
 -------------------------------------------------------------------------------
 -- rtl
@@ -400,13 +408,13 @@ architecture rtl of wrsw_dio is
 begin  
  -- Dummy counter for simulationg WRPC seconds time
--  U_dummy: dummy_time
+  U_dummy: dummy_time
--    port map(
+    port map(
--      clk_sys     => clk_ref_i,
+      clk_sys     => clk_ref_i,
--      rst_n       => rst_n_i, 
+      rst_n       => rst_n_i, 
--      tm_utc      => tm_utc, 
+      tm_utc      => tm_seconds, 
--      tm_cycles   => tm_cycles
+      tm_cycles   => tm_cycles
--    );	
+    );	
  ------------------------------------------------------------------------------
  -- GEN AND STAMPER
@@ -420,12 +428,12 @@ begin
        pulse_o          => dio_pulse_prog(i),
        -- DEBUG
--        tm_time_valid_i  => '1',--tm_time_valid_i,
+        tm_time_valid_i  => '1',--tm_time_valid_i,
--        tm_utc_i         => tm_utc,--tm_utc_i, 
+        tm_utc_i         => tm_seconds,--tm_utc_i, 
--        tm_cycles_i      => tm_cycles, --tm_cycles_i, 
+        tm_cycles_i      => tm_cycles, --tm_cycles_i, 
-        tm_time_valid_i  => tm_time_valid_i,
+--        tm_time_valid_i  => tm_time_valid_i,
-        tm_utc_i         => tm_seconds_i, 
+--        tm_utc_i         => tm_seconds_i, 
-        tm_cycles_i      => tm_cycles_i, 
+--        tm_cycles_i      => tm_cycles_i, 
        trig_ready_o     => trig_ready(i),
@@ -444,12 +452,13 @@ begin
        pulse_a_i       => dio_in_i(i),
--        tm_time_valid_i => '1',--tm_time_valid_i,
+		  -- DEBUG
--        tm_utc_i        => tm_utc, --tm_utc_i, 
+        tm_time_valid_i => '1',--tm_time_valid_i,
--        tm_cycles_i     => tm_cycles, --tm_cycles_i, 
+        tm_utc_i        => tm_seconds, --tm_utc_i, 
-        tm_time_valid_i => tm_time_valid_i,
+        tm_cycles_i     => tm_cycles, --tm_cycles_i, 
-        tm_utc_i        => tm_seconds_i, 
+--        tm_time_valid_i => tm_time_valid_i,
-        tm_cycles_i     => tm_cycles_i, 
+--        tm_utc_i        => tm_seconds_i, 
+--        tm_cycles_i     => tm_cycles_i, 
        tag_utc_o       => tag_seconds(i), 
        tag_cycles_o    => tag_cycles(i), 
@@ -543,13 +552,28 @@ begin
      clk_sys_i     => clk_sys_i,
      rst_n_i       => rst_n_i,
      -- Master connections
-      slave_i(0)    => slave_i,
+      slave_i(0)    => slave_bypass_i,
-      slave_o(0)    => slave_o,
+      slave_o(0)    => slave_bypass_o,
      -- Slave conenctions
      master_i      => cbar_master_in,
      master_o      => cbar_master_out
      );
+  -- Irq form one slave is bypassed to the Master connection 
+  slave_bypass_i.cyc <= slave_i.cyc;
+  slave_bypass_i.stb <= slave_i.stb;
+  slave_bypass_i.adr <= slave_i.adr;
+  slave_bypass_i.sel <= slave_i.sel;
+  slave_bypass_i.dat <= slave_i.dat;	
+  slave_bypass_i.we <= slave_i.we;	
+  slave_o.ack        <= slave_bypass_o.ack;		
+  --slave_o.err        <= slave_bypass_o.err;
+  --slave_o.rty        <= slave_bypass_o.rty;
+  slave_o.stall      <= slave_bypass_o.stall;
+  slave_o.int        <= wb_dio_irq;
+  slave_o.dat        <= slave_bypass_o.dat;	 
  immediate_output_with_pulse_length: for i in 0 to 4 generate
    immediate_output_component: immed_pulse_counter
    generic map (
@@ -595,7 +619,8 @@ begin
      wb_we_i     => cbar_master_out(3).we,  
      wb_ack_o    => cbar_master_in(3).ack,
      wb_stall_o  => cbar_master_in(3).stall,
-      wb_int_o    => cbar_master_in(3).int,--wb_irq_data_fifo_o, --slave_o.int,
+		-- Crossbar could not propagate interrupt lines of several slaves  => signal bypass
+      wb_int_o    => wb_dio_irq, 
      clk_asyn_i  => clk_ref_i,
      dio_tsf0_wr_req_i       => dio_tsf_wr_req(0),

--- a/modules/wrsw_dio/xwrsw_dio.vhd
+++ b/modules/wrsw_dio/xwrsw_dio.vhd
--- a/software_test_dio_core/dio_fmc.py
+++ b/software_test_dio_core/dio_fmc.py
@@ -23,6 +23,17 @@ class VIC_irq:
    def get_reg(self, adr):        
        return self.bus.iread(0, self.base + adr, 4)
+class wrcore_time:
+    def __init__(self, bus, base):
+	self.bus = bus;
+	self.base = base;
+    def set_reg(self, adr, value):        
+        self.bus.iwrite(0, self.base + adr, 4, value)
+    def get_reg(self, adr):        
+        return self.bus.iread(0, self.base + adr, 4)
 class CDAC5578:
@@ -63,10 +74,10 @@ class CDAC5578:
 class CFmcDio:
-    BASE_REGS = 0x300
-    BASE_GPIO = 0x200
-    BASE_I2C = 0x100
    BASE_ONEWIRE = 0x0
+    BASE_I2C = 0x100
+    BASE_GPIO = 0x200
+    BASE_REGS = 0x300
    I2C_ADDR_DAC = 0x48
    I2C_ADDR_EEPROM = 0x50
@@ -132,13 +143,13 @@ class CFmcDio:
            return self.ds1820.read_temp(serial_number)
    def set_reg(self, adr, value):        
-        self.bus.iwrite(0, 0x60000 + self.BASE_REGS + adr, 4, value)
+        self.bus.iwrite(0, 0x62000 + self.BASE_REGS + adr, 4, value)
    def get_reg(self, adr):        
-        return self.bus.iread(0, 0x60000 + self.BASE_REGS + adr, 4)
+        return self.bus.iread(0, 0x62000 + self.BASE_REGS + adr, 4)
    def get_reg_long(self, adr):        
-        return self.bus.iread(0, 0x60000 + self.BASE_REGS + adr, 8)
+        return self.bus.iread(0, 0x62000 + self.BASE_REGS + adr, 8)
    def wait_irq_spec(self):
        return self.bus.irqwait()

--- a/software_test_dio_core/fpga_loader
+++ b/software_test_dio_core/fpga_loader
--- a/software_test_dio_core/load.sh
+++ b/software_test_dio_core/load.sh
 #!/bin/bash
-insmod ~/pts/gnurabbit/kernel/rawrabbit.ko vendor=0x10dc device=0x18d
+insmod ~/OHWR/wr-nic/software_test_dio_core/rawrabbit.ko vendor=0x10dc device=0x18d
--- a/software_test_dio_core/rawrabbit.ko
+++ b/software_test_dio_core/rawrabbit.ko
--- a/software_test_dio_core/test_pulse.py
+++ b/software_test_dio_core/test_pulse.py
--- a/software_test_dio_core/test_pulse_v01.py
+++ b/software_test_dio_core/test_pulse_v01.py
+#!/usr/bin/python
+#coding: utf8
+from ptsexcept import *
+from dio_fmc import *
+import rr
+import os
+import sys
+import gn4124
+import kbhit
+"""
+Tests DIO core (GEN AND STAMPER PULSE)
+"""
+def pause():
+   raw_input("press key\n")
+GN4124_CSR = 0x0
+def main(default_directory="."):
+   print "(-------------STARTING TEST-----------------)"
+   # Configure the FPGA using the program fpga_loader
+   path_fpga_loader = './fpga_loader'
+   path_firmware = '../syn/spec/wr_nic_top.bin'
+   firmware_loader = os.path.join(default_directory, path_fpga_loader)
+   bitstream = os.path.join(default_directory, path_firmware)
+   print "Loading firmware: %s" % (firmware_loader + ' ' + bitstream)
+   os.system( firmware_loader + ' ' + bitstream )
+   # Load board library and open the corresponding device
+   spec = rr.Gennum()
+   gennum = gn4124.CGN4124(spec, GN4124_CSR)
+   dio = CFmcDio(spec, 0x62000)
+   print "(3 devices expected)"
+   print
+   print ("FMC temperature: %3.3f°C" % dio.get_temp())
+   print "(expected room or computer temperature)"
+   print
+   # Lemo output configuration
+   print "(------------CONFIGURING DIO CHANNELS--------------)"
+   print "Value of LEMOs with all drivers enabled and terminations disabled"
+   for lemon in range(5):
+      dio.set_term(lemon, 0)
+      dio.set_dir(lemon, 1)  # enable output
+      dio.set_in_threshold(lemon,15)
+   print "Input threshold set to an intermediate level ({}).".format(dio.get_in_threshold(0))
+   print
+   print "(------------CONFIGURING INTERRUPTS--------------)"
+   # DIO Interrupts
+   print "(DIO Interrupts)"
+   dio.set_reg(0x64, 0x1f)   # Interrupts when the fifos have datas (UTC time from the pulse stamper)
+   #dio.set_reg(0x64, 0x3ff)  # fifos and pulse gen rdy interrupts
+   mask_irq = dio.get_reg(0x68)
+   print "MASK IRQ DIO =>", mask_irq
+   status_irq = dio.get_reg(0x6c) 
+   print "STATUS IRQ DIO =>", status_irq
+   # VIC Interrupts
+   print "(VIC Interrupts)"
+   VIC = VIC_irq(spec, 0x60000)
+   VIC.set_reg(0x0, 0x3)   # control register
+   control_irq_vic = VIC.get_reg(0x0)
+   print "CONTROL IRQ VIC =>", control_irq_vic
+   VIC.set_reg(0x8, 0x7)   # enable register
+   mask_irq_vic = VIC.get_reg(0x10)
+   print "MASK IRQ VIC =>", mask_irq_vic
+   status_irq_vic = VIC.get_reg(0x4) 
+   print "STATUS VIC IRQ =>", status_irq_vic
+   # Simulate interrupts
+   #VIC.set_reg(0x18, 0x7)   # generate soft irq
+   #status_irq_vic = VIC.get_reg(0x4) 
+   #print "STATUS VIC IRQ AFTER SOFTWARE INTERRUPTS =>", status_irq_vic
+   # Checking interrupts at pc level
+   #print "Waiting irq ..."   
+   #spec.irqena()   
+   #gennum.set_interrupt_config()
+   #a=gennum.wait_irq()
+   #b=spec.irqwait()   
+   #print "Is this working?", a,b
+   # Read WRCORE time --> HANG UP THE PC!!!!!!!
+   #WR_CORE_AD     =0x0
+   #PRI_CROSSBAR_AD=0x00020000 # Second bridge
+   #SEC_CROSSBAR_AD=0x00000300 # PPS
+   #time = wrcore_time(spec, (WR_CORE_AD + PRI_CROSSBAR_AD+SEC_CROSSBAR_AD))  
+   #print "eso", time
+   #seconds= time.get_reg(0x8) NNOOOOOOO!!!!!! 0x00020308
+   #cycles = time.get_reg(0x4)
+   #seconds=10
+   #cycles=0
+   #print "Time is: ", seconds, "and", cycles*8, "(cycles", cycles, ")"
+   ###################################################################################
+   # START LEMO OUTPUT DANCING ...
+   print
+   print "(------------START LEMO CONFIGURATION--------------)"
+   #print "Note: The dummy time core is already running after configuring the fpga, therefore you should run this program"
+   #print "before the configured trigger time below." 
+   # BASIC GPIO FUNCTIONALITY TEST
+   dio.set_reg(0x3C, 0x00)   # channels as GPIOs  
+   for lemon in range(5):
+     dio.set_dir(lemon, 1)  # enable output
+     dio.set_out(lemon,0)
+     val=dio.get_in (lemon)
+     print "Set value for channel", lemon, " to 0, read: ", val
+     dio.set_out(lemon,1)
+     val=dio.get_in (lemon)
+     print "Set value for channel", lemon, " to 1, read: ", val
+   # Please connect channel 0 and 1 with a lemo wire for this test
+   dio.set_dir(0, 0)  # enable channel 1 output and dissble channel 0
+   dio.set_dir(1,1)   
+   dio.set_out(1,0)
+   val=dio.get_in (0)
+   print "Channel 1 write 0, channel 0 read", val
+   dio.set_out(1,1)
+   val=dio.get_in (0)
+   print "Channel 1 write 1, channel 0 read", val
+   # Osciloscope test
+   #dio.set_out(4,1)
+   #pause() 
+   #dio.set_out(4,0)
+   #pause() 
+   #dio.set_out(4,1)
+   #pause() 
+   #dio.set_out(4,0)
+   #pause() 
+   # TIME-LENGTH PROGRAMMABLE PULSES TESTS
+   dio.set_reg(0x3C, 0x1f)   #Generate a programmable/immediate pulse of different length  
+   # Setting pulse length
+   dio.set_reg(0x48, 0x1)   
+   dio.set_reg(0x4C, 0x8)   
+   dio.set_reg(0x50, 0x10)   
+   dio.set_reg(0x54, 0x1)   
+   dio.set_reg(0x58, 0x40) 
+   # Time-stamps FIFOs registers address
+   adr_status_fifo = [0x7c, 0x8c, 0x9c, 0xac, 0xbc]
+   adr_time        = [0x70, 0x80, 0x90, 0xa0, 0xb0] # we just take the lowest 32 bits for the seconds
+   adr_cycles      = [0x78, 0x88, 0x98, 0xa8, 0xb8]
+   # Flushng fifos from previous game
+   print
+   for dio_pulse in range(5): # reading of pulses
+     print "------Flushing fifos ", dio_pulse, ":"
+     status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
+     cont = 0
+     while((status_fifo_reg & 0xff) != 0x0):
+       time   = dio.get_reg_long(adr_time[dio_pulse])
+       cycles = dio.get_reg(adr_cycles[dio_pulse])
+       print "Pulse ", cont
+       print "Seconds DIO dio_pulse =>", time
+       print "cycles DIO dio_pulse =>", cycles
+       status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
+       cont = cont + 1
+     print
+   ###################################################################################################
+   # Inmmediate output test
+   print
+   print "(-----------IMMEDIATE PULSE GENERATION (5 pulses for each DIO)---------------)"
+   #pause()
+   for num_pulses in range(5):
+     dio.set_reg(0x5C, 0x1f)   #Generate a pulse of different length
+   #status_irq = dio.get_reg(0x6c) 
+   ##print "STATUS IRQ DIO =>", status_irq
+   print "5 Immediate pulse of different length has been generated for each channel"
+   print
+   status_irq_vic = VIC.get_reg(0x4) 
+   print "STATUS VIC IRQ =>", status_irq_vic
+   status_irq = dio.get_reg(0x6c) 
+   print "STATUS IRQ DIO =>", status_irq # 31 means the 5 fifos has data
+   print
+   for dio_pulse in range(5): # reading of pulses
+     print "------Pulses from DIO ", dio_pulse, ":"
+     status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
+     cont = 0
+     while((status_fifo_reg & 0xff) != 0x0):
+       time   = dio.get_reg_long(adr_time[dio_pulse])
+       cycles = dio.get_reg(adr_cycles[dio_pulse])
+       print "Pulse ", cont
+       print "Seconds DIO dio_pulse =>", time
+       print "cycles DIO dio_pulse =>", cycles
+       status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
+       cont = cont + 1
+     print
+   print
+   status_irq_vic = VIC.get_reg(0x4) 
+   print "STATUS VIC IRQ =>", status_irq_vic
+   status_irq = dio.get_reg(0x6c) 
+   print "STATUS IRQ DIO =>", status_irq # we have read the fifo, no data to read => 0
+   ############################################################################
+   print
+   print "Starting time-programmable test" 
+   print
+   print "(------------TIME-TRIGGER BASED OUTPUTS--------------)"
+   # Programmable output test	
+   dio_rdy = dio.get_reg(0x44)
+   if dio_rdy != 0x1f:
+     print "Some pulse_gen module isn't ready to accept next trigger time tag, dio_rdy:", dio_rdy
+     exit()
+   #TIME TRIGGERS VALUES FOR EACH CHANNEL
+   dio.set_reg(0x0, 3)      #trig0 seconds_low
+   dio.set_reg(0x4, 0)      #trig0 seconds_high
+   dio.set_reg(0x8, 0)      #trig0 cycles
+   dio.set_reg(0xc, 5)     #trig1 seconds_low
+   dio.set_reg(0x10, 0)     #trig1 seconds_high
+   dio.set_reg(0x14, 67)    #trig1 cycles
+   dio.set_reg(0x18, 10)    #trig2 seconds_low
+   dio.set_reg(0x1c, 0)     #trig2 seconds_high
+   dio.set_reg(0x20, 430)   #trig2 cycles
+   dio.set_reg(0x24, 12)    #trig3 seconds_low
+   dio.set_reg(0x28, 0)     #trig3 seconds_high
+   dio.set_reg(0x2c, 94)    #trig3 cycles
+   dio.set_reg(0x30, 15)    #trig4 seconds_low
+   dio.set_reg(0x34, 0)     #trig4 seconds_high
+   dio.set_reg(0x38, 98)    #trig4 cycles
+   dio.set_reg(0x40, 0x1f)  # channell x trigger strobe
+   print
+   for dio_pulse in range(5):
+     print "Waiting pulse stamper from DIO ", dio_pulse," ...."
+     status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
+     while((status_fifo_reg & 0xff) != 0x1): #counter = 0x1
+       status_fifo_reg = dio.get_reg(adr_status_fifo[dio_pulse])
+     time   = dio.get_reg_long(adr_time[dio_pulse])
+     cycles = dio.get_reg(adr_cycles[dio_pulse])
+     print "DIO dio_pulse seconds =>", time
+     print "DIO dio_pulse cycles  =>", cycles
+     print
+   status_irq_vic = VIC.get_reg(0x4) 
+   print "STATUS VIC IRQ =>", status_irq_vic
+   print
+   status_irq = dio.get_reg(0x6c) 
+   print "STATUS IRQ DIO =>", status_irq
+   exit()
+if __name__ == "__main__":
+    main(".")
--- a/syn/spec/wr_nic.xise
+++ b/syn/spec/wr_nic.xise
--- a/top/spec/wr_nic_top.vhd
+++ b/top/spec/wr_nic_top.vhd
@@ -40,6 +40,11 @@
 --  0x00060000: VIC  
 --  0x00061000: TxTSU
 --  0x00062000: DIO
+--       0x000: DIO-ONEWIRE
+--       0x100: DIO-I2C
+--       0x200: DIO-GPIO
+--       0x300: DIO-REGISTERS
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
@@ -80,8 +85,8 @@ entity wr_nic_top is
      L_RST_N : in std_logic;           -- Reset from GN4124 (RSTOUT18_N)
      -- General Purpose Interface
-      GPIO       : inout std_logic_vector(1 downto 0);  -- GPIO[0] -> GN4124 GPIO8
+      GPIO       : inout std_logic_vector(1 downto 0);  -- GPIO[0] -> GN4124 GPIO8 -- T.B.V. datasheet write 9 
-                                                        -- GPIO[1] -> GN4124 GPIO9
+                                                        -- GPIO[1] -> GN4124 GPIO9 -- T.B.V. datasheet write 9 
      -- PCIe to Local [Inbound Data] - RX
      P2L_RDY    : out   std_logic;                      -- Rx Buffer Full Flag
      P2L_CLKn   : in    std_logic;                      -- Receiver Source Synchronous Clock-
@@ -475,7 +480,7 @@ architecture rtl of wr_nic_top is
  end component;
  -- DIO core
-  component wrsw_dio
+  component xwrsw_dio
    generic (
      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
      g_address_granularity : t_wishbone_address_granularity := WORD
@@ -866,9 +871,9 @@ begin
      p_rd_d_rdy_i => P_RD_D_RDY,
      tx_error_i   => TX_ERROR,
-		dma_irq_o       => open, -- T.B.D. Check it is ok
+		dma_irq_o       => open,
      irq_p_i      => vic_irq,
-      irq_p_o      => GPIO(0),
+      irq_p_o      => GPIO(1),  -- T.B.D. Check if GPIO is 1 or 0
      dma_reg_clk_i => clk_sys, -- Look, many signals just take default values if not used
@@ -1153,7 +1158,7 @@ begin
 -----------------------------------
 --   DIO core
 -----------------------------------
-  U_dio_core : wrsw_dio
+  U_dio_core : xwrsw_dio
    generic map (
      g_interface_mode      => PIPELINED,
      g_address_granularity => BYTE)