misc: renaming filename to specdio/wr_nic_dio_top.bin

We want to make clear that this architecture is to run a dio with wr-nic on a spec board. No changes in the code was made except renaming files.

misc: renaming filename to specdio/wr_nic_dio_top.bin
We want to make clear that this architecture is to run a dio with wr-nic on a spec board. No changes in the code was made except renaming files.
975fcb19 · Benoit Rat · 9ce01de1 · 975fcb19 · 975fcb19 · 975fcb19
Commit 975fcb19 authored Oct 09, 2013 by Benoit Rat
13 changed files
--- a/basic_python/diotest_specdriver.py
+++ b/basic_python/diotest_specdriver.py
@@ -21,7 +21,7 @@ def main(default_directory="."):

   # Configure the FPGA using the program fpga_loader
   path_fpga_loader = './fpga_loader'
-   path_firmware = '../syn/spec/wr_nic_top.bin'
+   path_firmware = '../syn/specdio/wr_nic_dio_top.bin'
   firmware_loader = os.path.join(default_directory, path_fpga_loader)
   bitstream = os.path.join(default_directory, path_firmware)
   print "Loading firmware: %s" % (firmware_loader + ' ' + bitstream)

--- a/basic_python/test_pulse.py
+++ b/basic_python/test_pulse.py
@@ -24,7 +24,7 @@ def main(default_directory="."):

   # Configure the FPGA using the program fpga_loader
   path_fpga_loader = './fpga_loader'
-   path_firmware = '../syn/spec/wr_nic_top.bin'
+   path_firmware = '../syn/specdio/wr_nic_dio_top.bin'
   firmware_loader = os.path.join(default_directory, path_fpga_loader)
   bitstream = os.path.join(default_directory, path_firmware)
   print "Loading firmware: %s" % (firmware_loader + ' ' + bitstream)

--- a/basic_python/test_pulse_v01.py
+++ b/basic_python/test_pulse_v01.py
@@ -24,7 +24,7 @@ def main(default_directory="."):

   # Configure the FPGA using the program fpga_loader
   path_fpga_loader = './fpga_loader'
-   path_firmware = '../syn/spec/wr_nic_top.bin'
+   path_firmware = '../syn/specdio/wr_nic_dio_top.bin'
   firmware_loader = os.path.join(default_directory, path_fpga_loader)
   bitstream = os.path.join(default_directory, path_firmware)
   print "Loading firmware: %s" % (firmware_loader + ' ' + bitstream)

--- a/syn/spec/Manifest.py
+++ b/syn/spec/Manifest.py
@@ -6,11 +6,11 @@ fetchto = "../../ip_cores"
 syn_device = "xc6slx45t"
 syn_grade = "-3"
 syn_package = "fgg484"
-syn_top = "wr_nic_sdb_top"
-syn_project = "wr_nic.xise"
+syn_top = "wr_nic_dio_top"
+syn_project = "wr_nic_dio.xise"

 modules = {"local" : 
-              [ "../../top/spec",
+              [ "../../top/specdio",
 		"../../platform/xilinx" 
              ] 
          }
--- a/syn/spec/wr_nic.xise
+++ b/syn/spec/wr_nic.xise
--- a/syn/spec/wrc.ram
+++ b/syn/spec/wrc.ram
--- a/testbench/top_level/Manifest.py
+++ b/testbench/top_level/Manifest.py
@@ -5,5 +5,5 @@ vlog_opt="+incdir+../../sim +incdir+gn4124_bfm +incdir+../../sim/wr-hdl +incdir+

 files = [ "main.sv" ]

-modules = { "local" :  [ "../..", "../../top/spec", "./gn4124_bfm"] }
+modules = { "local" :  [ "../..", "../../top/specdio", "./gn4124_bfm"] }

--- a/top/spec/Manifest.py
+++ b/top/spec/Manifest.py
-files = ["wr_nic_sdb_top.vhd", "wr_nic_sdb_top.ucf", "spec_reset_gen.vhd", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd" ]
+files = ["wr_nic_dio_top.vhd", "wr_nic_dio_top.ucf", "spec_reset_gen.vhd", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd" ]

 modules = { "local" : [ "../../" ] }
--- a/top/spec/spec_reset_gen.vhd
+++ b/top/spec/spec_reset_gen.vhd
--- a/top/spec/spec_serial_dac.vhd
+++ b/top/spec/spec_serial_dac.vhd
--- a/top/spec/spec_serial_dac_arb.vhd
+++ b/top/spec/spec_serial_dac_arb.vhd
--- a/top/spec/wr_nic_sdb_top.ucf
+++ b/top/spec/wr_nic_sdb_top.ucf
--- a/top/spec/wr_nic_sdb_top.vhd
+++ b/top/spec/wr_nic_sdb_top.vhd
@@ -93,7 +93,7 @@ use work.endpoint_pkg.all;
 use work.wrnic_sdb_pkg.all;


-entity wr_nic_sdb_top is
+entity wr_nic_dio_top is
  generic
    (
      g_nic_usedma : boolean := false;
@@ -218,9 +218,9 @@ entity wr_nic_sdb_top is
      uart_txd_o : out std_logic
      );

-end wr_nic_sdb_top;
+end wr_nic_dio_top;

-architecture rtl of wr_nic_sdb_top is
+architecture rtl of wr_nic_dio_top is

  ------------------------------------------------------------------------------
  -- Components declaration
@@ -923,7 +923,7 @@ begin

      tm_dac_value_o       => open,
      tm_dac_wr_o          => open,
-      tm_clk_aux_lock_en_i => (others=>'0'),
+      tm_clk_aux_lock_en_i => (others => '0'),
      tm_clk_aux_locked_o  => open,
      tm_time_valid_o      => tm_time_valid,
      tm_tai_o             => tm_seconds,