kernel: synced up registers' headers with the most recent HDL, removed obsolete files

98933e52 · Tomasz Wlostowski · Miguel Jimenez Lopez · 75a74920 · 98933e52 · 75a74920
Commit 98933e52 authored Jun 11, 2012 by Tomasz Wlostowski Committed by Miguel Jimenez Lopez Sep 04, 2019
14 changed files
--- a/kernel/wbgen-regs/Makefile
+++ b/kernel/wbgen-regs/Makefile
 # This Makefile is used to reproduce the headers from svn checkout.
 # You need to have "wbgen2" in your command search path and the white-rabbit
-# svn checkout in $SVN.  Since this is only meant to be used by me,
-# no serious checking is done
-
-# List of input files in SVN checkout
-MODULES = $(SVN)/trunk/hdl/modules
-SPECS = $(SVN)/trunk/documentation/specifications
-
-WB_ENDPOINT = $(MODULES)/wrsw_endpoint/ep_wishbone_controller.wb
-WB_PPSG     = $(MODULES)/wrsw_pps_gen/wrsw_pps_gen.wb
-WB_CALIB    = $(MODULES)/wrsw_calibrator_dmtd/wrsw_calibrator_dmtd.wb
-WB_TSTAMP   = $(MODULES)/wrsw_txtsu/wrsw_txtsu.wb
-WB_RTU      = $(MODULES)/wrsw_rtu/wrsw_rtu_wb.wb
-WB_NIC      = $(SPECS)/hdlspec/WRSW_wbc_internal_NIC/wr_nic.wb
-
-HEADERS = endpoint-regs.h ppsg-regs.h calib-regs.h tstamp-regs.h rtu-regs.h \
-          nic-regs.h
+# repos (wr-cores and wr-switch-hdl) Git checkout in $REPOS.  
+# Since this is only meant to be used by me (or Tom) no serious checking is done.
+
+# List of input files in Git checkout
+
+MODULES_WRS ?= $(REPOS)/wr-switch-hdl/modules
+MODULES_WRC ?= $(REPOS)/wr-hdl/modules
+
+#SPECS = $(HW_REPO)/trunk/documentation/specifications
+
+WB_ENDPOINT = $(MODULES_WRC)/wr_endpoint/ep_wishbone_controller.wb
+WB_MDIO 		= $(MODULES_WRC)/wr_endpoint/pcs_regs.wb
+WB_PPSG     = $(MODULES_WRC)/wr_pps_gen/pps_gen_wb.wb
+WB_TSTAMP   = $(MODULES_WRS)/wrsw_txtsu/wrsw_txtsu.wb
+WB_RTU      = $(MODULES_WRS)/wrsw_rtu/rtu_wishbone_slave.wb
+WB_NIC      = $(MODULES_WRS)/wrsw_nic/wr_nic.wb
+WB_SOFTPLL  = $(MODULES_WRC)/wr_softpll/wr_softpll.wb
+
+HEADERS = endpoint-regs.h endpoint-mdio.h ppsg-regs.h tstamp-regs.h rtu-regs.h \
+          nic-regs.h softpll-regs.h
 WBINPUT = $(HEADERS:.h=wb)

 # No default, for people who types "make" everywhere (like me)
@@ -28,7 +32,7 @@ headers: $(HEADERS)

 %.h: %.wb
 	wbgen2 --cstyle=struct  --co=$@ $<
-	sed -i 's,inttypes.h,linux/types.h,' $@
+	sed -i 's,#include <inttypes.h>,#ifdef __KERNEL__\n#include <linux/types.h>\n#else\n#include <stdint.h>\n#endif\n,' $@
 	sed -i '/ Created *: .*20[0-9][0-9]$$/ d' $@
 	sed -i 's/-REGS_WB//' $@

@@ -37,9 +41,10 @@ headers: $(HEADERS)
 # Do it silent so errors stand out
 wbinput:
 	@cp $(WB_ENDPOINT) endpoint-regs.wb
+	@cp $(WB_MDIO) endpoint-mdio.wb
 	@cp $(WB_PPSG) ppsg-regs.wb
-	@cp $(WB_CALIB) calib-regs.wb
 	@cp $(WB_TSTAMP) tstamp-regs.wb
 	@cp $(WB_RTU) rtu-regs.wb
 	@cp $(WB_NIC) nic-regs.wb
+	@cp $(WB_SOFTPLL) softpll-regs.wb
 	@echo "Copied input files from subversions to local directory"
--- a/kernel/wbgen-regs/calib-regs.h
+++ b/kernel/wbgen-regs/calib-regs.h
-/*
-  Register definitions for slave core: DMTD PHY Calibrator
-
-  * File           : calib-regs.h
-  * Author         : auto-generated by wbgen2 from calib-regs.wb
-  * Standard       : ANSI C
-
-    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE calib-regs.wb
-    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
-
-*/
-
-#ifndef __WBGEN2_REGDEFS_CALIB
-#define __WBGEN2_REGDEFS_CALIB
-
-#include <linux/types.h>
-
-#if defined( __GNUC__)
-#define PACKED __attribute__ ((packed))
-#else
-#error "Unsupported compiler?"
-#endif
-
-#ifndef __WBGEN2_MACROS_DEFINED__
-#define __WBGEN2_MACROS_DEFINED__
-#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
-#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
-#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
-#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
-#endif
-
-
-/* definitions for register: Control Register */
-
-/* definitions for field: Enable in reg: Control Register */
-#define DPC_CR_EN                             WBGEN2_GEN_MASK(0, 1)
-
-/* definitions for field: Compare clock select in reg: Control Register */
-#define DPC_CR_IN_SEL_MASK                    WBGEN2_GEN_MASK(8, 4)
-#define DPC_CR_IN_SEL_SHIFT                   8
-#define DPC_CR_IN_SEL_W(value)                WBGEN2_GEN_WRITE(value, 8, 4)
-#define DPC_CR_IN_SEL_R(reg)                  WBGEN2_GEN_READ(reg, 8, 4)
-
-/* definitions for field: DMTD averaging samples in reg: Control Register */
-#define DPC_CR_N_AVG_MASK                     WBGEN2_GEN_MASK(16, 12)
-#define DPC_CR_N_AVG_SHIFT                    16
-#define DPC_CR_N_AVG_W(value)                 WBGEN2_GEN_WRITE(value, 16, 12)
-#define DPC_CR_N_AVG_R(reg)                   WBGEN2_GEN_READ(reg, 16, 12)
-
-/* definitions for register: Status register */
-
-/* definitions for field: Phase shift value in reg: Status register */
-#define DPC_SR_PS_VAL_MASK                    WBGEN2_GEN_MASK(0, 24)
-#define DPC_SR_PS_VAL_SHIFT                   0
-#define DPC_SR_PS_VAL_W(value)                WBGEN2_GEN_WRITE(value, 0, 24)
-#define DPC_SR_PS_VAL_R(reg)                  WBGEN2_GEN_READ(reg, 0, 24)
-
-/* definitions for field: Phase shift value ready in reg: Status register */
-#define DPC_SR_PS_RDY                         WBGEN2_GEN_MASK(24, 1)
-
-PACKED struct DPC_WB {
-  /* [0x0]: REG Control Register */
-  uint32_t CR;
-  /* [0x4]: REG Status register */
-  uint32_t SR;
-};
-
-#endif
--- a/kernel/wbgen-regs/calib-regs.wb
+++ b/kernel/wbgen-regs/calib-regs.wb
-- -*- Mode: LUA; tab-width: 2 -*-
-
-peripheral {
-	 name = "DMTD PHY Calibrator";
-	 prefix = "dpc";
-	 hdl_entity = "dmtd_calibrator_wb";
-
-	 reg {
-			name = "Control Register";
-			prefix = "CR";
-
-			field {
-				 name = "Enable";
-				 type = BIT;
-				 prefix = "EN";
-				 access_dev = READ_ONLY;
-				 access_bus = READ_WRITE;
-			};
-
-			field {
-				 name = "Compare clock select";
-				 prefix = "IN_SEL";
-				 type = SLV;
-				 size = 4;
-				 align = 8;
-				 access_dev = READ_ONLY;
-				 access_bus = READ_WRITE;
-			};
-
-			field {
-				 name = "DMTD averaging samples";
-				 prefix = "N_AVG";
-				 type = SLV;
-				 size = 12;
-				 align = 16;
-				 access_dev = READ_ONLY;
-				 access_bus = READ_WRITE;
-			};
-	 };
-
-	 reg {
-			name = "Status register";
-			prefix = "SR";
-
-			field {
-				 name = "Phase shift value";
-				 prefix = "PS_VAL";
-				 size = 24;
-				 type = SLV;
-				 access_dev = WRITE_ONLY;
-				 access_bus = READ_ONLY;
-			};
-
-			field {
-				 name = "Phase shift value ready";
-				 prefix = "PS_RDY";
-				 type = BIT;
-				 load = LOAD_EXT;
-				 access_dev = READ_WRITE;
-				 access_bus = READ_WRITE;
-			};
-	 };
-};
-
-
--- a/kernel/wbgen-regs/endpoint-mdio.h
+++ b/kernel/wbgen-regs/endpoint-mdio.h
+/*
+  Register definitions for slave core: WR Endpoint 1000base-X TBI PCS register block
+
+  * File           : endpoint-mdio.h
+  * Author         : auto-generated by wbgen2 from endpoint-mdio.wb
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE endpoint-mdio.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB
+#define __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: MDIO Control Register */
+
+/* definitions for field: Reserved in reg: MDIO Control Register */
+#define MDIO_MCR_RESV_MASK                    WBGEN2_GEN_MASK(0, 5)
+#define MDIO_MCR_RESV_SHIFT                   0
+#define MDIO_MCR_RESV_W(value)                WBGEN2_GEN_WRITE(value, 0, 5)
+#define MDIO_MCR_RESV_R(reg)                  WBGEN2_GEN_READ(reg, 0, 5)
+
+/* definitions for field: Unidirectional Enable in reg: MDIO Control Register */
+#define MDIO_MCR_UNI_EN                       WBGEN2_GEN_MASK(5, 1)
+
+/* definitions for field: Speed Selection (MSB) in reg: MDIO Control Register */
+#define MDIO_MCR_SPEED1000_MASK               WBGEN2_GEN_MASK(6, 1)
+#define MDIO_MCR_SPEED1000_SHIFT              6
+#define MDIO_MCR_SPEED1000_W(value)           WBGEN2_GEN_WRITE(value, 6, 1)
+#define MDIO_MCR_SPEED1000_R(reg)             WBGEN2_GEN_READ(reg, 6, 1)
+
+/* definitions for field: Collision Test in reg: MDIO Control Register */
+#define MDIO_MCR_CTST_MASK                    WBGEN2_GEN_MASK(7, 1)
+#define MDIO_MCR_CTST_SHIFT                   7
+#define MDIO_MCR_CTST_W(value)                WBGEN2_GEN_WRITE(value, 7, 1)
+#define MDIO_MCR_CTST_R(reg)                  WBGEN2_GEN_READ(reg, 7, 1)
+
+/* definitions for field: Duplex Mode in reg: MDIO Control Register */
+#define MDIO_MCR_FULLDPLX_MASK                WBGEN2_GEN_MASK(8, 1)
+#define MDIO_MCR_FULLDPLX_SHIFT               8
+#define MDIO_MCR_FULLDPLX_W(value)            WBGEN2_GEN_WRITE(value, 8, 1)
+#define MDIO_MCR_FULLDPLX_R(reg)              WBGEN2_GEN_READ(reg, 8, 1)
+
+/* definitions for field: Restart Auto-Negotiation in reg: MDIO Control Register */
+#define MDIO_MCR_ANRESTART                    WBGEN2_GEN_MASK(9, 1)
+
+/* definitions for field: Isolate in reg: MDIO Control Register */
+#define MDIO_MCR_ISOLATE_MASK                 WBGEN2_GEN_MASK(10, 1)
+#define MDIO_MCR_ISOLATE_SHIFT                10
+#define MDIO_MCR_ISOLATE_W(value)             WBGEN2_GEN_WRITE(value, 10, 1)
+#define MDIO_MCR_ISOLATE_R(reg)               WBGEN2_GEN_READ(reg, 10, 1)
+
+/* definitions for field: Power Down in reg: MDIO Control Register */
+#define MDIO_MCR_PDOWN                        WBGEN2_GEN_MASK(11, 1)
+
+/* definitions for field: Auto-Negotiation Enable in reg: MDIO Control Register */
+#define MDIO_MCR_ANENABLE                     WBGEN2_GEN_MASK(12, 1)
+
+/* definitions for field: Speed Selection (LSB) in reg: MDIO Control Register */
+#define MDIO_MCR_SPEED100_MASK                WBGEN2_GEN_MASK(13, 1)
+#define MDIO_MCR_SPEED100_SHIFT               13
+#define MDIO_MCR_SPEED100_W(value)            WBGEN2_GEN_WRITE(value, 13, 1)
+#define MDIO_MCR_SPEED100_R(reg)              WBGEN2_GEN_READ(reg, 13, 1)
+
+/* definitions for field: Loopback in reg: MDIO Control Register */
+#define MDIO_MCR_LOOPBACK                     WBGEN2_GEN_MASK(14, 1)
+
+/* definitions for field: Reset in reg: MDIO Control Register */
+#define MDIO_MCR_RESET                        WBGEN2_GEN_MASK(15, 1)
+
+/* definitions for register: MDIO Status Register */
+
+/* definitions for field: Extended Capability in reg: MDIO Status Register */
+#define MDIO_MSR_ERCAP_MASK                   WBGEN2_GEN_MASK(0, 1)
+#define MDIO_MSR_ERCAP_SHIFT                  0
+#define MDIO_MSR_ERCAP_W(value)               WBGEN2_GEN_WRITE(value, 0, 1)
+#define MDIO_MSR_ERCAP_R(reg)                 WBGEN2_GEN_READ(reg, 0, 1)
+
+/* definitions for field: Jabber Detect in reg: MDIO Status Register */
+#define MDIO_MSR_JCD_MASK                     WBGEN2_GEN_MASK(1, 1)
+#define MDIO_MSR_JCD_SHIFT                    1
+#define MDIO_MSR_JCD_W(value)                 WBGEN2_GEN_WRITE(value, 1, 1)
+#define MDIO_MSR_JCD_R(reg)                   WBGEN2_GEN_READ(reg, 1, 1)
+
+/* definitions for field: Link Status in reg: MDIO Status Register */
+#define MDIO_MSR_LSTATUS                      WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Auto-Negotiation Ability in reg: MDIO Status Register */
+#define MDIO_MSR_ANEGCAPABLE_MASK             WBGEN2_GEN_MASK(3, 1)
+#define MDIO_MSR_ANEGCAPABLE_SHIFT            3
+#define MDIO_MSR_ANEGCAPABLE_W(value)         WBGEN2_GEN_WRITE(value, 3, 1)
+#define MDIO_MSR_ANEGCAPABLE_R(reg)           WBGEN2_GEN_READ(reg, 3, 1)
+
+/* definitions for field: Remote Fault in reg: MDIO Status Register */
+#define MDIO_MSR_RFAULT                       WBGEN2_GEN_MASK(4, 1)
+
+/* definitions for field: Auto-Negotiation Complete in reg: MDIO Status Register */
+#define MDIO_MSR_ANEGCOMPLETE                 WBGEN2_GEN_MASK(5, 1)
+
+/* definitions for field: MF Preamble Suppression in reg: MDIO Status Register */
+#define MDIO_MSR_MFSUPPRESS_MASK              WBGEN2_GEN_MASK(6, 1)
+#define MDIO_MSR_MFSUPPRESS_SHIFT             6
+#define MDIO_MSR_MFSUPPRESS_W(value)          WBGEN2_GEN_WRITE(value, 6, 1)
+#define MDIO_MSR_MFSUPPRESS_R(reg)            WBGEN2_GEN_READ(reg, 6, 1)
+
+/* definitions for field: Unidirectional Ability in reg: MDIO Status Register */
+#define MDIO_MSR_UNIDIRABLE_MASK              WBGEN2_GEN_MASK(7, 1)
+#define MDIO_MSR_UNIDIRABLE_SHIFT             7
+#define MDIO_MSR_UNIDIRABLE_W(value)          WBGEN2_GEN_WRITE(value, 7, 1)
+#define MDIO_MSR_UNIDIRABLE_R(reg)            WBGEN2_GEN_READ(reg, 7, 1)
+
+/* definitions for field: Extended Status Capable in reg: MDIO Status Register */
+#define MDIO_MSR_ESTATEN_MASK                 WBGEN2_GEN_MASK(8, 1)
+#define MDIO_MSR_ESTATEN_SHIFT                8
+#define MDIO_MSR_ESTATEN_W(value)             WBGEN2_GEN_WRITE(value, 8, 1)
+#define MDIO_MSR_ESTATEN_R(reg)               WBGEN2_GEN_READ(reg, 8, 1)
+
+/* definitions for field: 100BASE-T2 Half Duplex in reg: MDIO Status Register */
+#define MDIO_MSR_100HALF2_MASK                WBGEN2_GEN_MASK(9, 1)
+#define MDIO_MSR_100HALF2_SHIFT               9
+#define MDIO_MSR_100HALF2_W(value)            WBGEN2_GEN_WRITE(value, 9, 1)
+#define MDIO_MSR_100HALF2_R(reg)              WBGEN2_GEN_READ(reg, 9, 1)
+
+/* definitions for field: 100BASE-T2 Full Duplex in reg: MDIO Status Register */
+#define MDIO_MSR_100FULL2_MASK                WBGEN2_GEN_MASK(10, 1)
+#define MDIO_MSR_100FULL2_SHIFT               10
+#define MDIO_MSR_100FULL2_W(value)            WBGEN2_GEN_WRITE(value, 10, 1)
+#define MDIO_MSR_100FULL2_R(reg)              WBGEN2_GEN_READ(reg, 10, 1)
+
+/* definitions for field: 10 Mbps Half Duplex in reg: MDIO Status Register */
+#define MDIO_MSR_10HALF_MASK                  WBGEN2_GEN_MASK(11, 1)
+#define MDIO_MSR_10HALF_SHIFT                 11
+#define MDIO_MSR_10HALF_W(value)              WBGEN2_GEN_WRITE(value, 11, 1)
+#define MDIO_MSR_10HALF_R(reg)                WBGEN2_GEN_READ(reg, 11, 1)
+
+/* definitions for field: 10 Mbps Full Duplex in reg: MDIO Status Register */
+#define MDIO_MSR_10FULL_MASK                  WBGEN2_GEN_MASK(12, 1)
+#define MDIO_MSR_10FULL_SHIFT                 12
+#define MDIO_MSR_10FULL_W(value)              WBGEN2_GEN_WRITE(value, 12, 1)
+#define MDIO_MSR_10FULL_R(reg)                WBGEN2_GEN_READ(reg, 12, 1)
+
+/* definitions for field: 100BASE-X Half Duplex in reg: MDIO Status Register */
+#define MDIO_MSR_100HALF_MASK                 WBGEN2_GEN_MASK(13, 1)
+#define MDIO_MSR_100HALF_SHIFT                13
+#define MDIO_MSR_100HALF_W(value)             WBGEN2_GEN_WRITE(value, 13, 1)
+#define MDIO_MSR_100HALF_R(reg)               WBGEN2_GEN_READ(reg, 13, 1)
+
+/* definitions for field: 100BASE-X Full Duplex in reg: MDIO Status Register */
+#define MDIO_MSR_100FULL_MASK                 WBGEN2_GEN_MASK(14, 1)
+#define MDIO_MSR_100FULL_SHIFT                14
+#define MDIO_MSR_100FULL_W(value)             WBGEN2_GEN_WRITE(value, 14, 1)
+#define MDIO_MSR_100FULL_R(reg)               WBGEN2_GEN_READ(reg, 14, 1)
+
+/* definitions for field: 100BASE-T4 in reg: MDIO Status Register */
+#define MDIO_MSR_100BASE4_MASK                WBGEN2_GEN_MASK(15, 1)
+#define MDIO_MSR_100BASE4_SHIFT               15
+#define MDIO_MSR_100BASE4_W(value)            WBGEN2_GEN_WRITE(value, 15, 1)
+#define MDIO_MSR_100BASE4_R(reg)              WBGEN2_GEN_READ(reg, 15, 1)
+
+/* definitions for register: MDIO PHY Identification Register 1 */
+
+/* definitions for field:  Organizationally Unique Identifier (bits 7-21) in reg: MDIO PHY Identification Register 1 */
+#define MDIO_PHYSID1_OUI_MASK                 WBGEN2_GEN_MASK(0, 16)
+#define MDIO_PHYSID1_OUI_SHIFT                0
+#define MDIO_PHYSID1_OUI_W(value)             WBGEN2_GEN_WRITE(value, 0, 16)
+#define MDIO_PHYSID1_OUI_R(reg)               WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for register: MDIO PHY Identification Register 2 */
+
+/* definitions for field: Revision Number in reg: MDIO PHY Identification Register 2 */
+#define MDIO_PHYSID2_REV_NUM_MASK             WBGEN2_GEN_MASK(0, 4)
+#define MDIO_PHYSID2_REV_NUM_SHIFT            0
+#define MDIO_PHYSID2_REV_NUM_W(value)         WBGEN2_GEN_WRITE(value, 0, 4)
+#define MDIO_PHYSID2_REV_NUM_R(reg)           WBGEN2_GEN_READ(reg, 0, 4)
+
+/* definitions for field: Manufacturer Model Number in reg: MDIO PHY Identification Register 2 */
+#define MDIO_PHYSID2_MMNUM_MASK               WBGEN2_GEN_MASK(4, 6)
+#define MDIO_PHYSID2_MMNUM_SHIFT              4
+#define MDIO_PHYSID2_MMNUM_W(value)           WBGEN2_GEN_WRITE(value, 4, 6)
+#define MDIO_PHYSID2_MMNUM_R(reg)             WBGEN2_GEN_READ(reg, 4, 6)
+
+/* definitions for field: Organizationally Unique Identifier (bits 0-5) in reg: MDIO PHY Identification Register 2 */
+#define MDIO_PHYSID2_OUI_MASK                 WBGEN2_GEN_MASK(10, 6)
+#define MDIO_PHYSID2_OUI_SHIFT                10
+#define MDIO_PHYSID2_OUI_W(value)             WBGEN2_GEN_WRITE(value, 10, 6)
+#define MDIO_PHYSID2_OUI_R(reg)               WBGEN2_GEN_READ(reg, 10, 6)
+
+/* definitions for register: MDIO Auto-Negotiation Advertisement Register */
+
+/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Advertisement Register */
+#define MDIO_ADVERTISE_RSVD3_MASK             WBGEN2_GEN_MASK(0, 5)
+#define MDIO_ADVERTISE_RSVD3_SHIFT            0
+#define MDIO_ADVERTISE_RSVD3_W(value)         WBGEN2_GEN_WRITE(value, 0, 5)
+#define MDIO_ADVERTISE_RSVD3_R(reg)           WBGEN2_GEN_READ(reg, 0, 5)
+
+/* definitions for field: Full Duplex in reg: MDIO Auto-Negotiation Advertisement Register */
+#define MDIO_ADVERTISE_FULL_MASK              WBGEN2_GEN_MASK(5, 1)
+#define MDIO_ADVERTISE_FULL_SHIFT             5
+#define MDIO_ADVERTISE_FULL_W(value)          WBGEN2_GEN_WRITE(value, 5, 1)
+#define MDIO_ADVERTISE_FULL_R(reg)            WBGEN2_GEN_READ(reg, 5, 1)
+
+/* definitions for field: Half Duplex in reg: MDIO Auto-Negotiation Advertisement Register */
+#define MDIO_ADVERTISE_HALF_MASK              WBGEN2_GEN_MASK(6, 1)
+#define MDIO_ADVERTISE_HALF_SHIFT             6
+#define MDIO_ADVERTISE_HALF_W(value)          WBGEN2_GEN_WRITE(value, 6, 1)
+#define MDIO_ADVERTISE_HALF_R(reg)            WBGEN2_GEN_READ(reg, 6, 1)
+
+/* definitions for field: Pause in reg: MDIO Auto-Negotiation Advertisement Register */
+#define MDIO_ADVERTISE_PAUSE_MASK             WBGEN2_GEN_MASK(7, 2)
+#define MDIO_ADVERTISE_PAUSE_SHIFT            7
+#define MDIO_ADVERTISE_PAUSE_W(value)         WBGEN2_GEN_WRITE(value, 7, 2)
+#define MDIO_ADVERTISE_PAUSE_R(reg)           WBGEN2_GEN_READ(reg, 7, 2)
+
+/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Advertisement Register */
+#define MDIO_ADVERTISE_RSVD2_MASK             WBGEN2_GEN_MASK(9, 3)
+#define MDIO_ADVERTISE_RSVD2_SHIFT            9
+#define MDIO_ADVERTISE_RSVD2_W(value)         WBGEN2_GEN_WRITE(value, 9, 3)
+#define MDIO_ADVERTISE_RSVD2_R(reg)           WBGEN2_GEN_READ(reg, 9, 3)
+
+/* definitions for field: Remote Fault in reg: MDIO Auto-Negotiation Advertisement Register */
+#define MDIO_ADVERTISE_RFAULT_MASK            WBGEN2_GEN_MASK(12, 2)
+#define MDIO_ADVERTISE_RFAULT_SHIFT           12
+#define MDIO_ADVERTISE_RFAULT_W(value)        WBGEN2_GEN_WRITE(value, 12, 2)
+#define MDIO_ADVERTISE_RFAULT_R(reg)          WBGEN2_GEN_READ(reg, 12, 2)
+
+/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Advertisement Register */
+#define MDIO_ADVERTISE_RSVD1_MASK             WBGEN2_GEN_MASK(14, 1)
+#define MDIO_ADVERTISE_RSVD1_SHIFT            14
+#define MDIO_ADVERTISE_RSVD1_W(value)         WBGEN2_GEN_WRITE(value, 14, 1)
+#define MDIO_ADVERTISE_RSVD1_R(reg)           WBGEN2_GEN_READ(reg, 14, 1)
+
+/* definitions for field: Next Page in reg: MDIO Auto-Negotiation Advertisement Register */
+#define MDIO_ADVERTISE_NPAGE_MASK             WBGEN2_GEN_MASK(15, 1)
+#define MDIO_ADVERTISE_NPAGE_SHIFT            15
+#define MDIO_ADVERTISE_NPAGE_W(value)         WBGEN2_GEN_WRITE(value, 15, 1)
+#define MDIO_ADVERTISE_NPAGE_R(reg)           WBGEN2_GEN_READ(reg, 15, 1)
+
+/* definitions for register: MDIO Auto-Negotiation Link Partner Ability Register */
+
+/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Link Partner Ability Register */
+#define MDIO_LPA_RSVD3_MASK                   WBGEN2_GEN_MASK(0, 5)
+#define MDIO_LPA_RSVD3_SHIFT                  0
+#define MDIO_LPA_RSVD3_W(value)               WBGEN2_GEN_WRITE(value, 0, 5)
+#define MDIO_LPA_RSVD3_R(reg)                 WBGEN2_GEN_READ(reg, 0, 5)
+
+/* definitions for field: Full Duplex in reg: MDIO Auto-Negotiation Link Partner Ability Register */
+#define MDIO_LPA_FULL                         WBGEN2_GEN_MASK(5, 1)
+
+/* definitions for field: Half Duplex in reg: MDIO Auto-Negotiation Link Partner Ability Register */
+#define MDIO_LPA_HALF                         WBGEN2_GEN_MASK(6, 1)
+
+/* definitions for field: Pause in reg: MDIO Auto-Negotiation Link Partner Ability Register */
+#define MDIO_LPA_PAUSE_MASK                   WBGEN2_GEN_MASK(7, 2)
+#define MDIO_LPA_PAUSE_SHIFT                  7
+#define MDIO_LPA_PAUSE_W(value)               WBGEN2_GEN_WRITE(value, 7, 2)
+#define MDIO_LPA_PAUSE_R(reg)                 WBGEN2_GEN_READ(reg, 7, 2)
+
+/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Link Partner Ability Register */
+#define MDIO_LPA_RSVD2_MASK                   WBGEN2_GEN_MASK(9, 3)
+#define MDIO_LPA_RSVD2_SHIFT                  9
+#define MDIO_LPA_RSVD2_W(value)               WBGEN2_GEN_WRITE(value, 9, 3)
+#define MDIO_LPA_RSVD2_R(reg)                 WBGEN2_GEN_READ(reg, 9, 3)
+
+/* definitions for field: Remote Fault in reg: MDIO Auto-Negotiation Link Partner Ability Register */
+#define MDIO_LPA_RFAULT_MASK                  WBGEN2_GEN_MASK(12, 2)
+#define MDIO_LPA_RFAULT_SHIFT                 12
+#define MDIO_LPA_RFAULT_W(value)              WBGEN2_GEN_WRITE(value, 12, 2)
+#define MDIO_LPA_RFAULT_R(reg)                WBGEN2_GEN_READ(reg, 12, 2)
+
+/* definitions for field: Acknowledge in reg: MDIO Auto-Negotiation Link Partner Ability Register */
+#define MDIO_LPA_LPACK                        WBGEN2_GEN_MASK(14, 1)
+
+/* definitions for field: Next Page in reg: MDIO Auto-Negotiation Link Partner Ability Register */
+#define MDIO_LPA_NPAGE                        WBGEN2_GEN_MASK(15, 1)
+
+/* definitions for register: MDIO Auto-Negotiation Expansion Register */
+
+/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Expansion Register */
+#define MDIO_EXPANSION_RSVD1_MASK             WBGEN2_GEN_MASK(0, 1)
+#define MDIO_EXPANSION_RSVD1_SHIFT            0
+#define MDIO_EXPANSION_RSVD1_W(value)         WBGEN2_GEN_WRITE(value, 0, 1)
+#define MDIO_EXPANSION_RSVD1_R(reg)           WBGEN2_GEN_READ(reg, 0, 1)
+
+/* definitions for field: Page Received in reg: MDIO Auto-Negotiation Expansion Register */
+#define MDIO_EXPANSION_LWCP_MASK              WBGEN2_GEN_MASK(1, 1)
+#define MDIO_EXPANSION_LWCP_SHIFT             1
+#define MDIO_EXPANSION_LWCP_W(value)          WBGEN2_GEN_WRITE(value, 1, 1)
+#define MDIO_EXPANSION_LWCP_R(reg)            WBGEN2_GEN_READ(reg, 1, 1)
+
+/* definitions for field: Next Page Able in reg: MDIO Auto-Negotiation Expansion Register */
+#define MDIO_EXPANSION_ENABLENPAGE_MASK       WBGEN2_GEN_MASK(2, 1)
+#define MDIO_EXPANSION_ENABLENPAGE_SHIFT      2
+#define MDIO_EXPANSION_ENABLENPAGE_W(value)   WBGEN2_GEN_WRITE(value, 2, 1)
+#define MDIO_EXPANSION_ENABLENPAGE_R(reg)     WBGEN2_GEN_READ(reg, 2, 1)
+
+/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Expansion Register */
+#define MDIO_EXPANSION_RSVD2_MASK             WBGEN2_GEN_MASK(3, 13)
+#define MDIO_EXPANSION_RSVD2_SHIFT            3
+#define MDIO_EXPANSION_RSVD2_W(value)         WBGEN2_GEN_WRITE(value, 3, 13)
+#define MDIO_EXPANSION_RSVD2_R(reg)           WBGEN2_GEN_READ(reg, 3, 13)
+
+/* definitions for register: MDIO Extended Status Register */
+
+/* definitions for field: Reserved in reg: MDIO Extended Status Register */
+#define MDIO_ESTATUS_RSVD1_MASK               WBGEN2_GEN_MASK(0, 12)
+#define MDIO_ESTATUS_RSVD1_SHIFT              0
+#define MDIO_ESTATUS_RSVD1_W(value)           WBGEN2_GEN_WRITE(value, 0, 12)
+#define MDIO_ESTATUS_RSVD1_R(reg)             WBGEN2_GEN_READ(reg, 0, 12)
+
+/* definitions for field: 1000Base-T Half Duplex in reg: MDIO Extended Status Register */
+#define MDIO_ESTATUS_1000_THALF_MASK          WBGEN2_GEN_MASK(12, 1)
+#define MDIO_ESTATUS_1000_THALF_SHIFT         12
+#define MDIO_ESTATUS_1000_THALF_W(value)      WBGEN2_GEN_WRITE(value, 12, 1)
+#define MDIO_ESTATUS_1000_THALF_R(reg)        WBGEN2_GEN_READ(reg, 12, 1)
+
+/* definitions for field: 1000Base-T Full Duplex in reg: MDIO Extended Status Register */
+#define MDIO_ESTATUS_1000_TFULL_MASK          WBGEN2_GEN_MASK(13, 1)
+#define MDIO_ESTATUS_1000_TFULL_SHIFT         13
+#define MDIO_ESTATUS_1000_TFULL_W(value)      WBGEN2_GEN_WRITE(value, 13, 1)
+#define MDIO_ESTATUS_1000_TFULL_R(reg)        WBGEN2_GEN_READ(reg, 13, 1)
+
+/* definitions for field: 1000Base-X Half Duplex in reg: MDIO Extended Status Register */
+#define MDIO_ESTATUS_1000_XHALF_MASK          WBGEN2_GEN_MASK(14, 1)
+#define MDIO_ESTATUS_1000_XHALF_SHIFT         14
+#define MDIO_ESTATUS_1000_XHALF_W(value)      WBGEN2_GEN_WRITE(value, 14, 1)
+#define MDIO_ESTATUS_1000_XHALF_R(reg)        WBGEN2_GEN_READ(reg, 14, 1)
+
+/* definitions for field: 1000Base-X Full Duplex in reg: MDIO Extended Status Register */
+#define MDIO_ESTATUS_1000_XFULL_MASK          WBGEN2_GEN_MASK(15, 1)
+#define MDIO_ESTATUS_1000_XFULL_SHIFT         15
+#define MDIO_ESTATUS_1000_XFULL_W(value)      WBGEN2_GEN_WRITE(value, 15, 1)
+#define MDIO_ESTATUS_1000_XFULL_R(reg)        WBGEN2_GEN_READ(reg, 15, 1)
+
+/* definitions for register: WhiteRabbit-specific Configuration Register */
+
+/* definitions for field: TX Calibration Pattern in reg: WhiteRabbit-specific Configuration Register */
+#define MDIO_WR_SPEC_TX_CAL                   WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Calibration Pattern RX Status in reg: WhiteRabbit-specific Configuration Register */
+#define MDIO_WR_SPEC_RX_CAL_STAT              WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Reset calibration counter in reg: WhiteRabbit-specific Configuration Register */
+#define MDIO_WR_SPEC_CAL_CRST                 WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: GTP RX Bitslide in reg: WhiteRabbit-specific Configuration Register */
+#define MDIO_WR_SPEC_BSLIDE_MASK              WBGEN2_GEN_MASK(4, 5)
+#define MDIO_WR_SPEC_BSLIDE_SHIFT             4
+#define MDIO_WR_SPEC_BSLIDE_W(value)          WBGEN2_GEN_WRITE(value, 4, 5)
+#define MDIO_WR_SPEC_BSLIDE_R(reg)            WBGEN2_GEN_READ(reg, 4, 5)
+
+PACKED struct MDIO_WB {
+  /* [0x0]: REG MDIO Control Register */
+  uint32_t MCR;
+  /* [0x4]: REG MDIO Status Register */
+  uint32_t MSR;
+  /* [0x8]: REG MDIO PHY Identification Register 1 */
+  uint32_t PHYSID1;
+  /* [0xc]: REG MDIO PHY Identification Register 2 */
+  uint32_t PHYSID2;
+  /* [0x10]: REG MDIO Auto-Negotiation Advertisement Register */
+  uint32_t ADVERTISE;
+  /* [0x14]: REG MDIO Auto-Negotiation Link Partner Ability Register */
+  uint32_t LPA;
+  /* [0x18]: REG MDIO Auto-Negotiation Expansion Register */
+  uint32_t EXPANSION;
+  /* padding to: 15 words */
+  uint32_t __padding_0[8];
+  /* [0x3c]: REG MDIO Extended Status Register */
+  uint32_t ESTATUS;
+  /* [0x40]: REG WhiteRabbit-specific Configuration Register */
+  uint32_t WR_SPEC;
+};
+
+#endif
--- a/kernel/wbgen-regs/endpoint-mdio.wb
+++ b/kernel/wbgen-regs/endpoint-mdio.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+-------------------------------------------------------------------------------
+-- Title      : 802.3 PCS Register Block (slave)
+-- Project    : White Rabbit MAC/Endpoint
+-------------------------------------------------------------------------------
+-- File       : pcs_regs.wb
+-- Author     : Tomasz Włostowski
+-- Company    : CERN BE-CO-HT
+-- Created    : 2010-11-18
+-- Last update: 2011-10-18
+-------------------------------------------------------------------------------
+-- Description: Standard PCS register block + WR-specific PCS fields: 
+-- RX bitslide and calibration pattern control.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1l.html
+--
+-------------------------------------------------------------------------------
+
+peripheral {
+	 name = "WR Endpoint 1000base-X TBI PCS register block";
+	 hdl_entity = "ep_pcs_tbi_mdio_wb";
+	 prefix = "MDIO";
+
+	 reg {
+			name = "MDIO Control Register";
+			prefix = "MCR";
+
+			field {
+				 name = "Reserved";
+				 description = "Always return 0s, writes ignored.";
+				 prefix = "RESV";
+				 type = CONSTANT;
+				 size = 5;
+				 value = 0;
+			};
+
+			field {
+				 name = "Unidirectional Enable";
+				 description = "1 = Enable transmit regardless of whether a valid link has been established\
+				 0 = Normal operation";
+
+				 prefix = "uni_en";
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+
+			};
+
+			field {
+				 name = "Speed Selection (MSB)";
+				 description = "Always 1, indicating (together with bit 13) a fixed speed of 1000 Mbps";
+				 prefix = "SPEED1000";
+				 type = CONSTANT;
+				 size = 1;
+				 value  = 1;
+			};
+
+
+			field {
+				 name = "Collision Test";
+				 description = "Always equal to 0, since collision detection is not supported";
+				 prefix = "ctst";
+				 type = CONSTANT;
+				 size = 1;
+				 value  = 0;
+			};
+
+
+
+			field {
+				 name = "Duplex Mode";
+				 description = "Always equal to 1 to indicate Full-Duplex operation";
+				 prefix = "fulldplx";
+				 type = CONSTANT;
+				 size = 1;
+				 value  = 1;
+			};
+
+
+			field {
+				 name = "Restart Auto-Negotiation";
+				 description = "write 1 = restart Auto-Negotiation process\
+				 write 0 = no effect";
+
+				 prefix = "anrestart";
+				 type = MONOSTABLE;
+			};
+
+
+			field {
+				 name = "Isolate";
+				 description = "GMII Electrical isolation enable. Ignored since the PCS doesn't use GMII";
+				 prefix = "isolate";
+				 size = 1;
+				 type = CONSTANT;
+				 value  = 0;
+			};
+
+
+			field {
+				 name = "Power Down";
+				 description = "1 = Power down \
+				 0 = Normal operation \
+				 This bit controls directly the PHY Enable pin";
+				 
+				 prefix = "pdown";
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+
+
+			};
+
+			field  {
+				 name = "Auto-Negotiation Enable";
+				 description = "1 = Enable Auto-Negotiation process \
+				 0 = Disable Auto-Negotiation process";
+				 prefix = "anenable";
+				 align = 12;
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+			};
+
+
+			field {
+				 name = "Speed Selection (LSB)";
+				 description = "Always 0, indicating (together with bit 6) a fixed speed of 1000 Mbps";
+				 align = 13;
+				 prefix = "SPEED100";
+				 size = 1;
+				 type = CONSTANT;
+				 value = 0;
+			};
+
+			field {
+				 name = "Loopback";
+				 description = "1 = enable loopback mode \
+				 0 = disable loopback mode \
+				 With the TBI version, loopback bit is connected to PHY loopback enable pin. When set to 1, indicates to the external PHY to enter loopback mode";
+
+				 prefix = "loopback";
+				 align = 14;
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+			};
+
+			field {
+				 name = "Reset";
+				 description = "write 1 = triggers reset of the PCS core\
+				 write 0 = no effect";
+
+				 align = 15;
+
+				 prefix = "reset";
+				 type = MONOSTABLE;
+			};
+	 };
+
+
+
+	 reg {
+			name = "MDIO Status Register";
+			prefix = "MSR";
+			--  options = READ_STROBE;
+
+			field {
+				 name = "Extended Capability";
+				 description = "Always 0, since extended register set is not supported";
+				 prefix = "ERCAP";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+
+			field {
+				 name = "Jabber Detect";
+				 description = "Always 0, since Jabber Detect is not supported";
+				 prefix = "JCD";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+			field {
+				 name = "Link Status";
+				 description = "1 = Link is up\
+				 0 = Link is down (or has been down)\
+				 Latches '0' if Link Status goes down. Clears to current Link Status on read.";
+				 prefix = "LSTATUS";
+				 type = BIT;
+				 access_bus=READ_ONLY;
+				 access_dev=WRITE_ONLY;
+				 ack_read="lstat_read_notify_o";
+			};
+
+
+			field {
+				 name = "Auto-Negotiation Ability";
+				 description = "Always 1, to indicate the support for Auto-Negotiation.";
+				 prefix = "ANEGCAPABLE";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 1;
+			};
+
+			field {
+				 name = "Remote Fault";
+				 description = "1 = Remote fault condition detected\
+				 0 = No remote fault condition detected\
+				 The bit clears itself after being read by the host.";
+				 prefix = "RFAULT";
+
+				 type = BIT;
+				 access_bus=READ_ONLY;
+				 access_dev=WRITE_ONLY;
+			};
+
+
+			field {
+				 name = "Auto-Negotiation Complete";
+				 description = "1 = Auto-Negotiation process completed\
+				 0 = Auto-Negotiation process not completed";
+				 prefix = "anegcomplete";
+				 type = BIT;
+				 access_bus=READ_ONLY;
+				 access_dev=WRITE_ONLY;
+			};
+
+			field {
+				 name = "MF Preamble Suppression";
+				 description = "Always 0, feature not supported. ";
+				 prefix = "mfsuppress";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+
+			field {
+				 name = "Unidirectional Ability";
+				 description = "Always 1, as the Unidirectional mode is supported. ";
+				 prefix = "unidirable";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 1;
+			};
+
+			field {
+				 name = "Extended Status Capable";
+				 description = "Always 1, indicating the presence of the Extended Status Register";
+				 prefix = "estaten";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 1;
+			};
+
+			field {
+				 name = "100BASE-T2 Half Duplex";
+				 description = "Always 0 (unsupported medium)";
+				 prefix = "100half2";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+			field {
+				 name = "100BASE-T2 Full Duplex";
+				 description = "Always 0 (unsupported medium)";
+				 prefix = "100full2";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+			
+
+			field {
+				 name = "10 Mbps Half Duplex";
+				 description = "Always 0 (unsupported medium)";
+				 prefix = "10half";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+			field {
+				 name = "10 Mbps Full Duplex";
+				 description = "Always 0 (unsupported medium)";
+				 prefix = "10full";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+
+			field {
+				 name = "100BASE-X Half Duplex";
+				 description = "Always 0 (unsupported medium)";
+				 prefix = "100half";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+
+			field {
+				 name = "100BASE-X Full Duplex";
+				 description = "Always 0 (unsupported medium)";
+				 prefix = "100full";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+			
+			field {
+				 name = "100BASE-T4";
+				 description = "Always 0 (unsupported medium)";
+				 prefix = "100base4";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+	 };
+
+
+	 reg {
+			name = "MDIO PHY Identification Register 1";
+			prefix = "PHYSID1";
+
+			field {
+				 name = " Organizationally Unique Identifier (bits 7-21)";
+				 description = "Always 0.";
+				 prefix = "OUI";
+				 type = CONSTANT;
+				 size = 16;
+				 value = 0;
+			};
+	 };
+
+	 reg {
+			name = "MDIO PHY Identification Register 2";
+			prefix = "PHYSID2";
+
+			field {
+				 name = "Revision Number";
+				 description = "Always 0.";
+				 prefix = "REV_NUM";
+				 type = CONSTANT;
+				 size = 4;
+				 value = 0;
+			};
+
+			field {
+				 name = "Manufacturer Model Number";
+				 description = "Always 0.";
+				 prefix = "MMNUM";
+				 type = CONSTANT;
+				 size = 6;
+				 value = 0;
+			};
+
+			field {
+				 name = "Organizationally Unique Identifier (bits 0-5)";
+				 description = "Always 0.";
+				 prefix = "OUI";
+				 type = CONSTANT;
+				 size = 6;
+				 value = 0;
+			};
+
+
+
+	 };
+
+	 reg {
+			name = "MDIO Auto-Negotiation Advertisement Register";
+			prefix = "ADVERTISE";
+
+			field {
+				 name = "Reserved";
+				 description = "Always 0.";
+				 prefix = "RSVD3";
+				 type = CONSTANT;
+				 size = 5;
+				 value = 0;
+			};
+
+			field {
+				 name = "Full Duplex";
+				 description = "Always 1, since Full Duplex Mode is the only supported mode.";
+				 prefix = "FULL";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 1;
+			};
+			
+			field {
+				 name = "Half Duplex";
+				 description = "Always 0, since Half Duplex Mode is not supported.";
+				 prefix = "HALF";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+			field {
+				 name = "Pause";
+				 description = "00 = No PAUSE\
+				 01 = Symmetric PAUSE \
+				 10 = Asymmetric PAUSE towards link partner\
+				 11 = Both Symmetric PAUSE and Asymmetric PAUSE towards link partner";
+
+				 prefix = "PAUSE";
+				 type = SLV;
+				 size = 2;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+			};
+
+			field {
+				 name = "Reserved";
+				 description = "Always 0.";
+				 prefix = "RSVD2";
+				 type = CONSTANT;
+				 size = 3;
+				 value = 0;
+			};
+
+			field {
+				 name = "Remote Fault";
+				 description = "00 = No Error \
+				 01 = Offline \
+				 10 = Link Failure \
+				 11 = Auto-Negotiation Error";
+
+				 prefix = "RFAULT";
+				 type = SLV;
+				 size = 2;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+			};
+
+			field {
+				 name = "Reserved";
+				 description = "Always 0.";
+				 prefix = "RSVD1";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+			field {
+				 name = "Next Page";
+				 description = "Always 0, since Next Page feature is not supported";
+				 prefix = "NPAGE";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+	 };
+
+
+
+
+
+	 reg {
+			name = "MDIO Auto-Negotiation Link Partner Ability Register";
+			prefix = "LPA";
+
+			field {
+				 name = "Reserved";
+				 description = "Always 0.";
+				 prefix = "RSVD3";
+				 type = CONSTANT;
+				 size = 5;
+				 value = 0;
+			};
+
+			field {
+				 name = "Full Duplex";
+				 description = "1 = Remote partner supports Full Duplex operation\
+				                0 = It doesn't";
+
+				 prefix = "FULL";
+
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+			
+			field {
+				 name = "Half Duplex";
+				 description = "1 = Remote partner supports Half Duplex operation\
+				                0 = It doesn't";
+				 prefix = "HALF";
+
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+
+			field {
+				 name = "Pause";
+				 description = "00 = No PAUSE\
+				 01 = Symmetric PAUSE \
+				 10 = Asymmetric PAUSE towards link partner\
+				 11 = Both Symmetric PAUSE and Asymmetric PAUSE towards link partner";
+
+				 prefix = "PAUSE";
+				 type = SLV;
+
+				 size = 2;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+
+			field {
+				 name = "Reserved";
+				 description = "Always 0.";
+				 prefix = "RSVD2";
+				 type = CONSTANT;
+				 size = 3;
+				 value = 0;
+			};
+
+			field {
+				 name = "Remote Fault";
+				 description = "00 = No Error \
+				 01 = Offline \
+				 10 = Link Failure \
+				 11 = Auto-Negotiation Error";
+
+				 prefix = "RFAULT";
+				 type = SLV;
+				 size = 2;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+
+			};
+
+			field {
+				 name = "Acknowledge";
+				 description = "Used by Auto-Negotiation function to indicate reception of a link partner's base or next page.";
+				 prefix = "LPACK";
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+
+			field {
+				 name = "Next Page";
+				 description = "1 = Next Page functionality is supported\
+				                0 = It isn't";
+				 prefix = "NPAGE";
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+	 };
+
+
+	 reg {
+			name = "MDIO Auto-Negotiation Expansion Register";
+			prefix = "EXPANSION";
+
+			field {
+				 name = "Reserved";
+				 description = "Always 0.";
+				 prefix = "RSVD1";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+			field {
+				 name = "Page Received";
+				 description = "Always 0, since we don't support the Next Page function";
+				 prefix = "LWCP";	
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+		};
+
+			field {
+				 name = "Next Page Able";
+				 description = "Always 0, since we don't support the Next Page function";
+				 prefix = "ENABLENPAGE";
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+			};
+
+			field {
+				 name = "Reserved";
+				 description = "Always 0.";
+				 prefix = "RSVD2";
+				 type = CONSTANT;
+				 size = 13;
+				 value = 0;
+			};
+	 };
+
+
+	 reg {
+			name = "MDIO Extended Status Register";
+			prefix = "ESTATUS";
+			align=15;
+
+			field {
+				 name = "Reserved";
+				 description = "Always 0.";
+				 prefix = "RSVD1";
+				 type = CONSTANT;
+				 size = 12;
+				 value = 0;
+			};
+
+			field {
+				 name = "1000Base-T Half Duplex";
+				 description = "Always 0, since this mode is not supported.";
+				 prefix = "1000_THALF";	
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+		};
+			field {
+				 name = "1000Base-T Full Duplex";
+				 description = "Always 0, since this mode is not supported.";
+				 prefix = "1000_TFULL";	
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+		};
+
+			field {
+				 name = "1000Base-X Half Duplex";
+				 description = "Always 0, since this mode is not supported.";
+				 prefix = "1000_XHALF";	
+				 type = CONSTANT;
+				 size = 1;
+				 value = 0;
+		};
+			field {
+				 name = "1000Base-X Full Duplex";
+				 description = "Always 1, indicating the support for 1000Base-X Full Duplex mode.";
+				 prefix = "1000_XFULL";	
+				 type = CONSTANT;
+				 size = 1;
+				 value = 1;
+		};
+	 };
+
+	 reg {
+			name = "WhiteRabbit-specific Configuration Register";
+			prefix = "WR_SPEC";
+
+			field {
+				 name = "TX Calibration Pattern";
+				 description = "Controls the transmission of WR PHY calibration pattern. \
+				                1 = PCS is sending calibration pattern\
+				                0 = Normal PCS operation";
+				 prefix = "TX_CAL";
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+				 clock = "tx_clk_i";
+				 
+			};
+
+			field {
+				 name = "Calibration Pattern RX Status";
+				 description = "1 = Valid calibration pattern is being received\
+				                0 = no calibration pattern detected by the receiver";
+				 prefix = "RX_CAL_STAT";
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+				 clock = "rx_clk_i";
+			};
+
+		field {
+			 name = "Reset calibration counter";
+			 prefix = "CAL_CRST";
+			 description = "1: resets the calibration pattern valid counter. \
+			 0: no effect";
+			 type = MONOSTABLE;
+			 clock = "rx_clk_i";
+		};
+
+		field {
+			 name = "GTP RX Bitslide";
+			 prefix = "BSLIDE";
+			 description = "Current receive path bit slide (valid only for Xilinx GTP/GTX versions)";
+			 type = SLV;
+			 size = 5;
+			 align = 4;
+			 access_bus = READ_ONLY;
+			 access_dev = WRITE_ONLY;
+			 clock = "rx_clk_i";
+		};
+ };
+};
+
--- a/kernel/wbgen-regs/endpoint-regs.h
+++ b/kernel/wbgen-regs/endpoint-regs.h
@@ -13,7 +13,12 @@
 #ifndef __WBGEN2_REGDEFS_ENDPOINT
 #define __WBGEN2_REGDEFS_ENDPOINT

+#ifdef __KERNEL__
 #include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))
@@ -265,6 +270,7 @@
 /* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
 #define EP_DMSR_PS_RDY                        WBGEN2_GEN_MASK(24, 1)
 /* definitions for RAM: Event counters memory */
+#define EP_RMON_RAM_BASE 0x00000080 /* base address */                                
 #define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */                               
 #define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */        


--- a/kernel/wbgen-regs/nic-regs.h
+++ b/kernel/wbgen-regs/nic-regs.h
@@ -13,7 +13,12 @@
 #ifndef __WBGEN2_REGDEFS_NIC
 #define __WBGEN2_REGDEFS_NIC

+#ifdef __KERNEL__
 #include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))
@@ -46,6 +51,24 @@
 /* definitions for field: Frame Received in reg: NIC Status Register */
 #define NIC_SR_REC                            WBGEN2_GEN_MASK(1, 1)

+/* definitions for field: Transmission done in reg: NIC Status Register */
+#define NIC_SR_TX_DONE                        WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Transmission error in reg: NIC Status Register */
+#define NIC_SR_TX_ERROR                       WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for field: Current TX descriptor in reg: NIC Status Register */
+#define NIC_SR_CUR_TX_DESC_MASK               WBGEN2_GEN_MASK(8, 3)
+#define NIC_SR_CUR_TX_DESC_SHIFT              8
+#define NIC_SR_CUR_TX_DESC_W(value)           WBGEN2_GEN_WRITE(value, 8, 3)
+#define NIC_SR_CUR_TX_DESC_R(reg)             WBGEN2_GEN_READ(reg, 8, 3)
+
+/* definitions for field: Current RX descriptor in reg: NIC Status Register */
+#define NIC_SR_CUR_RX_DESC_MASK               WBGEN2_GEN_MASK(16, 3)
+#define NIC_SR_CUR_RX_DESC_SHIFT              16
+#define NIC_SR_CUR_RX_DESC_W(value)           WBGEN2_GEN_WRITE(value, 16, 3)
+#define NIC_SR_CUR_RX_DESC_R(reg)             WBGEN2_GEN_READ(reg, 16, 3)
+
 /* definitions for register: SW_Reset */

 /* definitions for register: TX Descriptor 1 register 1 */
@@ -71,16 +94,16 @@
 /* definitions for register: TX Descriptor 1 register 2 */

 /* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 1 register 2 */
-#define NIC_TX1_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_TX1_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_TX1_D2_OFFSET_SHIFT               0
-#define NIC_TX1_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_TX1_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_TX1_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_TX1_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

-/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 1 register 2 */
-#define NIC_TX1_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 1 register 2 */
+#define NIC_TX1_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_TX1_D2_LEN_SHIFT                  16
-#define NIC_TX1_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_TX1_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_TX1_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_TX1_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: TX Descriptor 1 register 3 */

@@ -113,16 +136,16 @@
 /* definitions for register: TX Descriptor 2 register 2 */

 /* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 2 register 2 */
-#define NIC_TX2_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_TX2_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_TX2_D2_OFFSET_SHIFT               0
-#define NIC_TX2_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_TX2_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_TX2_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_TX2_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

-/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 2 register 2 */
-#define NIC_TX2_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 2 register 2 */
+#define NIC_TX2_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_TX2_D2_LEN_SHIFT                  16
-#define NIC_TX2_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_TX2_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_TX2_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_TX2_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: TX Descriptor 2 register 3 */

@@ -155,16 +178,16 @@
 /* definitions for register: TX Descriptor 3 register 2 */

 /* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 3 register 2 */
-#define NIC_TX3_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_TX3_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_TX3_D2_OFFSET_SHIFT               0
-#define NIC_TX3_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_TX3_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_TX3_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_TX3_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

-/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 3 register 2 */
-#define NIC_TX3_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 3 register 2 */
+#define NIC_TX3_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_TX3_D2_LEN_SHIFT                  16
-#define NIC_TX3_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_TX3_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_TX3_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_TX3_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: TX Descriptor 3 register 3 */

@@ -197,16 +220,16 @@
 /* definitions for register: TX Descriptor 4 register 2 */

 /* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 4 register 2 */
-#define NIC_TX4_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_TX4_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_TX4_D2_OFFSET_SHIFT               0
-#define NIC_TX4_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_TX4_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_TX4_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_TX4_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

-/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 4 register 2 */
-#define NIC_TX4_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 4 register 2 */
+#define NIC_TX4_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_TX4_D2_LEN_SHIFT                  16
-#define NIC_TX4_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_TX4_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_TX4_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_TX4_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: TX Descriptor 4 register 3 */

@@ -239,16 +262,16 @@
 /* definitions for register: TX Descriptor 5 register 2 */

 /* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 5 register 2 */
-#define NIC_TX5_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_TX5_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_TX5_D2_OFFSET_SHIFT               0
-#define NIC_TX5_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_TX5_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_TX5_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_TX5_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

-/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 5 register 2 */
-#define NIC_TX5_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 5 register 2 */
+#define NIC_TX5_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_TX5_D2_LEN_SHIFT                  16
-#define NIC_TX5_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_TX5_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_TX5_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_TX5_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: TX Descriptor 5 register 3 */

@@ -281,16 +304,16 @@
 /* definitions for register: TX Descriptor 6 register 2 */

 /* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 6 register 2 */
-#define NIC_TX6_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_TX6_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_TX6_D2_OFFSET_SHIFT               0
-#define NIC_TX6_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_TX6_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_TX6_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_TX6_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

-/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 6 register 2 */
-#define NIC_TX6_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 6 register 2 */
+#define NIC_TX6_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_TX6_D2_LEN_SHIFT                  16
-#define NIC_TX6_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_TX6_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_TX6_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_TX6_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: TX Descriptor 6 register 3 */

@@ -323,16 +346,16 @@
 /* definitions for register: TX Descriptor 7 register 2 */

 /* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 7 register 2 */
-#define NIC_TX7_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_TX7_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_TX7_D2_OFFSET_SHIFT               0
-#define NIC_TX7_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_TX7_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_TX7_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_TX7_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

-/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 7 register 2 */
-#define NIC_TX7_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 7 register 2 */
+#define NIC_TX7_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_TX7_D2_LEN_SHIFT                  16
-#define NIC_TX7_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_TX7_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_TX7_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_TX7_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: TX Descriptor 7 register 3 */

@@ -365,16 +388,16 @@
 /* definitions for register: TX Descriptor 8 register 2 */

 /* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 8 register 2 */
-#define NIC_TX8_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_TX8_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_TX8_D2_OFFSET_SHIFT               0
-#define NIC_TX8_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_TX8_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_TX8_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_TX8_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

-/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 8 register 2 */
-#define NIC_TX8_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 8 register 2 */
+#define NIC_TX8_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_TX8_D2_LEN_SHIFT                  16
-#define NIC_TX8_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_TX8_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_TX8_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_TX8_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: TX Descriptor 8 register 3 */

@@ -401,7 +424,7 @@
 /* definitions for field: Got RX Timestamp in reg: RX Descriptor 1 register 1 */
 #define NIC_RX1_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

-/* definitions for field: RX timestamp (possibly) incorrect in reg: RX Descriptor 1 register 1 */
+/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 1 register 1 */
 #define NIC_RX1_D1_TS_INCORRECT               WBGEN2_GEN_MASK(15, 1)

 /* definitions for register: RX Descriptor 1 register 2 */
@@ -421,16 +444,16 @@
 /* definitions for register: RX Descriptor 1 register 3 */

 /* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 1 register 3 */
-#define NIC_RX1_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_RX1_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_RX1_D3_OFFSET_SHIFT               0
-#define NIC_RX1_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_RX1_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_RX1_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_RX1_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

 /* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 1 register 3 */
-#define NIC_RX1_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+#define NIC_RX1_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_RX1_D3_LEN_SHIFT                  16
-#define NIC_RX1_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_RX1_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_RX1_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_RX1_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: RX Descriptor 2 register 1 */

@@ -449,7 +472,7 @@
 /* definitions for field: Got RX Timestamp in reg: RX Descriptor 2 register 1 */
 #define NIC_RX2_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

-/* definitions for field: RX timestamp (possibly) incorrect in reg: RX Descriptor 2 register 1 */
+/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 2 register 1 */
 #define NIC_RX2_D1_TS_INCORRECT               WBGEN2_GEN_MASK(15, 1)

 /* definitions for register: RX Descriptor 2 register 2 */
@@ -469,16 +492,16 @@
 /* definitions for register: RX Descriptor 2 register 3 */

 /* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 2 register 3 */
-#define NIC_RX2_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_RX2_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_RX2_D3_OFFSET_SHIFT               0
-#define NIC_RX2_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_RX2_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_RX2_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_RX2_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

 /* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 2 register 3 */
-#define NIC_RX2_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+#define NIC_RX2_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_RX2_D3_LEN_SHIFT                  16
-#define NIC_RX2_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_RX2_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_RX2_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_RX2_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: RX Descriptor 3 register 1 */

@@ -497,7 +520,7 @@
 /* definitions for field: Got RX Timestamp in reg: RX Descriptor 3 register 1 */
 #define NIC_RX3_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

-/* definitions for field: RX timestamp (possibly) incorrect in reg: RX Descriptor 3 register 1 */
+/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 3 register 1 */
 #define NIC_RX3_D1_TS_INCORRECT               WBGEN2_GEN_MASK(15, 1)

 /* definitions for register: RX Descriptor 3 register 2 */
@@ -517,16 +540,16 @@
 /* definitions for register: RX Descriptor 3 register 3 */

 /* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 3 register 3 */
-#define NIC_RX3_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_RX3_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_RX3_D3_OFFSET_SHIFT               0
-#define NIC_RX3_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_RX3_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_RX3_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_RX3_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

 /* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 3 register 3 */
-#define NIC_RX3_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+#define NIC_RX3_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_RX3_D3_LEN_SHIFT                  16
-#define NIC_RX3_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_RX3_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_RX3_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_RX3_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: RX Descriptor 4 register 1 */

@@ -545,7 +568,7 @@
 /* definitions for field: Got RX Timestamp in reg: RX Descriptor 4 register 1 */
 #define NIC_RX4_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

-/* definitions for field: RX timestamp (possibly) incorrect in reg: RX Descriptor 4 register 1 */
+/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 4 register 1 */
 #define NIC_RX4_D1_TS_INCORRECT               WBGEN2_GEN_MASK(15, 1)

 /* definitions for register: RX Descriptor 4 register 2 */
@@ -565,16 +588,16 @@
 /* definitions for register: RX Descriptor 4 register 3 */

 /* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 4 register 3 */
-#define NIC_RX4_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_RX4_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_RX4_D3_OFFSET_SHIFT               0
-#define NIC_RX4_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_RX4_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_RX4_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_RX4_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

 /* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 4 register 3 */
-#define NIC_RX4_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+#define NIC_RX4_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_RX4_D3_LEN_SHIFT                  16
-#define NIC_RX4_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_RX4_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_RX4_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_RX4_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: RX Descriptor 5 register 1 */

@@ -593,7 +616,7 @@
 /* definitions for field: Got RX Timestamp in reg: RX Descriptor 5 register 1 */
 #define NIC_RX5_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

-/* definitions for field: RX timestamp (possibly) incorrect in reg: RX Descriptor 5 register 1 */
+/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 5 register 1 */
 #define NIC_RX5_D1_TS_INCORRECT               WBGEN2_GEN_MASK(15, 1)

 /* definitions for register: RX Descriptor 5 register 2 */
@@ -613,16 +636,16 @@
 /* definitions for register: RX Descriptor 5 register 3 */

 /* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 5 register 3 */
-#define NIC_RX5_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_RX5_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_RX5_D3_OFFSET_SHIFT               0
-#define NIC_RX5_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_RX5_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_RX5_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_RX5_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

 /* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 5 register 3 */
-#define NIC_RX5_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+#define NIC_RX5_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_RX5_D3_LEN_SHIFT                  16
-#define NIC_RX5_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_RX5_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_RX5_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_RX5_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: RX Descriptor 6 register 1 */

@@ -641,7 +664,7 @@
 /* definitions for field: Got RX Timestamp in reg: RX Descriptor 6 register 1 */
 #define NIC_RX6_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

-/* definitions for field: RX timestamp (possibly) incorrect in reg: RX Descriptor 6 register 1 */
+/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 6 register 1 */
 #define NIC_RX6_D1_TS_INCORRECT               WBGEN2_GEN_MASK(15, 1)

 /* definitions for register: RX Descriptor 6 register 2 */
@@ -661,16 +684,16 @@
 /* definitions for register: RX Descriptor 6 register 3 */

 /* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 6 register 3 */
-#define NIC_RX6_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_RX6_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_RX6_D3_OFFSET_SHIFT               0
-#define NIC_RX6_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_RX6_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_RX6_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_RX6_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

 /* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 6 register 3 */
-#define NIC_RX6_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+#define NIC_RX6_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_RX6_D3_LEN_SHIFT                  16
-#define NIC_RX6_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_RX6_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_RX6_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_RX6_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: RX Descriptor 7 register 1 */

@@ -689,7 +712,7 @@
 /* definitions for field: Got RX Timestamp in reg: RX Descriptor 7 register 1 */
 #define NIC_RX7_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

-/* definitions for field: RX timestamp (possibly) incorrect in reg: RX Descriptor 7 register 1 */
+/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 7 register 1 */
 #define NIC_RX7_D1_TS_INCORRECT               WBGEN2_GEN_MASK(15, 1)

 /* definitions for register: RX Descriptor 7 register 2 */
@@ -709,16 +732,16 @@
 /* definitions for register: RX Descriptor 7 register 3 */

 /* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 7 register 3 */
-#define NIC_RX7_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_RX7_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_RX7_D3_OFFSET_SHIFT               0
-#define NIC_RX7_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_RX7_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_RX7_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_RX7_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

 /* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 7 register 3 */
-#define NIC_RX7_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+#define NIC_RX7_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_RX7_D3_LEN_SHIFT                  16
-#define NIC_RX7_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_RX7_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_RX7_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_RX7_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: RX Descriptor 8 register 1 */

@@ -737,7 +760,7 @@
 /* definitions for field: Got RX Timestamp in reg: RX Descriptor 8 register 1 */
 #define NIC_RX8_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

-/* definitions for field: RX timestamp (possibly) incorrect in reg: RX Descriptor 8 register 1 */
+/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 8 register 1 */
 #define NIC_RX8_D1_TS_INCORRECT               WBGEN2_GEN_MASK(15, 1)

 /* definitions for register: RX Descriptor 8 register 2 */
@@ -757,16 +780,16 @@
 /* definitions for register: RX Descriptor 8 register 3 */

 /* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 8 register 3 */
-#define NIC_RX8_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
+#define NIC_RX8_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 13)
 #define NIC_RX8_D3_OFFSET_SHIFT               0
-#define NIC_RX8_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
-#define NIC_RX8_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)
+#define NIC_RX8_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 13)
+#define NIC_RX8_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 13)

 /* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 8 register 3 */
-#define NIC_RX8_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
+#define NIC_RX8_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 13)
 #define NIC_RX8_D3_LEN_SHIFT                  16
-#define NIC_RX8_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
-#define NIC_RX8_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)
+#define NIC_RX8_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 13)
+#define NIC_RX8_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 13)

 /* definitions for register: Interrupt disable register */

@@ -776,11 +799,8 @@
 /* definitions for field: Transmit Complete in reg: Interrupt disable register */
 #define NIC_EIC_IDR_TCOMP                     WBGEN2_GEN_MASK(1, 1)

-/* definitions for field: Receive Error in reg: Interrupt disable register */
-#define NIC_EIC_IDR_RXERR                     WBGEN2_GEN_MASK(2, 1)
-
 /* definitions for field: Transmit Error in reg: Interrupt disable register */
-#define NIC_EIC_IDR_TXERR                     WBGEN2_GEN_MASK(3, 1)
+#define NIC_EIC_IDR_TXERR                     WBGEN2_GEN_MASK(2, 1)

 /* definitions for register: Interrupt enable register */

@@ -790,11 +810,8 @@
 /* definitions for field: Transmit Complete in reg: Interrupt enable register */
 #define NIC_EIC_IER_TCOMP                     WBGEN2_GEN_MASK(1, 1)

-/* definitions for field: Receive Error in reg: Interrupt enable register */
-#define NIC_EIC_IER_RXERR                     WBGEN2_GEN_MASK(2, 1)
-
 /* definitions for field: Transmit Error in reg: Interrupt enable register */
-#define NIC_EIC_IER_TXERR                     WBGEN2_GEN_MASK(3, 1)
+#define NIC_EIC_IER_TXERR                     WBGEN2_GEN_MASK(2, 1)

 /* definitions for register: Interrupt mask register */

@@ -804,11 +821,8 @@
 /* definitions for field: Transmit Complete in reg: Interrupt mask register */
 #define NIC_EIC_IMR_TCOMP                     WBGEN2_GEN_MASK(1, 1)

-/* definitions for field: Receive Error in reg: Interrupt mask register */
-#define NIC_EIC_IMR_RXERR                     WBGEN2_GEN_MASK(2, 1)
-
 /* definitions for field: Transmit Error in reg: Interrupt mask register */
-#define NIC_EIC_IMR_TXERR                     WBGEN2_GEN_MASK(3, 1)
+#define NIC_EIC_IMR_TXERR                     WBGEN2_GEN_MASK(2, 1)

 /* definitions for register: Interrupt status register */

@@ -818,11 +832,8 @@
 /* definitions for field: Transmit Complete in reg: Interrupt status register */
 #define NIC_EIC_ISR_TCOMP                     WBGEN2_GEN_MASK(1, 1)

-/* definitions for field: Receive Error in reg: Interrupt status register */
-#define NIC_EIC_ISR_RXERR                     WBGEN2_GEN_MASK(2, 1)
-
 /* definitions for field: Transmit Error in reg: Interrupt status register */
-#define NIC_EIC_ISR_TXERR                     WBGEN2_GEN_MASK(3, 1)
+#define NIC_EIC_ISR_TXERR                     WBGEN2_GEN_MASK(2, 1)
 /* definitions for RAM: TX/RX Buffers */
 #define NIC_MEM_BASE 0x00008000 /* base address */                                
 #define NIC_MEM_BYTES 0x00008000 /* size in bytes */                               

--- a/kernel/wbgen-regs/nic-regs.wb
+++ b/kernel/wbgen-regs/nic-regs.wb
@@ -75,10 +75,10 @@ top = peripheral {
      field {
 				 name = "Buffer Not Available";
 				 prefix = "bna";
-				 description = "No buffers were available when receiving a packet. Cleared by writing a one to this bit";
+				 description = "No buffers were available when receiving a packet.";
 				 type = BIT;
-				 access_bus = READ_WRITE;
-				 access_dev = READ_WRITE;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
 				 load = LOAD_EXT;
      };

@@ -92,6 +92,57 @@ top = peripheral {
 				 access_dev = READ_WRITE;
 				 load = LOAD_EXT;
      };
+
+      field {
+				 name = "Transmission done";
+				 prefix = "tx_done";
+				 description = "read 1: All non-empty TX descriptors have been transmitted\
+				                read 0: Transmission in progress\
+				 write 1: Clears the flag\
+				 write 0: No effect";
+
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_WRITE;
+				 load = LOAD_EXT;
+      };
+
+      field {
+				 name = "Transmission error";
+				 prefix = "tx_error";
+				 description = "read 1: A TX error occured and the transmission was stopped. CUR_TX_DESC is pointing the TX descriptor for which the error occured\
+				                read 0: No TX error\
+				 write 1: Clears the flag\
+				 write 0: No effect";
+
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_WRITE;
+				 load = LOAD_EXT;
+      };
+
+
+			field {
+				 align = 8;
+				 name = "Current TX descriptor";
+				 size = 3;
+				 prefix = "cur_TX_Desc";
+				 description = "Index of the currently handled TX descriptor";
+				 type = SLV;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+
+			field {
+				 align = 8;
+				 name = "Current RX descriptor";
+				 size = 3;
+				 prefix = "cur_RX_DESC";
+				 description = "Index of the currently handled RX descriptor";
+				 type = SLV;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
   };


@@ -109,6 +160,7 @@ top = peripheral {
 	 irq {
      name = "Receive Complete";
      prefix = "rcomp";
+      ack_line = true;
      description = "A frame has been stored in memory.";
      trigger = LEVEL_1;
   };
@@ -116,20 +168,17 @@ top = peripheral {
   irq {
      name = "Transmit Complete";
      prefix = "tcomp";
+      ack_line = true;
+			mask_line = true;
      description = "Frame successfully transmitted";
      trigger = LEVEL_1;
   };

-   irq {
-      name = "Receive Error";
-      prefix = "rxerr";
-      description = "Receive Error";
-      trigger = LEVEL_1;
-   };
-
   irq {
      name = "Transmit Error";
      prefix = "txerr";
+      ack_line = true;
+			mask_line = true;
      trigger = LEVEL_1;
   };

@@ -138,31 +187,30 @@ top = peripheral {
 --			prefix = "dtx";
 --			size = 32;
 --			width = 32;
- --     access_bus = READ_WRITE;
-  --    access_dev = READ_WRITE;
-	-- };
+--      access_bus = READ_WRITE;
+--      access_dev = READ_WRITE;
+--	 };

-	-- ram {
-	--		name = "RX descriptors mem";
+--	 ram {
+--			name = "RX descriptors mem";
 --			prefix = "drx";
 --			size = 32;
 --			width = 32;
- --     access_bus = READ_WRITE;
-  --    access_dev = READ_WRITE;
-	-- };
+--      access_bus = READ_WRITE;
+--      access_dev = READ_WRITE;
+--	 };


-   ram {
-      name = "TX/RX Buffers";
-      prefix = "mem";
-      -- 8192 * 32 = 32Kb
-      size = 8192;
-      width = 32;
-      access_bus = READ_WRITE;
-      access_dev = READ_WRITE;
-
-   };
+    ram {
+       name = "TX/RX Buffers";
+       prefix = "mem";
+       -- 8192 * 32 = 32Kb
+       size = 8192;
+       width = 32;
+       access_bus = READ_WRITE;
+       access_dev = READ_WRITE;

+    };
 };


@@ -235,21 +283,20 @@ TX_desc_template =
      name = "TX Descriptor %d register 2";
      prefix = "tx%d_d2";

-- extended the sizes to 16 bits (although the buffer is 32kB-long)
      field {
 				 name = "offset in RAM--in bytes, must be aligned to 32-bit boundary";
 				 prefix = "offset";
 				 type = SLV;
-				 size = 16;
+				 size = 13;
 				 access_bus = READ_WRITE;
 				 access_dev = READ_ONLY;
      };

      field {
-				 name = "Length of buffer in bytes";
+				 name = "Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2)";
 				 prefix = "len";
 				 type = SLV;
-				 size = 16;
+				 size = 13;
 				 align = 16;
 				 access_bus = READ_WRITE;
 				 access_dev = READ_ONLY;
@@ -320,18 +367,17 @@ RX_desc_template = {
 				 access_dev = WRITE_ONLY;
      };

-      field {
-				 name = "RX timestamp (possibly) incorrect";
-				 prefix = "TS_INCORRECT";
-				 description = "read 1: the RX timestamp in R2 register may be incorrect, because it has been generated during counter adjustment,\
-				 								read 0: the RX timestamp in R2 register is correct";
-
-				 type = BIT;
-				 access_bus = READ_ONLY;
-				 access_dev = WRITE_ONLY;
+     field {
+         name = "RX Timestamp (possibly) incorrect";
+         prefix = "TS_INCORRECT";
+         align = 15;
+         description = "1 - there is a risk that the timestamp in RX_D2 is invalid, because it was taken during counter adjustment,\
+         0 - RX timestamp OK.";
+         type = BIT;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
      };
-      
-      
+
   };

 	 
@@ -342,8 +388,8 @@ RX_desc_template = {
      
      field {
 				 name = "RX_TS_R";
-				 description = "Value of the RX timestamp (rising edge bits)";
 				 prefix = "TS_R";
+				 description = "Value of the RX timestamp (rising edge bits)";
 				 size = 28;
 				 type = SLV;
 				 access_bus = READ_ONLY;
@@ -369,7 +415,7 @@ RX_desc_template = {
 				 name = "Offset in packet RAM (in bytes, 32-bit aligned)";
 				 prefix = "offset";
 				 type = SLV;
-				 size = 16;
+				 size = 13;
 				 access_bus = READ_WRITE;
 				 access_dev = READ_ONLY;
      },
@@ -378,7 +424,7 @@ RX_desc_template = {
 				 name = "Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet.";
 				 prefix = "len";
 				 type = SLV;
-				 size = 16;
+				 size = 13;
 				 align = 16;
 				 access_bus = READ_WRITE;
 				 access_dev = READ_WRITE;

--- a/kernel/wbgen-regs/ppsg-regs.h
+++ b/kernel/wbgen-regs/ppsg-regs.h
@@ -13,7 +13,12 @@
 #ifndef __WBGEN2_REGDEFS_PPSG
 #define __WBGEN2_REGDEFS_PPSG

+#ifdef __KERNEL__
 #include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))
@@ -62,6 +67,17 @@

 /* definitions for register: UTC Adjustment register (most-significant part) */

+/* definitions for register: External sync control register */
+
+/* definitions for field: Sync to external PPS input in reg: External sync control register */
+#define PPSG_ESCR_SYNC                        WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: PPS output valid in reg: External sync control register */
+#define PPSG_ESCR_PPS_VALID                   WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
+#define PPSG_ESCR_TM_VALID                    WBGEN2_GEN_MASK(2, 1)
+
 PACKED struct PPSG_WB {
  /* [0x0]: REG Control Register */
  uint32_t CR;
@@ -77,6 +93,8 @@ PACKED struct PPSG_WB {
  uint32_t ADJ_UTCLO;
  /* [0x18]: REG UTC Adjustment register (most-significant part) */
  uint32_t ADJ_UTCHI;
+  /* [0x1c]: REG External sync control register */
+  uint32_t ESCR;
 };

 #endif
--- a/kernel/wbgen-regs/ppsg-regs.wb
+++ b/kernel/wbgen-regs/ppsg-regs.wb
@@ -56,6 +56,7 @@ peripheral {
 				 clock = "refclk_i";
 			};

+
 			field {
 				 name = "PPS Pulse width";
 				 description = "Width of generated PPS pulses in 125 MHz refernce clock cycles";
@@ -151,6 +152,46 @@ peripheral {
 			};
 	 };

+	 reg {
+			name = "External sync control register";
+			prefix = "ESCR";
+			
+			field {
+				 name = "Sync to external PPS input";
+				 description = "write 1: Waits until a pulse on external PPS input arrives and re-synchronizes the PPS counter to it\
+				 write 0: no effect\
+				 read 1: external synchronization done\
+				 read 0: external synchronization in progress";
+				 type = BIT;
+				 prefix = "SYNC";
+				 access_bus = READ_WRITE;
+				 access_dev = READ_WRITE;
+				 load = LOAD_EXT;
+				 clock = "refclk_i";
+			};
+
+      field {
+         name = "PPS output valid";
+         description = "write 1: PPS output provides reliable 1-PPS signal\
+                        write 0: PPS output is invalid";
+         prefix = "PPS_VALID";
+         type = BIT;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+         clock = "refclk_i";
+      };
+
+      field {
+         name = "Timecode output(UTC+cycles) valid";
+         description = "write 1: Timecode output provides valid time\
+                        write 0: Timecode output does not provide valid time";
+         prefix = "TM_VALID";
+         type = BIT;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+         clock = "refclk_i";
+      };

+	 };

 };
--- a/kernel/wbgen-regs/rtu-regs.h
+++ b/kernel/wbgen-regs/rtu-regs.h
@@ -13,7 +13,12 @@
 #ifndef __WBGEN2_REGDEFS_RTU
 #define __WBGEN2_REGDEFS_RTU

+#ifdef __KERNEL__
 #include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))

--- a/kernel/wbgen-regs/softpll-regs.h
+++ b/kernel/wbgen-regs/softpll-regs.h
+/*
+  Register definitions for slave core: WR Softcore PLL
+
+  * File           : softpll-regs.h
+  * Author         : auto-generated by wbgen2 from softpll-regs.wb
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE softpll-regs.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_SOFTPLL
+#define __WBGEN2_REGDEFS_SOFTPLL
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: SPLL Control/Status Register */
+
+/* definitions for field: Tagger enable in reg: SPLL Control/Status Register */
+#define SPLL_CSR_TAG_EN_MASK                  WBGEN2_GEN_MASK(0, 4)
+#define SPLL_CSR_TAG_EN_SHIFT                 0
+#define SPLL_CSR_TAG_EN_W(value)              WBGEN2_GEN_WRITE(value, 0, 4)
+#define SPLL_CSR_TAG_EN_R(reg)                WBGEN2_GEN_READ(reg, 0, 4)
+
+/* definitions for field: Tag ready in reg: SPLL Control/Status Register */
+#define SPLL_CSR_TAG_RDY_MASK                 WBGEN2_GEN_MASK(4, 4)
+#define SPLL_CSR_TAG_RDY_SHIFT                4
+#define SPLL_CSR_TAG_RDY_W(value)             WBGEN2_GEN_WRITE(value, 4, 4)
+#define SPLL_CSR_TAG_RDY_R(reg)               WBGEN2_GEN_READ(reg, 4, 4)
+
+/* definitions for field: Aux clock locking enable in reg: SPLL Control/Status Register */
+#define SPLL_CSR_AUX_EN                       WBGEN2_GEN_MASK(8, 1)
+
+/* definitions for field: Aux clock locked flag (to slave) in reg: SPLL Control/Status Register */
+#define SPLL_CSR_AUX_LOCK                     WBGEN2_GEN_MASK(9, 1)
+
+/* definitions for register: HPLL Frequency Error */
+
+/* definitions for register: DMPLL Tag ref */
+
+/* definitions for register: DMPLL Tag fb */
+
+/* definitions for register: DMPLL Tag aux */
+
+/* definitions for register: HPLL DAC Output */
+
+/* definitions for register: DMPLL DAC Output */
+
+/* definitions for register: AUX DAC Output */
+
+/* definitions for register: Deglitcher threshold */
+
+/* definitions for register: Interrupt disable register */
+
+/* definitions for field: Got a tag in reg: Interrupt disable register */
+#define SPLL_EIC_IDR_TAG                      WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for register: Interrupt enable register */
+
+/* definitions for field: Got a tag in reg: Interrupt enable register */
+#define SPLL_EIC_IER_TAG                      WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for register: Interrupt mask register */
+
+/* definitions for field: Got a tag in reg: Interrupt mask register */
+#define SPLL_EIC_IMR_TAG                      WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for register: Interrupt status register */
+
+/* definitions for field: Got a tag in reg: Interrupt status register */
+#define SPLL_EIC_ISR_TAG                      WBGEN2_GEN_MASK(0, 1)
+
+PACKED struct SPLL_WB {
+  /* [0x0]: REG SPLL Control/Status Register */
+  uint32_t CSR;
+  /* [0x4]: REG HPLL Frequency Error */
+  uint32_t PER_HPLL;
+  /* [0x8]: REG DMPLL Tag ref */
+  uint32_t TAG_REF;
+  /* [0xc]: REG DMPLL Tag fb */
+  uint32_t TAG_FB;
+  /* [0x10]: REG DMPLL Tag aux */
+  uint32_t TAG_AUX;
+  /* [0x14]: REG HPLL DAC Output */
+  uint32_t DAC_HPLL;
+  /* [0x18]: REG DMPLL DAC Output */
+  uint32_t DAC_DMPLL;
+  /* [0x1c]: REG AUX DAC Output */
+  uint32_t DAC_AUX;
+  /* [0x20]: REG Deglitcher threshold */
+  uint32_t DEGLITCH_THR;
+  /* padding to: 16 words */
+  uint32_t __padding_0[7];
+  /* [0x40]: REG Interrupt disable register */
+  uint32_t EIC_IDR;
+  /* [0x44]: REG Interrupt enable register */
+  uint32_t EIC_IER;
+  /* [0x48]: REG Interrupt mask register */
+  uint32_t EIC_IMR;
+  /* [0x4c]: REG Interrupt status register */
+  uint32_t EIC_ISR;
+};
+
+#endif
--- a/kernel/wbgen-regs/softpll-regs.wb
+++ b/kernel/wbgen-regs/softpll-regs.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+	 name = "WR Softcore PLL";
+	 hdl_entity = "softpll_wb";
+	 prefix = "SPLL";
+	 
+	 reg {
+			name = "SPLL Control/Status Register";
+			prefix = "CSR";
+			
+				field {
+					 name = "Tagger enable";
+					 prefix = "TAG_EN";
+					 type = SLV;
+					 size = 4;
+					 access_bus = READ_WRITE;
+					 access_dev = READ_ONLY;
+				};
+				
+				field {
+					 name = "Tag ready";
+					 prefix = "TAG_RDY";
+					 type = SLV;
+					 size = 4;
+					 access_bus = READ_ONLY;
+					 access_dev = WRITE_ONLY;
+				};
+
+        field {
+           name = "Aux clock locking enable";
+           prefix = "AUX_EN";
+           type = BIT;
+					 access_bus = READ_ONLY;
+					 access_dev = WRITE_ONLY;
+        };
+
+        field {
+           name = "Aux clock locked flag (to slave)";
+           prefix = "AUX_LOCK";
+           type = BIT;
+					 access_bus = READ_WRITE;
+					 access_dev = READ_ONLY;
+        };
+
+		 };
+
+		 reg {
+				name = "HPLL Frequency Error";
+				prefix = "PER_HPLL";
+				
+				field {
+					 name = "Period error value";
+					 type = SLV;
+					 size = 32;
+					 access_bus = READ_ONLY;
+					 access_dev = WRITE_ONLY;
+					 ack_read = "tag_hpll_rd_period_o";
+
+				};
+		 };
+
+		 reg {
+				name = "DMPLL Tag ref";
+				prefix = "TAG_REF";
+				
+				field {
+					 name = "Tag value";
+					 type = SLV;
+					 size = 32;
+					 access_bus = READ_ONLY;
+					 access_dev = WRITE_ONLY;
+					 ack_read = "tag_ref_rd_ack_o";
+				};
+		 };
+
+		 reg {
+				name = "DMPLL Tag fb";
+				prefix = "TAG_FB";
+				
+				field {
+					 name = "Tag value";
+					 type = SLV;
+					 size = 32;
+					 access_bus = READ_ONLY;
+					 access_dev = WRITE_ONLY;
+					 ack_read = "tag_fb_rd_ack_o";
+
+				};
+		 };
+
+	 reg {
+				name = "DMPLL Tag aux";
+				prefix = "TAG_AUX";
+				
+				field {
+					 name = "Tag value";
+					 type = SLV;
+					 size = 32;
+					 access_bus = READ_ONLY;
+					 access_dev = WRITE_ONLY;
+					 ack_read = "tag_aux_rd_ack_o";
+				};
+		 };
+
+		 reg {
+				name = "HPLL DAC Output";
+				prefix = "DAC_HPLL";
+				
+				field {
+					 name = "DAC value";
+					 type = PASS_THROUGH;
+					 size = 16;
+				};
+		 };
+
+		 reg {
+				name = "DMPLL DAC Output";
+				prefix = "DAC_DMPLL";
+				
+				field {
+					 name = "DAC value";
+					 type = PASS_THROUGH;
+					 size = 16;
+				};
+		 }; 
+
+     reg {
+				name = "AUX DAC Output";
+				prefix = "DAC_AUX";
+				
+				field {
+					 name = "DAC value";
+					 type = PASS_THROUGH;
+					 size = 24;
+				};
+		 };
+
+		 reg {
+				name = "Deglitcher threshold";
+				prefix = "DEGLITCH_THR";
+				
+				field {
+					 name = "Threshold";
+					 type = SLV;
+					 size = 16;
+					 access_bus = READ_WRITE;
+					 access_dev = READ_ONLY;
+				};
+		 };
+
+
+		  irq {
+		  		name = "Got a tag";
+		  		prefix = "TAG";
+		  		trigger = LEVEL_1;
+		  };
+	};
+
+
--- a/kernel/wbgen-regs/tstamp-regs.h
+++ b/kernel/wbgen-regs/tstamp-regs.h
@@ -13,7 +13,12 @@
 #ifndef __WBGEN2_REGDEFS_TSTAMP
 #define __WBGEN2_REGDEFS_TSTAMP

+#ifdef __KERNEL__
 #include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))