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White Rabbit Network Interface Card
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99e35c71
Commit
99e35c71
authored
Mar 06, 2013
by
Grzegorz Daniluk
Committed by
Miguel Jimenez Lopez
Sep 04, 2019
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adding kernel driver for PSTATS counters
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c9c8850c
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pstats-regs.h
kernel/wbgen-regs/pstats-regs.h
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kernel/wbgen-regs/pstats-regs.h
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99e35c71
/*
Register definitions for slave core: WR Switch Per-Port Statistic Counters
* File : pstats_regs.h
* Author : auto-generated by wbgen2 from wrsw_pstats.wb
* Created : Tue Feb 26 09:43:21 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pstats.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_PSTATS_WB
#define __WBGEN2_REGDEFS_WRSW_PSTATS_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Enable transfer of counter content in reg: Control Register */
#define PSTATS_CR_RD_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Enable transfer of per-counter IRQ state in reg: Control Register */
#define PSTATS_CR_RD_IRQ WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number in reg: Control Register */
#define PSTATS_CR_PORT_MASK WBGEN2_GEN_MASK(8, 5)
#define PSTATS_CR_PORT_SHIFT 8
#define PSTATS_CR_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 5)
#define PSTATS_CR_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 5)
/* definitions for field: Memory address in reg: Control Register */
#define PSTATS_CR_ADDR_MASK WBGEN2_GEN_MASK(16, 5)
#define PSTATS_CR_ADDR_SHIFT 16
#define PSTATS_CR_ADDR_W(value) WBGEN2_GEN_WRITE(value, 16, 5)
#define PSTATS_CR_ADDR_R(reg) WBGEN2_GEN_READ(reg, 16, 5)
/* definitions for register: L1 Counter Value/First word of per-counter IRQ state */
/* definitions for register: L2 Counter Value */
/* definitions for register: Debug register */
/* definitions for field: Events overflow in reg: Debug register */
#define PSTATS_DBG_EVT_OV_MASK WBGEN2_GEN_MASK(0, 8)
#define PSTATS_DBG_EVT_OV_SHIFT 0
#define PSTATS_DBG_EVT_OV_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define PSTATS_DBG_EVT_OV_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: Counters overflow in reg: Debug register */
#define PSTATS_DBG_CNT_OV_MASK WBGEN2_GEN_MASK(8, 8)
#define PSTATS_DBG_CNT_OV_SHIFT 8
#define PSTATS_DBG_CNT_OV_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define PSTATS_DBG_CNT_OV_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: L2 Events overflow in reg: Debug register */
#define PSTATS_DBG_L2_EVT_OV_MASK WBGEN2_GEN_MASK(16, 1)
#define PSTATS_DBG_L2_EVT_OV_SHIFT 16
#define PSTATS_DBG_L2_EVT_OV_W(value) WBGEN2_GEN_WRITE(value, 16, 1)
#define PSTATS_DBG_L2_EVT_OV_R(reg) WBGEN2_GEN_READ(reg, 16, 1)
/* definitions for field: L2 Counters overflow in reg: Debug register */
#define PSTATS_DBG_L2_CNT_OV_MASK WBGEN2_GEN_MASK(17, 1)
#define PSTATS_DBG_L2_CNT_OV_SHIFT 17
#define PSTATS_DBG_L2_CNT_OV_W(value) WBGEN2_GEN_WRITE(value, 17, 1)
#define PSTATS_DBG_L2_CNT_OV_R(reg) WBGEN2_GEN_READ(reg, 17, 1)
/* definitions for field: L2 Clear flags in reg: Debug register */
#define PSTATS_DBG_L2_CLR WBGEN2_GEN_MASK(30, 1)
/* definitions for field: Clear flags in reg: Debug register */
#define PSTATS_DBG_CLR WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Interrupt disable register */
/* definitions for field: Port0 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Port1 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port2 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Port3 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Port4 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Port5 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT5 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Port6 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT6 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Port7 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT7 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Port8 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT8 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Port9 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT9 WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Port10 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT10 WBGEN2_GEN_MASK(10, 1)
/* definitions for field: Port11 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT11 WBGEN2_GEN_MASK(11, 1)
/* definitions for field: Port12 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT12 WBGEN2_GEN_MASK(12, 1)
/* definitions for field: Port13 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT13 WBGEN2_GEN_MASK(13, 1)
/* definitions for field: Port14 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT14 WBGEN2_GEN_MASK(14, 1)
/* definitions for field: Port15 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT15 WBGEN2_GEN_MASK(15, 1)
/* definitions for field: Port16 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT16 WBGEN2_GEN_MASK(16, 1)
/* definitions for field: Port17 IRQ in reg: Interrupt disable register */
#define PSTATS_EIC_IDR_PORT17 WBGEN2_GEN_MASK(17, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: Port0 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Port1 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port2 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Port3 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Port4 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Port5 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT5 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Port6 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT6 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Port7 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT7 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Port8 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT8 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Port9 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT9 WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Port10 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT10 WBGEN2_GEN_MASK(10, 1)
/* definitions for field: Port11 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT11 WBGEN2_GEN_MASK(11, 1)
/* definitions for field: Port12 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT12 WBGEN2_GEN_MASK(12, 1)
/* definitions for field: Port13 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT13 WBGEN2_GEN_MASK(13, 1)
/* definitions for field: Port14 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT14 WBGEN2_GEN_MASK(14, 1)
/* definitions for field: Port15 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT15 WBGEN2_GEN_MASK(15, 1)
/* definitions for field: Port16 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT16 WBGEN2_GEN_MASK(16, 1)
/* definitions for field: Port17 IRQ in reg: Interrupt enable register */
#define PSTATS_EIC_IER_PORT17 WBGEN2_GEN_MASK(17, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: Port0 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Port1 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port2 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Port3 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Port4 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Port5 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT5 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Port6 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT6 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Port7 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT7 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Port8 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT8 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Port9 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT9 WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Port10 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT10 WBGEN2_GEN_MASK(10, 1)
/* definitions for field: Port11 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT11 WBGEN2_GEN_MASK(11, 1)
/* definitions for field: Port12 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT12 WBGEN2_GEN_MASK(12, 1)
/* definitions for field: Port13 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT13 WBGEN2_GEN_MASK(13, 1)
/* definitions for field: Port14 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT14 WBGEN2_GEN_MASK(14, 1)
/* definitions for field: Port15 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT15 WBGEN2_GEN_MASK(15, 1)
/* definitions for field: Port16 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT16 WBGEN2_GEN_MASK(16, 1)
/* definitions for field: Port17 IRQ in reg: Interrupt mask register */
#define PSTATS_EIC_IMR_PORT17 WBGEN2_GEN_MASK(17, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: Port0 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Port1 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port2 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Port3 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Port4 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT4 WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Port5 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT5 WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Port6 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT6 WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Port7 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT7 WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Port8 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT8 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Port9 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT9 WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Port10 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT10 WBGEN2_GEN_MASK(10, 1)
/* definitions for field: Port11 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT11 WBGEN2_GEN_MASK(11, 1)
/* definitions for field: Port12 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT12 WBGEN2_GEN_MASK(12, 1)
/* definitions for field: Port13 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT13 WBGEN2_GEN_MASK(13, 1)
/* definitions for field: Port14 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT14 WBGEN2_GEN_MASK(14, 1)
/* definitions for field: Port15 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT15 WBGEN2_GEN_MASK(15, 1)
/* definitions for field: Port16 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT16 WBGEN2_GEN_MASK(16, 1)
/* definitions for field: Port17 IRQ in reg: Interrupt status register */
#define PSTATS_EIC_ISR_PORT17 WBGEN2_GEN_MASK(17, 1)
PACKED
struct
PSTATS_WB
{
/* [0x0]: REG Control Register */
uint32_t
CR
;
/* [0x4]: REG L1 Counter Value/First word of per-counter IRQ state */
uint32_t
L1_CNT_VAL
;
/* [0x8]: REG L2 Counter Value */
uint32_t
L2_CNT_VAL
;
/* [0xc]: REG Debug register */
uint32_t
DBG
;
/* padding to: 8 words */
uint32_t
__padding_0
[
4
];
/* [0x20]: REG Interrupt disable register */
uint32_t
EIC_IDR
;
/* [0x24]: REG Interrupt enable register */
uint32_t
EIC_IER
;
/* [0x28]: REG Interrupt mask register */
uint32_t
EIC_IMR
;
/* [0x2c]: REG Interrupt status register */
uint32_t
EIC_ISR
;
};
#endif
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