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a6ea7146
Commit
a6ea7146
authored
Jul 25, 2013
by
Benoit Rat
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syn: correct error using virtex6 chipscope file instead of spartan6
parent
918c26b8
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1 changed file
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317 additions
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298 deletions
+317
-298
wr_nic.xise
syn/spec/wr_nic.xise
+317
-298
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syn/spec/wr_nic.xise
View file @
a6ea7146
...
@@ -46,7 +46,7 @@
...
@@ -46,7 +46,7 @@
<property
xil_pn:name=
"Change Device Speed To"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To Post Trace"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To Post Trace"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Combinatorial Logic Optimization"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Combinatorial Logic Optimization"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile EDK Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"
non-
default"
/>
<property
xil_pn:name=
"Compile EDK Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile SIMPRIM (Timing) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile SIMPRIM (Timing) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile UNISIM (Functional) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile UNISIM (Functional) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile XilinxCoreLib (CORE Generator) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile XilinxCoreLib (CORE Generator) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
...
@@ -78,6 +78,7 @@
...
@@ -78,6 +78,7 @@
<property
xil_pn:name=
"Enable Cyclic Redundancy Checking (CRC) spartan6"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Cyclic Redundancy Checking (CRC) spartan6"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Debugging of Serial Mode BitStream"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Debugging of Serial Mode BitStream"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable External Master Clock spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable External Master Clock spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Hardware Co-Simulation"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Internal Done Pipe"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Internal Done Pipe"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Message Filtering"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Message Filtering"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Multi-Pin Wake-Up Suspend Mode spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Multi-Pin Wake-Up Suspend Mode spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
@@ -217,6 +218,7 @@
...
@@ -217,6 +218,7 @@
<property
xil_pn:name=
"Preferred Language"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Preferred Language"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Produce Verbose Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Produce Verbose Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Project Description"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Project Description"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Project Generator"
xil_pn:value=
"ProjNav"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Property Specification in Project File"
xil_pn:value=
"Store all values"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Property Specification in Project File"
xil_pn:value=
"Store all values"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Style"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Style"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
...
@@ -307,7 +309,7 @@
...
@@ -307,7 +309,7 @@
<property
xil_pn:name=
"Use Synchronous Reset"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synchronous Reset"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synchronous Set"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synchronous Set"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synthesis Constraints File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synthesis Constraints File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"User Browsed Strategy Files"
xil_pn:value=
"/
opt/Xilinx/14.5
/ISE_DS/ISE/data/default.xds"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"User Browsed Strategy Files"
xil_pn:value=
"/
home/opt/Xilinx/14.4
/ISE_DS/ISE/data/default.xds"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"UserID Code (8 Digit Hexadecimal)"
xil_pn:value=
"0xFFFFFFFF"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"UserID Code (8 Digit Hexadecimal)"
xil_pn:value=
"0xFFFFFFFF"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VCCAUX Voltage Level spartan6"
xil_pn:value=
"2.5V"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VCCAUX Voltage Level spartan6"
xil_pn:value=
"2.5V"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VHDL Source Analysis Standard"
xil_pn:value=
"VHDL-93"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VHDL Source Analysis Standard"
xil_pn:value=
"VHDL-93"
xil_pn:valueState=
"default"
/>
...
@@ -339,888 +341,905 @@
...
@@ -339,888 +341,905 @@
<libraries/>
<libraries/>
<files>
<files>
<file
xil_pn:name=
"../../
ip_cores/wr-switch-hdl/modules/wrsw_swcore/ram_bug/buggy_ram.ngc"
xil_pn:type=
"FILE_NGC
"
>
<file
xil_pn:name=
"../../
top/spec/wr_nic_sdb_top.ucf"
xil_pn:type=
"FILE_UCF
"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1"
/>
</file>
</file>
<file
xil_pn:name=
"../../
ip_cores/wr-switch-hdl/platform/virtex6
/chipscope/chipscope_icon.ngc"
xil_pn:type=
"FILE_NGC"
>
<file
xil_pn:name=
"../../
platform/xilinx
/chipscope/chipscope_icon.ngc"
xil_pn:type=
"FILE_NGC"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2"
/>
</file>
</file>
<file
xil_pn:name=
"../../
ip_cores/wr-switch-hdl/platform/virtex6
/chipscope/chipscope_ila.ngc"
xil_pn:type=
"FILE_NGC"
>
<file
xil_pn:name=
"../../
platform/xilinx
/chipscope/chipscope_ila.ngc"
xil_pn:type=
"FILE_NGC"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3"
/>
</file>
</file>
<file
xil_pn:name=
"../../
platform/xilinx/chipscope/chipscope_icon
.ngc"
xil_pn:type=
"FILE_NGC"
>
<file
xil_pn:name=
"../../
ip_cores/wr-switch-hdl/modules/wrsw_swcore/ram_bug/buggy_ram
.ngc"
xil_pn:type=
"FILE_NGC"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4"
/>
</file>
</file>
<file
xil_pn:name=
"../../
platform/xilinx/chipscope/chipscope_ila
.ngc"
xil_pn:type=
"FILE_NGC"
>
<file
xil_pn:name=
"../../
ip_cores/wr-switch-hdl/platform/virtex6/chipscope/chipscope_icon
.ngc"
xil_pn:type=
"FILE_NGC"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/
general-cores/modules/genrams/genram_pkg.vhd"
xil_pn:type=
"FILE_VHDL
"
>
<file
xil_pn:name=
"../../ip_cores/
wr-switch-hdl/platform/virtex6/chipscope/chipscope_ila.ngc"
xil_pn:type=
"FILE_NGC
"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6"
/>
</file>
</file>
<file
xil_pn:name=
"../../
top/spec/spec_serial_dac
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/genrams/genram_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7"
/>
</file>
</file>
<file
xil_pn:name=
"../../
top/spec/spec_serial_dac_arb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wishbone_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8"
/>
</file>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wishbone_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
top/spec/spec_serial_dac
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9"
/>
</file>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
top/spec/spec_serial_dac_arb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10"
/>
</file>
</file>
<file
xil_pn:name=
"../../
ip_cores/wr-cores/modules/fabric/wr_fabric
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wrsw_dio/wrnic_sdb
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11"
/>
</file>
</file>
<file
xil_pn:name=
"../../
modules/wrsw_dio/wrnic_sdb
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/
wr_endpoint/endpoint
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/
fabric/wr_fabric
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"13"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"13"
/>
</file>
</file>
<file
xil_pn:name=
"../../
modules/wrsw_dio/pulse_gen_pl
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"14"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"14"
/>
</file>
</file>
<file
xil_pn:name=
"../../
modules/wrsw_dio/immed_pulse_counter
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"15"
/>
<association
xil_pn:name=
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xil_pn:seqID=
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/>
</file>
</file>
<file
xil_pn:name=
"../../modules/wrsw_dio/
dummy_time
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/wrsw_dio/
pulse_gen_pl
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
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/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"16"
/>
</file>
</file>
<file
xil_pn:name=
"../../
ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wrsw_dio/immed_pulse_counter
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
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/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"17"
/>
</file>
</file>
<file
xil_pn:name=
"../../
ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slav
e.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/wrsw_dio/dummy_tim
e.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
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/>
<association
xil_pn:name=
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xil_pn:seqID=
"18"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/gn4124-core/hdl/gn4124core/rtl/
l2p_arbiter
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/gn4124-core/hdl/gn4124core/rtl/
spartan6/gn4124_core_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/
wr-cores/modules/wrc_core/wrc_syscon_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/
gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"20"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"20"
/>
</file>
</file>
<file
xil_pn:name=
"../../ip_cores/gn4124-core/hdl/gn4124core/rtl/
p2l_decode32
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/gn4124-core/hdl/gn4124core/rtl/
l2p_arbiter
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"21"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"21"
/>
</file>
</file>
<file
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...
...
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