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White Rabbit Network Interface Card
Commit b053fb72 authored by Alessandro Rubini's avatar Alessandro Rubini Committed by Miguel Jimenez Lopez
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kernel: copied new endpoint header and wb file

parent ca1c8911
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Showing with 449 additions and 139 deletions
kernel/wbgen-regs/endpoint-regs.h
View file @ b053fb72
......@@ -41,11 +41,23 @@
/* definitions for field: Reset event counters in reg: Endpoint Control Register */
#define EP_ECR_RST_CNT WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Transmit framer enable in reg: Endpoint Control Register */
#define EP_ECR_TX_EN_FRA WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Transmit path enable in reg: Endpoint Control Register */
#define EP_ECR_TX_EN WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Receive deframer enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN_FRA WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Receive path enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Feature present: VLAN tagging in reg: Endpoint Control Register */
#define EP_ECR_FEAT_VLAN WBGEN2_GEN_MASK(24, 1)
/* definitions for field: Feature present: DDMTD phase measurement in reg: Endpoint Control Register */
#define EP_ECR_FEAT_DMTD WBGEN2_GEN_MASK(25, 1)
/* definitions for field: Feature present: IEEE1588 timestamper in reg: Endpoint Control Register */
#define EP_ECR_FEAT_PTP WBGEN2_GEN_MASK(26, 1)
/* definitions for field: Feature present: DPI packet classifier in reg: Endpoint Control Register */
#define EP_ECR_FEAT_DPI WBGEN2_GEN_MASK(27, 1)
/* definitions for register: Timestamping Control Register */
......@@ -72,29 +84,96 @@
/* definitions for field: RX accept HP in reg: RX Deframer Control Register */
#define EP_RFCR_A_HP WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX accept fragments in reg: RX Deframer Control Register */
#define EP_RFCR_A_FRAG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: RX 802.1q port mode in reg: RX Deframer Control Register */
#define EP_RFCR_QMODE_MASK WBGEN2_GEN_MASK(4, 2)
#define EP_RFCR_QMODE_SHIFT 4
#define EP_RFCR_QMODE_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define EP_RFCR_QMODE_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Force 802.1q priority in reg: RX Deframer Control Register */
#define EP_RFCR_FIX_PRIO WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Port-assigned 802.1x priority in reg: RX Deframer Control Register */
#define EP_RFCR_PRIO_VAL_MASK WBGEN2_GEN_MASK(8, 3)
#define EP_RFCR_PRIO_VAL_SHIFT 8
#define EP_RFCR_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define EP_RFCR_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: Port-assigned VID in reg: RX Deframer Control Register */
#define EP_RFCR_VID_VAL_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_RFCR_VID_VAL_SHIFT 16
#define EP_RFCR_VID_VAL_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_RFCR_VID_VAL_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for field: RX keep CRC in reg: RX Deframer Control Register */
#define EP_RFCR_KEEP_CRC WBGEN2_GEN_MASK(3, 1)
/* definitions for field: RX Fiter HP Priorities in reg: RX Deframer Control Register */
#define EP_RFCR_HPAP_MASK WBGEN2_GEN_MASK(4, 8)
#define EP_RFCR_HPAP_SHIFT 4
#define EP_RFCR_HPAP_W(value) WBGEN2_GEN_WRITE(value, 4, 8)
#define EP_RFCR_HPAP_R(reg) WBGEN2_GEN_READ(reg, 4, 8)
/* definitions for field: Maximum receive unit (MRU) in reg: RX Deframer Control Register */
#define EP_RFCR_MRU_MASK WBGEN2_GEN_MASK(12, 14)
#define EP_RFCR_MRU_SHIFT 12
#define EP_RFCR_MRU_W(value) WBGEN2_GEN_WRITE(value, 12, 14)
#define EP_RFCR_MRU_R(reg) WBGEN2_GEN_READ(reg, 12, 14)
/* definitions for register: VLAN control register 0 */
/* definitions for field: RX 802.1q port mode in reg: VLAN control register 0 */
#define EP_VCR0_QMODE_MASK WBGEN2_GEN_MASK(0, 2)
#define EP_VCR0_QMODE_SHIFT 0
#define EP_VCR0_QMODE_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define EP_VCR0_QMODE_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Force 802.1q priority in reg: VLAN control register 0 */
#define EP_VCR0_FIX_PRIO WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Port-assigned 802.1q priority in reg: VLAN control register 0 */
#define EP_VCR0_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define EP_VCR0_PRIO_VAL_SHIFT 4
#define EP_VCR0_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define EP_VCR0_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Port-assigned VID in reg: VLAN control register 0 */
#define EP_VCR0_PVID_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_VCR0_PVID_SHIFT 16
#define EP_VCR0_PVID_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_VCR0_PVID_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: VLAN Control Register 1 */
/* definitions for field: Egress untagged set bitmap VID in reg: VLAN Control Register 1 */
#define EP_VCR1_VID_MASK WBGEN2_GEN_MASK(0, 12)
#define EP_VCR1_VID_SHIFT 0
#define EP_VCR1_VID_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define EP_VCR1_VID_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Egress untagged set bitmap value in reg: VLAN Control Register 1 */
#define EP_VCR1_VALUE_MASK WBGEN2_GEN_MASK(12, 1)
#define EP_VCR1_VALUE_SHIFT 12
#define EP_VCR1_VALUE_W(value) WBGEN2_GEN_WRITE(value, 12, 1)
#define EP_VCR1_VALUE_R(reg) WBGEN2_GEN_READ(reg, 12, 1)
/* definitions for register: Packet Filter Control Register 0 */
/* definitions for field: Microcode Memory Address in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_MM_ADDR_MASK WBGEN2_GEN_MASK(0, 6)
#define EP_PFCR0_MM_ADDR_SHIFT 0
#define EP_PFCR0_MM_ADDR_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define EP_PFCR0_MM_ADDR_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for field: Microcode Memory Write Enable in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_MM_WRITE_MASK WBGEN2_GEN_MASK(6, 1)
#define EP_PFCR0_MM_WRITE_SHIFT 6
#define EP_PFCR0_MM_WRITE_W(value) WBGEN2_GEN_WRITE(value, 6, 1)
#define EP_PFCR0_MM_WRITE_R(reg) WBGEN2_GEN_READ(reg, 6, 1)
/* definitions for field: Packet Filter Enable in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_ENABLE WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Microcode Memory Data (24 MSBs) in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_MM_DATA_MSB_MASK WBGEN2_GEN_MASK(8, 24)
#define EP_PFCR0_MM_DATA_MSB_SHIFT 8
#define EP_PFCR0_MM_DATA_MSB_W(value) WBGEN2_GEN_WRITE(value, 8, 24)
#define EP_PFCR0_MM_DATA_MSB_R(reg) WBGEN2_GEN_READ(reg, 8, 24)
/* definitions for register: Packet Filter Control Register 1 */
/* definitions for field: Microcode Memory Data (12 LSBs) in reg: Packet Filter Control Register 1 */
#define EP_PFCR1_MM_DATA_LSB_MASK WBGEN2_GEN_MASK(0, 12)
#define EP_PFCR1_MM_DATA_LSB_SHIFT 0
#define EP_PFCR1_MM_DATA_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define EP_PFCR1_MM_DATA_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for register: Traffic Class Assignment Register */
/* definitions for field: 802.1Q priority tag to Traffic Class map in reg: Traffic Class Assignment Register */
#define EP_TCAR_PCP_MAP_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_TCAR_PCP_MAP_SHIFT 0
#define EP_TCAR_PCP_MAP_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_TCAR_PCP_MAP_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for register: Flow Control Register */
......@@ -120,28 +199,6 @@
/* definitions for register: Endpoint MAC address low part register */
/* definitions for register: DMTD Control Register */
/* definitions for field: DMTD Phase measurement enable in reg: DMTD Control Register */
#define EP_DMCR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMTD averaging samples in reg: DMTD Control Register */
#define EP_DMCR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_DMCR_N_AVG_SHIFT 16
#define EP_DMCR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_DMCR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: DMTD Status register */
/* definitions for field: DMTD Phase shift value in reg: DMTD Status register */
#define EP_DMSR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_DMSR_PS_VAL_SHIFT 0
#define EP_DMSR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_DMSR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for register: MDIO Control Register */
/* definitions for field: MDIO Register Value in reg: MDIO Control Register */
......@@ -159,16 +216,22 @@
/* definitions for field: MDIO Read/Write select in reg: MDIO Control Register */
#define EP_MDIO_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: MDIO Status Register */
/* definitions for register: MDIO Address/Status Register */
/* definitions for field: MDIO Read Value in reg: MDIO Address/Status Register */
#define EP_MDIO_ASR_RDATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_ASR_RDATA_SHIFT 0
#define EP_MDIO_ASR_RDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_ASR_RDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Read Value in reg: MDIO Status Register */
#define EP_MDIO_SR_RDATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_SR_RDATA_SHIFT 0
#define EP_MDIO_SR_RDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_SR_RDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO PHY Address in reg: MDIO Address/Status Register */
#define EP_MDIO_ASR_PHYAD_MASK WBGEN2_GEN_MASK(16, 8)
#define EP_MDIO_ASR_PHYAD_SHIFT 16
#define EP_MDIO_ASR_PHYAD_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define EP_MDIO_ASR_PHYAD_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for field: MDIO Ready in reg: MDIO Status Register */
#define EP_MDIO_SR_READY WBGEN2_GEN_MASK(31, 1)
/* definitions for field: MDIO Ready in reg: MDIO Address/Status Register */
#define EP_MDIO_ASR_READY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Identification register */
......@@ -179,6 +242,28 @@
/* definitions for field: Link activity in reg: Debug/Status register */
#define EP_DSR_LACT WBGEN2_GEN_MASK(1, 1)
/* definitions for register: DMTD Control Register */
/* definitions for field: DMTD Phase measurement enable in reg: DMTD Control Register */
#define EP_DMCR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMTD averaging samples in reg: DMTD Control Register */
#define EP_DMCR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_DMCR_N_AVG_SHIFT 16
#define EP_DMCR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_DMCR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: DMTD Status register */
/* definitions for field: DMTD Phase shift value in reg: DMTD Status register */
#define EP_DMSR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_DMSR_PS_VAL_SHIFT 0
#define EP_DMSR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_DMSR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
......@@ -190,26 +275,36 @@ PACKED struct EP_WB {
uint32_t TSCR;
/* [0x8]: REG RX Deframer Control Register */
uint32_t RFCR;
/* [0xc]: REG Flow Control Register */
/* [0xc]: REG VLAN control register 0 */
uint32_t VCR0;
/* [0x10]: REG VLAN Control Register 1 */
uint32_t VCR1;
/* [0x14]: REG Packet Filter Control Register 0 */
uint32_t PFCR0;
/* [0x18]: REG Packet Filter Control Register 1 */
uint32_t PFCR1;
/* [0x1c]: REG Traffic Class Assignment Register */
uint32_t TCAR;
/* [0x20]: REG Flow Control Register */
uint32_t FCR;
/* [0x10]: REG Endpoint MAC address high part register */
/* [0x24]: REG Endpoint MAC address high part register */
uint32_t MACH;
/* [0x14]: REG Endpoint MAC address low part register */
/* [0x28]: REG Endpoint MAC address low part register */
uint32_t MACL;
/* [0x18]: REG DMTD Control Register */
uint32_t DMCR;
/* [0x1c]: REG DMTD Status register */
uint32_t DMSR;
/* [0x20]: REG MDIO Control Register */
/* [0x2c]: REG MDIO Control Register */
uint32_t MDIO_CR;
/* [0x24]: REG MDIO Status Register */
uint32_t MDIO_SR;
/* [0x28]: REG Identification register */
/* [0x30]: REG MDIO Address/Status Register */
uint32_t MDIO_ASR;
/* [0x34]: REG Identification register */
uint32_t IDCODE;
/* [0x2c]: REG Debug/Status register */
/* [0x38]: REG Debug/Status register */
uint32_t DSR;
/* [0x3c]: REG DMTD Control Register */
uint32_t DMCR;
/* [0x40]: REG DMTD Status register */
uint32_t DMSR;
/* padding to: 32 words */
uint32_t __padding_0[20];
uint32_t __padding_0[15];
/* [0x80 - 0xff]: RAM Event counters memory, 32 32-bit words, 32-bit aligned, word-addressable */
uint32_t RMON_RAM [32];
};
......
kernel/wbgen-regs/endpoint-regs.wb
View file @ b053fb72
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
-- Title : Wishbone Register Block (slave)
-- Project : White Rabbit MAC/Endpoint
-------------------------------------------------------------------------------
-- File : ep_wishbone_controller.wb
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-10-18
-------------------------------------------------------------------------------
-- Description: Description of all non-PCS endpoint control registers
-- for wbgen2 Wishbone slave core generator.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1l.html
--
-------------------------------------------------------------------------------
peripheral {
name = "WR switch endpoint controller";
description = "EP controller";
hdl_entity = "ep_wishbone_controller";
prefix = "EP";
prefix = "ep";
-- ECR
reg {
......@@ -31,10 +65,10 @@ peripheral {
};
field {
name = "Transmit framer enable";
description = "1: TX framer is enabled\
0: TX framer is disabled";
prefix = "TX_EN_FRA";
name = "Transmit path enable";
description = "1: TX path is enabled\
0: TX path is disabled";
prefix = "TX_EN";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
......@@ -42,15 +76,60 @@ peripheral {
field {
name = "Receive deframer enable";
prefix = "RX_en_fra";
description = "1: RX deframer is enabled\
0: RX deframer is disabled";
name = "Receive path enable";
prefix = "RX_en";
description = "1: RX path is enabled\
0: RX path is disabled";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Feature present: VLAN tagging";
description = "1: this implementation of WR Endpoint supports VLAN processing \
(tagging/untagging). VCR register can be used to control the \
VLAN functionality \
0: no VLAN support compiled";
prefix = "FEAT_VLAN";
align = 24;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: DDMTD phase measurement";
description = "1: this implementation of WR Endpoint can do fine phase measurements \
using a DDMTD phase detector\
0: no phase measurement support compiled";
prefix = "FEAT_DMTD";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: IEEE1588 timestamper";
description = "1: this implementation of WR Endpoint can timestamp packets\
0: no timestamping compiled";
prefix = "FEAT_PTP";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: DPI packet classifier";
description = "1: this implementation of WR Endpoint includes Deep Packet Inspection packet classifier/filter\
0: no DPI compiled";
prefix = "FEAT_DPI";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -72,7 +151,7 @@ peripheral {
field {
name = "Receive timestamping enable";
description = "1: enables RX timestamping. RX timestamps are embedded into OOB field on the fabric interface\
description = "1: enables RX timestamping. RX timestamps are embedded into OOB field on the fabric interface. Must be enabled if used in a multi-port configuration (e.g. in a switch)\
0: disables RX timestamping";
prefix = "EN_RXTS";
access_bus = READ_WRITE;
......@@ -84,7 +163,7 @@ peripheral {
name = "Timestamping counter synchronization start";
prefix = "CS_START";
description = "write 1: starts synchronizing the local PPS counter used for timestamping TX/RX packets with an external pulse provided on pps_i input.\
After synchronization, SYNC_DONE flag will be set to 1. The counter value equals to 0 when PPS line is high.\
After synchronization, the CS_DONE flag will be set to 1. The counter value equals to 0 when PPS line is high.\
write 0: no effect";
type = MONOSTABLE;
clock = "tx_clk_i";
......@@ -137,15 +216,40 @@ peripheral {
};
field {
name = "RX accept fragments";
description = "1: endpoint accepts WhiteRabbit fragmented frames\
0: fragmented frames are dropped";
prefix = "a_frag";
name = "RX keep CRC";
description = "1: endpoint keeps FCS fields on the fabric side\
0: FCS fields are stripped";
prefix = "KEEP_CRC";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "RX Fiter HP Priorities";
prefix = "HPAP";
description = "Map of 802.1q PCP values which qualify the incoming frame as HP. Each bit corresponds to one PCP value (bit 7: PCP == 7, bit 0: PCP == 0).";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Maximum receive unit (MRU)";
description = "Maximum size of a frame which is considered valid (in bytes)";
prefix = "MRU";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 14;
};
};
reg {
name = "VLAN control register 0";
prefix = "VCR0";
field {
name = "RX 802.1q port mode";
description = "00: ACCESS port - tags untagged received packets with VID from RX_VID field. Drops all tagged packets not belonging to RX_VID VLAN\
......@@ -173,7 +277,7 @@ peripheral {
};
field {
name = "Port-assigned 802.1x priority";
name = "Port-assigned 802.1q priority";
description = "Packet priority value for retagging. When FIX_PRIO is 1, the endpoint uses this value as the packet priority. Otherwise, priority value is taken from 802.1q header if it's present. If there is no 802.1q header, the priority is assumed to be PRIO_VAL.";
prefix = "PRIO_VAL";
type = SLV;
......@@ -186,7 +290,7 @@ peripheral {
field {
name = "Port-assigned VID";
description = "VLAN id value for tagging incoming packets if the port is in ACCESS mode. For TRUNK/unqualified the value of VID is ignored.";
prefix = "vid_VAL";
prefix = "PVID";
type = SLV;
align = 16;
size = 12;
......@@ -195,6 +299,107 @@ peripheral {
};
};
reg {
name = "VLAN Control Register 1";
description = "Controls the access to the egress VLAN untagged set.\
Each write can enable (VALUE=1) / disable (VALUE=0) untagging frames\
with given VID";
prefix = "VCR1";
field {
name = "Egress untagged set bitmap VID";
description = "write: the VID to be tagged/untagged\
read: undefined";
prefix = "VID";
type = PASS_THROUGH;
size = 12;
};
field {
name = "Egress untagged set bitmap value";
description = "write 1: frames with matching VID are untagged\
write 0: frames with matching VID are not modified\
read: undefined";
prefix = "VALUE";
type = PASS_THROUGH;
size = 1;
};
};
reg {
name = "Packet Filter Control Register 0";
description = "Controls the microcode memory access of the Packet Filter Unit. \
See the Endpoint documentation for more details";
prefix = "PFCR0";
field {
name = "Microcode Memory Address";
prefix = "MM_ADDR";
size = 6;
type = PASS_THROUGH;
};
field {
size = 1;
name = "Microcode Memory Write Enable";
prefix = "MM_WRITE";
type = PASS_THROUGH;
};
field {
type = BIT;
name = "Packet Filter Enable";
prefix = "ENABLE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
size = 24;
name = "Microcode Memory Data (24 MSBs)";
prefix = "MM_DATA_MSB";
type = PASS_THROUGH;
};
};
reg {
name = "Packet Filter Control Register 1";
description = "Controls the microcode memory access of the Packet Filter Unit. \
See the Endpoint documentation for more details";
prefix= "PFCR1";
field{
size = 12;
name = "Microcode Memory Data (12 LSBs)";
prefix = "MM_DATA_LSB";
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Traffic Class Assignment Register";
description = "Controls the mapping of VLAN priority fields into Swcore's traffic classes.. See Endpoint's documentation for more details.";
prefix = "TCAR";
field {
name = "802.1Q priority tag to Traffic Class map";
prefix = "PCP_MAP";
description = "Controls the mapping of PCP into Traffic Classes. The mapping algorithm is: TC = PCP_MAP[PCP * 3 + 2 : PCP * 3]; ";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Flow Control Register";
description = "";
......@@ -274,55 +479,6 @@ peripheral {
};
};
reg {
name = "DMTD Control Register";
prefix = "DMCR";
field {
name = "DMTD Phase measurement enable";
description = "1: enables DMTD phase measurement";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
description = "Number of raw DMTD phase samples averaged in every measurement cycle";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "DMTD Status register";
prefix = "DMSR";
field {
name = "DMTD Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "DMTD Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
reg {
name = "MDIO Control Register";
description = "Register controlling the read/write operations on the MDIO PHY/PCS interface. Writing to this register clears the READY bit in the MDIO Status Register";
......@@ -356,9 +512,9 @@ peripheral {
};
reg {
name = "MDIO Status Register";
name = "MDIO Address/Status Register";
description = "Register with the current status of the MDIO interface";
prefix = "MDIO_SR";
prefix = "MDIO_ASR";
field {
......@@ -370,6 +526,16 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "MDIO PHY Address";
description = "Address of the PHY on the MDIO bus";
prefix = "PHYAD";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "MDIO Ready";
......@@ -419,6 +585,55 @@ peripheral {
};
};
reg {
name = "DMTD Control Register";
prefix = "DMCR";
field {
name = "DMTD Phase measurement enable";
description = "1: enables DMTD phase measurement";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
description = "Number of raw DMTD phase samples averaged in every measurement cycle";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "DMTD Status register";
prefix = "DMSR";
field {
name = "DMTD Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "DMTD Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
ram {
name = "Event counters memory";
description = "RMON event counters:\
......
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