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White Rabbit Network Interface Card
Commit ca1c8911 authored by Alessandro Rubini's avatar Alessandro Rubini Committed by Miguel Jimenez Lopez
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kernel: move drivers to new dir; fixed Mkafiles for rtu

parent 64968740
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kernel/wbgen-regs/Makefile 0 → 100644
View file @ ca1c8911
# This Makefile is used to reproduce the headers from svn checkout.
# You need to have "wbgen2" in your command search path and the white-rabbit
# svn checkout in $SVN. Since this is only meant to be used by me,
# no serious checking is done
# List of input files in SVN checkout
MODULES = $(SVN)/trunk/hdl/modules
SPECS = $(SVN)/trunk/documentation/specifications
WB_ENDPOINT = $(MODULES)/wrsw_endpoint/ep_wishbone_controller.wb
WB_PPSG = $(MODULES)/wrsw_pps_gen/wrsw_pps_gen.wb
WB_CALIB = $(MODULES)/wrsw_calibrator_dmtd/wrsw_calibrator_dmtd.wb
WB_TSTAMP = $(MODULES)/wrsw_txtsu/wrsw_txtsu.wb
WB_RTU = $(MODULES)/wrsw_rtu/wrsw_rtu_wb.wb
WB_NIC = $(SPECS)/hdlspec/WRSW_wbc_internal_NIC/wr_nic.wb
HEADERS = endpoint-regs.h ppsg-regs.h calib-regs.h tstamp-regs.h rtu-regs.h \
nic-regs.h
WBINPUT = $(HEADERS:.h=wb)
# No default, for people who types "make" everywhere (like me)
all:
@echo "This is for developer's use, see Makefile for details"
exit 1
# The headers rule regenerates headers from local wb files
headers: $(HEADERS)
%.h: %.wb
wbgen2 --cstyle=struct --co=$@ $<
sed -i 's,inttypes.h,linux/types.h,' $@
sed -i '/ Created *: .*20[0-9][0-9]$$/ d' $@
sed -i 's/-REGS_WB//' $@
# The wbinput rule just copies here stuff from svn.
# Do it silent so errors stand out
wbinput:
@cp $(WB_ENDPOINT) endpoint-regs.wb
@cp $(WB_PPSG) ppsg-regs.wb
@cp $(WB_CALIB) calib-regs.wb
@cp $(WB_TSTAMP) tstamp-regs.wb
@cp $(WB_RTU) rtu-regs.wb
@cp $(WB_NIC) nic-regs.wb
@echo "Copied input files from subversions to local directory"
kernel/wbgen-regs/README 0 → 100644
View file @ ca1c8911
The headers have been derived from what is in svn:
documentation/specifications/hdlspec/memory_map/
In that directory you find the html generated from the wb files.
Here I import the relevant headers. The overall register
map is in ../nic/nic-hardware.h .
The .wb files whence the headers are generated come from different
plases in the white rabbit svn. To ease myself I wrote this in
the Makefile. You can "make wbinput" to get a fresh copy of them,
provided you have SVN set in your environment (point to the root
checkout, before "trunk" subdirectory). If unset or wrong, cp fails.
With "make headers" you can regenerate the headers from the wb input
files. Each generated file is postprocesses with sed to fix these
issues:
* generated files include <inttypes.h> as they use uint32_t. We want
<linux/types.h> instead, as no <inttypes.h> nor <stdint.h> is there
* generated files include the date of creation. This brings to noise
in the "git diff" or plain "diff", so I'd better have no date.
* creation of "#ifdef __THIS_HEADER__" fails on the dash, so I remove
the dash and trailing part with sed (as of writing, it has issues with
pathnames too, this is one the reasons why I copy the wb here first).
kernel/wbgen-regs/calib-regs.h 0 → 100644
View file @ ca1c8911
/*
Register definitions for slave core: DMTD PHY Calibrator
* File : calib-regs.h
* Author : auto-generated by wbgen2 from calib-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE calib-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CALIB
#define __WBGEN2_REGDEFS_CALIB
#include <linux/types.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Enable in reg: Control Register */
#define DPC_CR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Compare clock select in reg: Control Register */
#define DPC_CR_IN_SEL_MASK WBGEN2_GEN_MASK(8, 4)
#define DPC_CR_IN_SEL_SHIFT 8
#define DPC_CR_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 4)
#define DPC_CR_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 4)
/* definitions for field: DMTD averaging samples in reg: Control Register */
#define DPC_CR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define DPC_CR_N_AVG_SHIFT 16
#define DPC_CR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define DPC_CR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: Status register */
/* definitions for field: Phase shift value in reg: Status register */
#define DPC_SR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define DPC_SR_PS_VAL_SHIFT 0
#define DPC_SR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DPC_SR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Phase shift value ready in reg: Status register */
#define DPC_SR_PS_RDY WBGEN2_GEN_MASK(24, 1)
PACKED struct DPC_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
/* [0x4]: REG Status register */
uint32_t SR;
};
#endif
kernel/wbgen-regs/calib-regs.wb 0 → 100644
View file @ ca1c8911
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "DMTD PHY Calibrator";
prefix = "dpc";
hdl_entity = "dmtd_calibrator_wb";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Enable";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Compare clock select";
prefix = "IN_SEL";
type = SLV;
size = 4;
align = 8;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Status register";
prefix = "SR";
field {
name = "Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
};
kernel/wbgen-regs/endpoint-regs.h 0 → 100644
View file @ ca1c8911
/*
Register definitions for slave core: WR switch endpoint controller
* File : endpoint-regs.h
* Author : auto-generated by wbgen2 from endpoint-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE endpoint-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_ENDPOINT
#define __WBGEN2_REGDEFS_ENDPOINT
#include <linux/types.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Endpoint Control Register */
/* definitions for field: Port identifier in reg: Endpoint Control Register */
#define EP_ECR_PORTID_MASK WBGEN2_GEN_MASK(0, 5)
#define EP_ECR_PORTID_SHIFT 0
#define EP_ECR_PORTID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define EP_ECR_PORTID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Reset event counters in reg: Endpoint Control Register */
#define EP_ECR_RST_CNT WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Transmit framer enable in reg: Endpoint Control Register */
#define EP_ECR_TX_EN_FRA WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Receive deframer enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN_FRA WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Timestamping Control Register */
/* definitions for field: Transmit timestamping enable in reg: Timestamping Control Register */
#define EP_TSCR_EN_TXTS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Receive timestamping enable in reg: Timestamping Control Register */
#define EP_TSCR_EN_RXTS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamping counter synchronization start in reg: Timestamping Control Register */
#define EP_TSCR_CS_START WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Timestamping counter synchronization done in reg: Timestamping Control Register */
#define EP_TSCR_CS_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for register: RX Deframer Control Register */
/* definitions for field: RX accept runts in reg: RX Deframer Control Register */
#define EP_RFCR_A_RUNT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX accept giants in reg: RX Deframer Control Register */
#define EP_RFCR_A_GIANT WBGEN2_GEN_MASK(1, 1)
/* definitions for field: RX accept HP in reg: RX Deframer Control Register */
#define EP_RFCR_A_HP WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX accept fragments in reg: RX Deframer Control Register */
#define EP_RFCR_A_FRAG WBGEN2_GEN_MASK(3, 1)
/* definitions for field: RX 802.1q port mode in reg: RX Deframer Control Register */
#define EP_RFCR_QMODE_MASK WBGEN2_GEN_MASK(4, 2)
#define EP_RFCR_QMODE_SHIFT 4
#define EP_RFCR_QMODE_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define EP_RFCR_QMODE_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Force 802.1q priority in reg: RX Deframer Control Register */
#define EP_RFCR_FIX_PRIO WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Port-assigned 802.1x priority in reg: RX Deframer Control Register */
#define EP_RFCR_PRIO_VAL_MASK WBGEN2_GEN_MASK(8, 3)
#define EP_RFCR_PRIO_VAL_SHIFT 8
#define EP_RFCR_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define EP_RFCR_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: Port-assigned VID in reg: RX Deframer Control Register */
#define EP_RFCR_VID_VAL_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_RFCR_VID_VAL_SHIFT 16
#define EP_RFCR_VID_VAL_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_RFCR_VID_VAL_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: Flow Control Register */
/* definitions for field: RX Pause enable in reg: Flow Control Register */
#define EP_FCR_RXPAUSE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX Pause enable in reg: Flow Control Register */
#define EP_FCR_TXPAUSE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX pause threshold in reg: Flow Control Register */
#define EP_FCR_TX_THR_MASK WBGEN2_GEN_MASK(8, 8)
#define EP_FCR_TX_THR_SHIFT 8
#define EP_FCR_TX_THR_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define EP_FCR_TX_THR_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: TX pause quanta in reg: Flow Control Register */
#define EP_FCR_TX_QUANTA_MASK WBGEN2_GEN_MASK(16, 16)
#define EP_FCR_TX_QUANTA_SHIFT 16
#define EP_FCR_TX_QUANTA_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define EP_FCR_TX_QUANTA_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Endpoint MAC address high part register */
/* definitions for register: Endpoint MAC address low part register */
/* definitions for register: DMTD Control Register */
/* definitions for field: DMTD Phase measurement enable in reg: DMTD Control Register */
#define EP_DMCR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMTD averaging samples in reg: DMTD Control Register */
#define EP_DMCR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_DMCR_N_AVG_SHIFT 16
#define EP_DMCR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_DMCR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: DMTD Status register */
/* definitions for field: DMTD Phase shift value in reg: DMTD Status register */
#define EP_DMSR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_DMSR_PS_VAL_SHIFT 0
#define EP_DMSR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_DMSR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for register: MDIO Control Register */
/* definitions for field: MDIO Register Value in reg: MDIO Control Register */
#define EP_MDIO_CR_DATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_CR_DATA_SHIFT 0
#define EP_MDIO_CR_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_CR_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Register Address in reg: MDIO Control Register */
#define EP_MDIO_CR_ADDR_MASK WBGEN2_GEN_MASK(16, 8)
#define EP_MDIO_CR_ADDR_SHIFT 16
#define EP_MDIO_CR_ADDR_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define EP_MDIO_CR_ADDR_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for field: MDIO Read/Write select in reg: MDIO Control Register */
#define EP_MDIO_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: MDIO Status Register */
/* definitions for field: MDIO Read Value in reg: MDIO Status Register */
#define EP_MDIO_SR_RDATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_SR_RDATA_SHIFT 0
#define EP_MDIO_SR_RDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_SR_RDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Ready in reg: MDIO Status Register */
#define EP_MDIO_SR_READY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Identification register */
/* definitions for register: Debug/Status register */
/* definitions for field: Link status in reg: Debug/Status register */
#define EP_DSR_LSTATUS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Link activity in reg: Debug/Status register */
#define EP_DSR_LACT WBGEN2_GEN_MASK(1, 1)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
PACKED struct EP_WB {
/* [0x0]: REG Endpoint Control Register */
uint32_t ECR;
/* [0x4]: REG Timestamping Control Register */
uint32_t TSCR;
/* [0x8]: REG RX Deframer Control Register */
uint32_t RFCR;
/* [0xc]: REG Flow Control Register */
uint32_t FCR;
/* [0x10]: REG Endpoint MAC address high part register */
uint32_t MACH;
/* [0x14]: REG Endpoint MAC address low part register */
uint32_t MACL;
/* [0x18]: REG DMTD Control Register */
uint32_t DMCR;
/* [0x1c]: REG DMTD Status register */
uint32_t DMSR;
/* [0x20]: REG MDIO Control Register */
uint32_t MDIO_CR;
/* [0x24]: REG MDIO Status Register */
uint32_t MDIO_SR;
/* [0x28]: REG Identification register */
uint32_t IDCODE;
/* [0x2c]: REG Debug/Status register */
uint32_t DSR;
/* padding to: 32 words */
uint32_t __padding_0[20];
/* [0x80 - 0xff]: RAM Event counters memory, 32 32-bit words, 32-bit aligned, word-addressable */
uint32_t RMON_RAM [32];
};
#endif
kernel/wbgen-regs/endpoint-regs.wb 0 → 100644
View file @ ca1c8911
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR switch endpoint controller";
description = "EP controller";
hdl_entity = "ep_wishbone_controller";
prefix = "EP";
-- ECR
reg {
name = "Endpoint Control Register";
prefix = "ECR";
description = "General endpoint control register";
field {
name = "Port identifier";
description = "Unique port identifier which will be embedded into OOB with the timestamp value";
prefix = "PORTID";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 5;
};
field {
name = "Reset event counters";
description = "write 1: resets all event counters\n0: no effect";
prefix = "rst_cnt";
type = MONOSTABLE;
};
field {
name = "Transmit framer enable";
description = "1: TX framer is enabled\
0: TX framer is disabled";
prefix = "TX_EN_FRA";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Receive deframer enable";
prefix = "RX_en_fra";
description = "1: RX deframer is enabled\
0: RX deframer is disabled";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
};
reg {
name = "Timestamping Control Register";
description = "Register controlling timestamping features of the endpoint";
prefix = "TSCR";
field {
name = "Transmit timestamping enable";
description = "1: enables TX timestamping. Endpoints passes timestamps to shared TX timestamping unit\
0: disables TX timestamping";
prefix = "EN_TXTS";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Receive timestamping enable";
description = "1: enables RX timestamping. RX timestamps are embedded into OOB field on the fabric interface\
0: disables RX timestamping";
prefix = "EN_RXTS";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Timestamping counter synchronization start";
prefix = "CS_START";
description = "write 1: starts synchronizing the local PPS counter used for timestamping TX/RX packets with an external pulse provided on pps_i input.\
After synchronization, SYNC_DONE flag will be set to 1. The counter value equals to 0 when PPS line is high.\
write 0: no effect";
type = MONOSTABLE;
clock = "tx_clk_i";
};
field {
name = "Timestamping counter synchronization done";
prefix = "CS_DONE";
description = "1: the counter synchronization procedure is done. \
0: the counter synchronization procedure is pending";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "tx_clk_i";
};
};
reg {
name = "RX Deframer Control Register";
prefix = "RFCR";
field {
name = "RX accept runts";
description = "1: endpoint accepts 'runt' frames (shorter than 64 bytes)\
0: 'runt' frames are dropped";
prefix = "A_RUNT";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "RX accept giants";
description = "1: endpoint accepts 'giant' frames (longer than 1516/1522 bytes)\
0: 'giant' frames are dropped";
prefix = "A_GIANT";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "RX accept HP";
description = "1: endpoint accepts HP frames\
0: HP frames are dropped";
prefix = "A_HP";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "RX accept fragments";
description = "1: endpoint accepts WhiteRabbit fragmented frames\
0: fragmented frames are dropped";
prefix = "a_frag";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "RX 802.1q port mode";
description = "00: ACCESS port - tags untagged received packets with VID from RX_VID field. Drops all tagged packets not belonging to RX_VID VLAN\
01: TRUNK port - passes only tagged VLAN packets. Drops all untagged packets.\
11: unqualified port - passes all traffic regardless of VLAN configuration";
type = SLV;
size = 2;
align = 2;
prefix = "Qmode";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Force 802.1q priority";
description = "1: ignores the 802.1x priority (if 802.1q header is present) and sets it to fixed value\
0: uses priority from 802.1q header";
prefix = "FIX_PRIO";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Port-assigned 802.1x priority";
description = "Packet priority value for retagging. When FIX_PRIO is 1, the endpoint uses this value as the packet priority. Otherwise, priority value is taken from 802.1q header if it's present. If there is no 802.1q header, the priority is assumed to be PRIO_VAL.";
prefix = "PRIO_VAL";
type = SLV;
size = 3;
align = 4;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Port-assigned VID";
description = "VLAN id value for tagging incoming packets if the port is in ACCESS mode. For TRUNK/unqualified the value of VID is ignored.";
prefix = "vid_VAL";
type = SLV;
align = 16;
size = 12;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Flow Control Register";
description = "";
prefix = "FCR";
field {
name = "RX Pause enable";
description = "1: enable reception of pause frames and TX path throttling \
0: disable reception of pause frames";
prefix = "RXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "TX Pause enable";
description = "1: enable transmission of pause frames and RX path throttling \
0: disable transmission of pause frames";
prefix = "TXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "TX pause threshold";
description = "Defines the percentage of space occupied in the RX buffer which triggers the transmission of a PAUSE frame. 0 = empty buffer, 255 = full buffer";
prefix = "TX_THR";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 8;
align = 8;
};
field {
name = "TX pause quanta";
description = "Defines the quanta value carried bypause frames sent by the Endpoint";
prefix = "TX_QUANTA";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
align = 16;
};
};
reg {
name = "Endpoint MAC address high part register";
prefix = "MACH";
description = "Register containing bits [47:32] of the endpoint's MAC address";
field {
name = "MAC Address";
description = "MAC Address bits [47:32]";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Endpoint MAC address low part register";
description = "Register containing bits [31:0] of the endpoint's MAC address";
prefix = "MACL";
field {
name = "MAC Address";
description = "MAC Address bits [31:0]";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DMTD Control Register";
prefix = "DMCR";
field {
name = "DMTD Phase measurement enable";
description = "1: enables DMTD phase measurement";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
description = "Number of raw DMTD phase samples averaged in every measurement cycle";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "DMTD Status register";
prefix = "DMSR";
field {
name = "DMTD Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "DMTD Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
reg {
name = "MDIO Control Register";
description = "Register controlling the read/write operations on the MDIO PHY/PCS interface. Writing to this register clears the READY bit in the MDIO Status Register";
prefix = "MDIO_CR";
field {
name = "MDIO Register Value";
description = "Data word to be written to the MDIO";
prefix = "DATA";
type = PASS_THROUGH;
size = 16;
};
field {
name = "MDIO Register Address";
description = "Address of the MDIO register to be read/written";
prefix = "ADDR";
type = SLV;
size = 8;
};
field {
name = "MDIO Read/Write select";
description = "1 = Performs a write to MDIO register at address ADDR with value DATA\
0 = Reads the value of MDIO register at address ADDR";
prefix = "RW";
align=31;
type = BIT;
};
};
reg {
name = "MDIO Status Register";
description = "Register with the current status of the MDIO interface";
prefix = "MDIO_SR";
field {
name = "MDIO Read Value";
description = "The value of the recently read MDIO register.";
prefix = "RDATA";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "MDIO Ready";
description = "1 = MDIO read/write operation is complete (for read operations, that means that RDATA contains a valid value)\
0 = MDIO operation in progress";
prefix = "READY";
align=31;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Identification register";
description = "Equal to 0xcafebabe";
prefix = "IDCODE";
field {
name = "IDCode";
type = CONSTANT;
size = 32;
value = 0xcafebabe;
};
};
reg { -- FIXME: move to HW ports (in V3) or at least add descriptions
name = "Debug/Status register";
description = "Some debug stuff";
prefix = "DSR";
field {
name = "Link status";
prefix = "LSTATUS";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Link activity";
prefix = "LACT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
ram {
name = "Event counters memory";
description = "RMON event counters:\
0x0 : TX PCS buffer underruns\
0x4 : RX PCS invalid 8b10b codes\
0x8 : RX PCS sync lost events\
0xc : RX PCS buffer overruns\
0x10: RX CRC errors\
0x14: RX valid frames\
0x18: RX runt frames\
0x1c: RX giant frames\
0x20: RX PCS errors\
0x24: RX dropped frames";
size = 32;
width = 32;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
prefix = "rmon_ram";
};
};
\ No newline at end of file
kernel/wbgen-regs/nic-regs.h 0 → 100644
View file @ ca1c8911
/*
Register definitions for slave core: White Rabbit Switch NIC's spec
* File : nic-regs.h
* Author : auto-generated by wbgen2 from nic-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE nic-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_NIC
#define __WBGEN2_REGDEFS_NIC
#include <linux/types.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: NIC Control Register */
/* definitions for field: Receive enable in reg: NIC Control Register */
#define NIC_CR_RX_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Transmit enable in reg: NIC Control Register */
#define NIC_CR_TX_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for register: NIC Status Register */
/* definitions for field: Buffer Not Available in reg: NIC Status Register */
#define NIC_SR_BNA WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Frame Received in reg: NIC Status Register */
#define NIC_SR_REC WBGEN2_GEN_MASK(1, 1)
/* definitions for register: SW_Reset */
/* definitions for register: TX Descriptor 1 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX1_D1_TS_ID_SHIFT 16
#define NIC_TX1_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX1_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 1 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 1 register 2 */
#define NIC_TX1_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX1_D2_OFFSET_SHIFT 0
#define NIC_TX1_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX1_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 1 register 2 */
#define NIC_TX1_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX1_D2_LEN_SHIFT 16
#define NIC_TX1_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX1_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 1 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 1 register 3 */
#define NIC_TX1_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX1_D3_DPM_SHIFT 0
#define NIC_TX1_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX1_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 2 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX2_D1_TS_ID_SHIFT 16
#define NIC_TX2_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX2_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 2 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 2 register 2 */
#define NIC_TX2_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX2_D2_OFFSET_SHIFT 0
#define NIC_TX2_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX2_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 2 register 2 */
#define NIC_TX2_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX2_D2_LEN_SHIFT 16
#define NIC_TX2_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX2_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 2 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 2 register 3 */
#define NIC_TX2_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX2_D3_DPM_SHIFT 0
#define NIC_TX2_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX2_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 3 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX3_D1_TS_ID_SHIFT 16
#define NIC_TX3_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX3_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 3 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 3 register 2 */
#define NIC_TX3_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX3_D2_OFFSET_SHIFT 0
#define NIC_TX3_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX3_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 3 register 2 */
#define NIC_TX3_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX3_D2_LEN_SHIFT 16
#define NIC_TX3_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX3_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 3 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 3 register 3 */
#define NIC_TX3_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX3_D3_DPM_SHIFT 0
#define NIC_TX3_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX3_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 4 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX4_D1_TS_ID_SHIFT 16
#define NIC_TX4_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX4_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 4 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 4 register 2 */
#define NIC_TX4_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX4_D2_OFFSET_SHIFT 0
#define NIC_TX4_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX4_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 4 register 2 */
#define NIC_TX4_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX4_D2_LEN_SHIFT 16
#define NIC_TX4_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX4_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 4 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 4 register 3 */
#define NIC_TX4_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX4_D3_DPM_SHIFT 0
#define NIC_TX4_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX4_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 5 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX5_D1_TS_ID_SHIFT 16
#define NIC_TX5_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX5_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 5 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 5 register 2 */
#define NIC_TX5_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX5_D2_OFFSET_SHIFT 0
#define NIC_TX5_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX5_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 5 register 2 */
#define NIC_TX5_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX5_D2_LEN_SHIFT 16
#define NIC_TX5_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX5_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 5 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 5 register 3 */
#define NIC_TX5_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX5_D3_DPM_SHIFT 0
#define NIC_TX5_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX5_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 6 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX6_D1_TS_ID_SHIFT 16
#define NIC_TX6_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX6_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 6 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 6 register 2 */
#define NIC_TX6_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX6_D2_OFFSET_SHIFT 0
#define NIC_TX6_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX6_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 6 register 2 */
#define NIC_TX6_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX6_D2_LEN_SHIFT 16
#define NIC_TX6_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX6_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 6 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 6 register 3 */
#define NIC_TX6_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX6_D3_DPM_SHIFT 0
#define NIC_TX6_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX6_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 7 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX7_D1_TS_ID_SHIFT 16
#define NIC_TX7_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX7_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 7 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 7 register 2 */
#define NIC_TX7_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX7_D2_OFFSET_SHIFT 0
#define NIC_TX7_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX7_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 7 register 2 */
#define NIC_TX7_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX7_D2_LEN_SHIFT 16
#define NIC_TX7_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX7_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 7 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 7 register 3 */
#define NIC_TX7_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX7_D3_DPM_SHIFT 0
#define NIC_TX7_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX7_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 8 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX8_D1_TS_ID_SHIFT 16
#define NIC_TX8_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX8_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 8 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 8 register 2 */
#define NIC_TX8_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX8_D2_OFFSET_SHIFT 0
#define NIC_TX8_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX8_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 8 register 2 */
#define NIC_TX8_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX8_D2_LEN_SHIFT 16
#define NIC_TX8_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX8_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 8 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 8 register 3 */
#define NIC_TX8_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX8_D3_DPM_SHIFT 0
#define NIC_TX8_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX8_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: RX Descriptor 1 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX1_D1_PORT_SHIFT 8
#define NIC_RX1_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX1_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for register: RX Descriptor 1 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 1 register 2 */
#define NIC_RX1_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX1_D2_TS_R_SHIFT 0
#define NIC_RX1_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX1_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 1 register 2 */
#define NIC_RX1_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX1_D2_TS_F_SHIFT 28
#define NIC_RX1_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX1_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 1 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 1 register 3 */
#define NIC_RX1_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX1_D3_OFFSET_SHIFT 0
#define NIC_RX1_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX1_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 1 register 3 */
#define NIC_RX1_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX1_D3_LEN_SHIFT 16
#define NIC_RX1_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX1_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 2 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX2_D1_PORT_SHIFT 8
#define NIC_RX2_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX2_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for register: RX Descriptor 2 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 2 register 2 */
#define NIC_RX2_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX2_D2_TS_R_SHIFT 0
#define NIC_RX2_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX2_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 2 register 2 */
#define NIC_RX2_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX2_D2_TS_F_SHIFT 28
#define NIC_RX2_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX2_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 2 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 2 register 3 */
#define NIC_RX2_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX2_D3_OFFSET_SHIFT 0
#define NIC_RX2_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX2_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 2 register 3 */
#define NIC_RX2_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX2_D3_LEN_SHIFT 16
#define NIC_RX2_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX2_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 3 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX3_D1_PORT_SHIFT 8
#define NIC_RX3_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX3_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for register: RX Descriptor 3 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 3 register 2 */
#define NIC_RX3_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX3_D2_TS_R_SHIFT 0
#define NIC_RX3_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX3_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 3 register 2 */
#define NIC_RX3_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX3_D2_TS_F_SHIFT 28
#define NIC_RX3_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX3_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 3 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 3 register 3 */
#define NIC_RX3_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX3_D3_OFFSET_SHIFT 0
#define NIC_RX3_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX3_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 3 register 3 */
#define NIC_RX3_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX3_D3_LEN_SHIFT 16
#define NIC_RX3_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX3_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 4 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX4_D1_PORT_SHIFT 8
#define NIC_RX4_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX4_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for register: RX Descriptor 4 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 4 register 2 */
#define NIC_RX4_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX4_D2_TS_R_SHIFT 0
#define NIC_RX4_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX4_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 4 register 2 */
#define NIC_RX4_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX4_D2_TS_F_SHIFT 28
#define NIC_RX4_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX4_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 4 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 4 register 3 */
#define NIC_RX4_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX4_D3_OFFSET_SHIFT 0
#define NIC_RX4_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX4_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 4 register 3 */
#define NIC_RX4_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX4_D3_LEN_SHIFT 16
#define NIC_RX4_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX4_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 5 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX5_D1_PORT_SHIFT 8
#define NIC_RX5_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX5_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for register: RX Descriptor 5 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 5 register 2 */
#define NIC_RX5_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX5_D2_TS_R_SHIFT 0
#define NIC_RX5_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX5_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 5 register 2 */
#define NIC_RX5_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX5_D2_TS_F_SHIFT 28
#define NIC_RX5_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX5_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 5 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 5 register 3 */
#define NIC_RX5_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX5_D3_OFFSET_SHIFT 0
#define NIC_RX5_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX5_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 5 register 3 */
#define NIC_RX5_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX5_D3_LEN_SHIFT 16
#define NIC_RX5_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX5_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 6 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX6_D1_PORT_SHIFT 8
#define NIC_RX6_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX6_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for register: RX Descriptor 6 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 6 register 2 */
#define NIC_RX6_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX6_D2_TS_R_SHIFT 0
#define NIC_RX6_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX6_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 6 register 2 */
#define NIC_RX6_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX6_D2_TS_F_SHIFT 28
#define NIC_RX6_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX6_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 6 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 6 register 3 */
#define NIC_RX6_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX6_D3_OFFSET_SHIFT 0
#define NIC_RX6_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX6_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 6 register 3 */
#define NIC_RX6_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX6_D3_LEN_SHIFT 16
#define NIC_RX6_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX6_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 7 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX7_D1_PORT_SHIFT 8
#define NIC_RX7_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX7_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for register: RX Descriptor 7 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 7 register 2 */
#define NIC_RX7_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX7_D2_TS_R_SHIFT 0
#define NIC_RX7_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX7_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 7 register 2 */
#define NIC_RX7_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX7_D2_TS_F_SHIFT 28
#define NIC_RX7_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX7_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 7 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 7 register 3 */
#define NIC_RX7_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX7_D3_OFFSET_SHIFT 0
#define NIC_RX7_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX7_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 7 register 3 */
#define NIC_RX7_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX7_D3_LEN_SHIFT 16
#define NIC_RX7_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX7_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 8 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX8_D1_PORT_SHIFT 8
#define NIC_RX8_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX8_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for register: RX Descriptor 8 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 8 register 2 */
#define NIC_RX8_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX8_D2_TS_R_SHIFT 0
#define NIC_RX8_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX8_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 8 register 2 */
#define NIC_RX8_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX8_D2_TS_F_SHIFT 28
#define NIC_RX8_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX8_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 8 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 8 register 3 */
#define NIC_RX8_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX8_D3_OFFSET_SHIFT 0
#define NIC_RX8_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX8_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 8 register 3 */
#define NIC_RX8_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX8_D3_LEN_SHIFT 16
#define NIC_RX8_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX8_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Interrupt disable register */
/* definitions for field: Receive Complete in reg: Interrupt disable register */
#define NIC_EIC_IDR_RCOMP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Transmit Complete in reg: Interrupt disable register */
#define NIC_EIC_IDR_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt disable register */
#define NIC_EIC_IDR_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt disable register */
#define NIC_EIC_IDR_TXERR WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: Receive Complete in reg: Interrupt enable register */
#define NIC_EIC_IER_RCOMP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Transmit Complete in reg: Interrupt enable register */
#define NIC_EIC_IER_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt enable register */
#define NIC_EIC_IER_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt enable register */
#define NIC_EIC_IER_TXERR WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: Receive Complete in reg: Interrupt mask register */
#define NIC_EIC_IMR_RCOMP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Transmit Complete in reg: Interrupt mask register */
#define NIC_EIC_IMR_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt mask register */
#define NIC_EIC_IMR_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt mask register */
#define NIC_EIC_IMR_TXERR WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: Receive Complete in reg: Interrupt status register */
#define NIC_EIC_ISR_RCOMP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Transmit Complete in reg: Interrupt status register */
#define NIC_EIC_ISR_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt status register */
#define NIC_EIC_ISR_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt status register */
#define NIC_EIC_ISR_TXERR WBGEN2_GEN_MASK(3, 1)
/* definitions for RAM: TX/RX Buffers */
#define NIC_MEM_BYTES 0x00008000 /* size in bytes */
#define NIC_MEM_WORDS 0x00002000 /* size in 32-bit words, 32-bit aligned */
PACKED struct NIC_WB {
/* [0x0]: REG NIC Control Register */
uint32_t CR;
/* [0x4]: REG NIC Status Register */
uint32_t SR;
/* [0x8]: REG SW_Reset */
uint32_t RESET;
/* padding to: 4 words */
uint32_t __padding_0[1];
/* [0x10]: REG TX Descriptor 1 register 1 */
uint32_t TX1_D1;
/* [0x14]: REG TX Descriptor 1 register 2 */
uint32_t TX1_D2;
/* [0x18]: REG TX Descriptor 1 register 3 */
uint32_t TX1_D3;
/* padding to: 8 words */
uint32_t __padding_1[1];
/* [0x20]: REG TX Descriptor 2 register 1 */
uint32_t TX2_D1;
/* [0x24]: REG TX Descriptor 2 register 2 */
uint32_t TX2_D2;
/* [0x28]: REG TX Descriptor 2 register 3 */
uint32_t TX2_D3;
/* padding to: 12 words */
uint32_t __padding_2[1];
/* [0x30]: REG TX Descriptor 3 register 1 */
uint32_t TX3_D1;
/* [0x34]: REG TX Descriptor 3 register 2 */
uint32_t TX3_D2;
/* [0x38]: REG TX Descriptor 3 register 3 */
uint32_t TX3_D3;
/* padding to: 16 words */
uint32_t __padding_3[1];
/* [0x40]: REG TX Descriptor 4 register 1 */
uint32_t TX4_D1;
/* [0x44]: REG TX Descriptor 4 register 2 */
uint32_t TX4_D2;
/* [0x48]: REG TX Descriptor 4 register 3 */
uint32_t TX4_D3;
/* padding to: 20 words */
uint32_t __padding_4[1];
/* [0x50]: REG TX Descriptor 5 register 1 */
uint32_t TX5_D1;
/* [0x54]: REG TX Descriptor 5 register 2 */
uint32_t TX5_D2;
/* [0x58]: REG TX Descriptor 5 register 3 */
uint32_t TX5_D3;
/* padding to: 24 words */
uint32_t __padding_5[1];
/* [0x60]: REG TX Descriptor 6 register 1 */
uint32_t TX6_D1;
/* [0x64]: REG TX Descriptor 6 register 2 */
uint32_t TX6_D2;
/* [0x68]: REG TX Descriptor 6 register 3 */
uint32_t TX6_D3;
/* padding to: 28 words */
uint32_t __padding_6[1];
/* [0x70]: REG TX Descriptor 7 register 1 */
uint32_t TX7_D1;
/* [0x74]: REG TX Descriptor 7 register 2 */
uint32_t TX7_D2;
/* [0x78]: REG TX Descriptor 7 register 3 */
uint32_t TX7_D3;
/* padding to: 32 words */
uint32_t __padding_7[1];
/* [0x80]: REG TX Descriptor 8 register 1 */
uint32_t TX8_D1;
/* [0x84]: REG TX Descriptor 8 register 2 */
uint32_t TX8_D2;
/* [0x88]: REG TX Descriptor 8 register 3 */
uint32_t TX8_D3;
/* padding to: 36 words */
uint32_t __padding_8[1];
/* [0x90]: REG RX Descriptor 1 register 1 */
uint32_t RX1_D1;
/* [0x94]: REG RX Descriptor 1 register 2 */
uint32_t RX1_D2;
/* [0x98]: REG RX Descriptor 1 register 3 */
uint32_t RX1_D3;
/* padding to: 40 words */
uint32_t __padding_9[1];
/* [0xa0]: REG RX Descriptor 2 register 1 */
uint32_t RX2_D1;
/* [0xa4]: REG RX Descriptor 2 register 2 */
uint32_t RX2_D2;
/* [0xa8]: REG RX Descriptor 2 register 3 */
uint32_t RX2_D3;
/* padding to: 44 words */
uint32_t __padding_10[1];
/* [0xb0]: REG RX Descriptor 3 register 1 */
uint32_t RX3_D1;
/* [0xb4]: REG RX Descriptor 3 register 2 */
uint32_t RX3_D2;
/* [0xb8]: REG RX Descriptor 3 register 3 */
uint32_t RX3_D3;
/* padding to: 48 words */
uint32_t __padding_11[1];
/* [0xc0]: REG RX Descriptor 4 register 1 */
uint32_t RX4_D1;
/* [0xc4]: REG RX Descriptor 4 register 2 */
uint32_t RX4_D2;
/* [0xc8]: REG RX Descriptor 4 register 3 */
uint32_t RX4_D3;
/* padding to: 52 words */
uint32_t __padding_12[1];
/* [0xd0]: REG RX Descriptor 5 register 1 */
uint32_t RX5_D1;
/* [0xd4]: REG RX Descriptor 5 register 2 */
uint32_t RX5_D2;
/* [0xd8]: REG RX Descriptor 5 register 3 */
uint32_t RX5_D3;
/* padding to: 56 words */
uint32_t __padding_13[1];
/* [0xe0]: REG RX Descriptor 6 register 1 */
uint32_t RX6_D1;
/* [0xe4]: REG RX Descriptor 6 register 2 */
uint32_t RX6_D2;
/* [0xe8]: REG RX Descriptor 6 register 3 */
uint32_t RX6_D3;
/* padding to: 60 words */
uint32_t __padding_14[1];
/* [0xf0]: REG RX Descriptor 7 register 1 */
uint32_t RX7_D1;
/* [0xf4]: REG RX Descriptor 7 register 2 */
uint32_t RX7_D2;
/* [0xf8]: REG RX Descriptor 7 register 3 */
uint32_t RX7_D3;
/* padding to: 64 words */
uint32_t __padding_15[1];
/* [0x100]: REG RX Descriptor 8 register 1 */
uint32_t RX8_D1;
/* [0x104]: REG RX Descriptor 8 register 2 */
uint32_t RX8_D2;
/* [0x108]: REG RX Descriptor 8 register 3 */
uint32_t RX8_D3;
/* padding to: 72 words */
uint32_t __padding_16[5];
/* [0x120]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x124]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x128]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x12c]: REG Interrupt status register */
uint32_t EIC_ISR;
/* padding to: 8192 words */
uint32_t __padding_17[8116];
/* [0x8000 - 0xffff]: RAM TX/RX Buffers, 8192 32-bit words, 32-bit aligned, word-addressable */
uint32_t MEM [8192];
};
#endif
kernel/wbgen-regs/nic-regs.wb 0 → 100644
View file @ ca1c8911
-- -*- Mode: LUA; tab-width: 2 -*-
-- White-Rabbit NIC spec
-- author: Emilio G. Cota <cota@braap.org>
-- updated by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
--
-- Use wbgen2 to generate code, documentation and more.
-- wbgen2 is available at:
-- http://www.ohwr.org/projects/wishbone-gen
--
top = peripheral {
name = "White Rabbit Switch NIC's spec",
description = "This NIC is in between the endpoints and the on-board Linux CPU of the White Rabbit Switch.\
\
Operation \
~~~~~~~ \
* There's a pool of n TX descriptors and a pool of n RX descriptors. \
* In fact, we should have n for TX and m for RX since 32K / 1536 = 21.3. Anyway, to make things simple, first let's do n and n; we can fine-tune later on. \
* Software keeps track of which buffers are marked to be used with the READY/EMPTY flags. \
* Interrupts are useed by software to update the state, e.g. when frames are received or when a frame has been sent. \
* Endianness: all multi-byte registers are Little Endian \
\
Frame transmission \
~~~~~~~~~~~~~~~ \
* Enable Transmission in the Control Register \
* Store the frame in memory \
* Fill in the corresponding descriptor from the TX pool \
* Set READY bit to 1 \
* Interrupt arrives--if enabled-- and software updates stats reading the descriptor (READY has been set to 0 by the NIC). \
\
Frame reception \
~~~~~~~~~~~~~ \
* Enable Reception in the Control Register \
* Initialize a descriptor from the RX descriptors pool. Mark it as EMPTY \
* A frame is received and, if enabled, the NIC raises an interrupt \
* With EMPTY set to 0, the frame can now be copied from the NIC's memory and stats can be updated \
* Set READY bit to 1 \
\
Todo \
~~~~ \
* Descriptors in RAM, not as registers. wbgen2 doesn't support this yet. Working on it. \
Known issues \
~~~~~~~~~~~ \
* Only 32-bit aligned addresses are supported";
hdl_entity = "nic_wishbone_slave";
prefix = "nic";
reg {
name = "NIC Control Register";
prefix = "CR";
field {
name = "Receive enable";
description = "Enables the NIC to receive data";
prefix = "rx_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Transmit enable";
description = "Enables the NIC to transmit data. When reset, the internal transmit pointer points to the first entry in the TX descriptor pool";
prefix = "tx_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "NIC Status Register";
prefix = "SR";
field {
name = "Buffer Not Available";
prefix = "bna";
description = "No buffers were available when receiving a packet. Cleared by writing a one to this bit";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Frame Received";
prefix = "rec";
description = "One or more frames have been received.\
Cleared by writing a one to this bit";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "SW_Reset";
description = "Writing to this register resets the NIC, zeroing all registers and resetting the state of the module";
prefix = "reset";
field {
name = "Software reset";
type = PASS_THROUGH;
size = 32;
};
};
irq {
name = "Receive Complete";
prefix = "rcomp";
description = "A frame has been stored in memory.";
trigger = LEVEL_1;
};
irq {
name = "Transmit Complete";
prefix = "tcomp";
description = "Frame successfully transmitted";
trigger = LEVEL_1;
};
irq {
name = "Receive Error";
prefix = "rxerr";
description = "Receive Error";
trigger = LEVEL_1;
};
irq {
name = "Transmit Error";
prefix = "txerr";
trigger = LEVEL_1;
};
-- ram {
-- name = "TX descriptors mem";
-- prefix = "dtx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
-- ram {
-- name = "RX descriptors mem";
-- prefix = "drx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
ram {
name = "TX/RX Buffers";
prefix = "mem";
-- 8192 * 32 = 32Kb
size = 8192;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
TX_desc_template =
{
reg {
name = "TX Descriptor %d register 1";
description = "1st part of TX descriptor header. ";
prefix = "tx%d_d1";
align = 4;
field {
name = "Ready";
prefix = "ready";
description = "0 - The descriptor and buffer can be manipulated. \
1 - The device owns the descriptor and will set the bit to 0 after transmission";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Error";
prefix = "error";
description = "1 - an error occured during transmission of this descriptor.\
0 - transmission was successful";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Timestamp Enable";
description = "Set to 1 if the frame has to be timestamped by the endpoint. The NIC will then generate a TX OOB block on its WRF source, containing the value of TS_ID from the descriptor. ";
prefix = "ts_e";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Pad Enable";
prefix = "pad_e";
description = "When set, short frames (< 60 bytes) are padded with zeros to 60 bytes. This doesn't include the CRC field (so the final frame length will be 64 bytes)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
-- todo: Errors: add some more, e.g. Retry Count, Retry Limit exceeded...
field {
name = "Timestamp Frame Identifier";
prefix = "ts_id";
description = "Frame Identifier - a 16-bit value which must be unique in reasonably long time period. It's used to match the TX timestamps coming from different physical ports with the timestamped packets.";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX Descriptor %d register 2";
prefix = "tx%d_d2";
-- extended the sizes to 16 bits (although the buffer is 32kB-long)
field {
name = "offset in RAM--in bytes, must be aligned to 32-bit boundary";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Length of buffer in bytes";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX Descriptor %d register 3";
prefix = "tx%d_d3";
field {
prefix = "DPM";
name = "Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet.";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
RX_desc_template = {
reg {
align=4;
name = "RX Descriptor %d register 1";
description = "Descriptor of an RX frame buffer";
prefix = "rx%d_d1";
field {
name = "Empty";
prefix = "empty";
description = "0 - Reception (or failure) has occurred on this buffer. The NIC cannot operate on the until this bit is set to 1. \
1 - The buffer is ready to be filled in with data by the NIC";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Error";
prefix = "error";
description = "Set when the the received frame contains an error (an error was indicated by the remote WRF source)";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block.";
prefix = "port";
type = SLV;
size = 6;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Got RX Timestamp";
prefix = "GOT_TS";
description = "1 - there is a valid RX timestamp present in the TS field,\
0 - no RX timestamp";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "RX Descriptor %d register 2";
prefix = "rx%d_d2";
field {
name = "RX_TS_R";
description = "Value of the RX timestamp (rising edge bits)";
prefix = "TS_R";
size = 28;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX_TS_F";
prefix = "TS_F";
description = "Value of the RX timestamp (falling edge bits)";
size = 4;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "RX Descriptor %d register 3";
prefix = "rx%d_d3";
field {
name = "Offset in packet RAM (in bytes, 32-bit aligned)";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet.";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
function generate_descriptors(n)
local i;
for i=1,n do
local T=deepcopy(TX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
print(r.name)
end, T);
table_join(periph, T);
end
for i=1,n do
local T=deepcopy(RX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
end, T);
table_join(periph, T);
end
end
generate_descriptors(8);
kernel/wbgen-regs/ppsg-regs.h 0 → 100644
View file @ ca1c8911
/*
Register definitions for slave core: WR Switch PPS generator and RTC
* File : ppsg-regs.h
* Author : auto-generated by wbgen2 from ppsg-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ppsg-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_PPSG
#define __WBGEN2_REGDEFS_PPSG
#include <linux/types.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Reset counter in reg: Control Register */
#define PPSG_CR_CNT_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Enable counter in reg: Control Register */
#define PPSG_CR_CNT_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Adjust offset in reg: Control Register */
#define PPSG_CR_CNT_ADJ WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Set time in reg: Control Register */
#define PPSG_CR_CNT_SET WBGEN2_GEN_MASK(3, 1)
/* definitions for field: PPS Pulse width in reg: Control Register */
#define PPSG_CR_PWIDTH_MASK WBGEN2_GEN_MASK(4, 28)
#define PPSG_CR_PWIDTH_SHIFT 4
#define PPSG_CR_PWIDTH_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define PPSG_CR_PWIDTH_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Nanosecond counter register */
/* definitions for register: UTC Counter register (least-significant part) */
/* definitions for register: UTC Counter register (most-significant part) */
/* definitions for register: Nanosecond adjustment register */
/* definitions for register: UTC Adjustment register (least-significant part) */
/* definitions for register: UTC Adjustment register (most-significant part) */
PACKED struct PPSG_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
/* [0x4]: REG Nanosecond counter register */
uint32_t CNTR_NSEC;
/* [0x8]: REG UTC Counter register (least-significant part) */
uint32_t CNTR_UTCLO;
/* [0xc]: REG UTC Counter register (most-significant part) */
uint32_t CNTR_UTCHI;
/* [0x10]: REG Nanosecond adjustment register */
uint32_t ADJ_NSEC;
/* [0x14]: REG UTC Adjustment register (least-significant part) */
uint32_t ADJ_UTCLO;
/* [0x18]: REG UTC Adjustment register (most-significant part) */
uint32_t ADJ_UTCHI;
};
#endif
kernel/wbgen-regs/ppsg-regs.wb 0 → 100644
View file @ ca1c8911
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Switch PPS generator and RTC";
description = "Unit generating PPS signals and acting as a UTC real-time clock";
hdl_entity = "pps_gen_wb";
prefix = "ppsg";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Reset counter";
description = "write 1: resets the counter\
write 0: no effect";
prefix = "CNT_RST";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "Enable counter";
description = "1: PPS counter is enabled";
prefix = "CNT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Adjust offset";
description = "write 1: Starts adjusting PPS/UTC offsets by adding the values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers to the current PPS counter value. These registers need to be programmed prior to update.\
write 0: no effect\
read 0: adjustment operation is done\
read 1: adjustment operation is in progress";
prefix = "CNT_ADJ";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "Set time";
description = "write 1: Sets the UTC/PPS counter to values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers";
prefix = "CNT_SET";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "PPS Pulse width";
description = "Width of generated PPS pulses in 125 MHz refernce clock cycles";
prefix = "PWIDTH";
size = 28;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock= "refclk_i";
};
};
reg {
name = "Nanosecond counter register";
description = "Nanosecond part of current time, expressed as number of 125 MHz reference clock cycles";
prefix = "CNTR_NSEC";
field {
name = "Nanosecond counter";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "UTC Counter register (least-significant part)";
description = "Lower 32 bits of current UTC time";
prefix = "CNTR_UTCLO";
field {
name = "UTC Counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "UTC Counter register (most-significant part)";
description = "Highest 8 bits of current UTC time";
prefix = "CNTR_UTCHI";
field {
name = "UTC Counter";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "Nanosecond adjustment register";
description = "Adjustment value for nanosecond counter";
prefix = "ADJ_NSEC";
field {
name = "Nanosecond adjustment";
type = PASS_THROUGH;
size = 28;
};
};
reg {
name = "UTC Adjustment register (least-significant part)";
description = "Lower 32 bits of adjustment value for UTC";
prefix = "ADJ_UTCLO";
field {
name = "UTC Counter adjustment";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "UTC Adjustment register (most-significant part)";
description = "Highest 8 bits of adjustment value for UTC";
prefix = "ADJ_UTCHI";
field {
name = "UTC Counter adjustment";
type = PASS_THROUGH;
size = 8;
};
};
};
kernel/wbgen-regs/rtu-regs.h 0 → 100644
View file @ ca1c8911
/*
Register definitions for slave core: Routing Table Unit (RTU)
* File : rtu-regs.h
* Author : auto-generated by wbgen2 from rtu-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_RTU
#define __WBGEN2_REGDEFS_RTU
#include <linux/types.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: RTU Global Control Register */
/* definitions for field: Main table bank select in reg: RTU Global Control Register */
#define RTU_GCR_HT_BSEL WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Hash collision table (HCAM) bank select in reg: RTU Global Control Register */
#define RTU_GCR_HCAM_BSEL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: RTU Global Enable in reg: RTU Global Control Register */
#define RTU_GCR_G_ENA WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Hash Poly in reg: RTU Global Control Register */
#define RTU_GCR_POLY_VAL_MASK WBGEN2_GEN_MASK(8, 16)
#define RTU_GCR_POLY_VAL_SHIFT 8
#define RTU_GCR_POLY_VAL_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define RTU_GCR_POLY_VAL_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: Aging register for HCAM */
/* definitions for register: Port Control Register 0 */
/* definitions for field: Learning enable in reg: Port Control Register 0 */
#define RTU_PCR0_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 0 */
#define RTU_PCR0_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 0 */
#define RTU_PCR0_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 0 */
#define RTU_PCR0_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 0 */
#define RTU_PCR0_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR0_PRIO_VAL_SHIFT 4
#define RTU_PCR0_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR0_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 0 */
#define RTU_PCR0_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 1 */
/* definitions for field: Learning enable in reg: Port Control Register 1 */
#define RTU_PCR1_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 1 */
#define RTU_PCR1_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 1 */
#define RTU_PCR1_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 1 */
#define RTU_PCR1_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 1 */
#define RTU_PCR1_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR1_PRIO_VAL_SHIFT 4
#define RTU_PCR1_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR1_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 1 */
#define RTU_PCR1_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 2 */
/* definitions for field: Learning enable in reg: Port Control Register 2 */
#define RTU_PCR2_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 2 */
#define RTU_PCR2_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 2 */
#define RTU_PCR2_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 2 */
#define RTU_PCR2_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 2 */
#define RTU_PCR2_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR2_PRIO_VAL_SHIFT 4
#define RTU_PCR2_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR2_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 2 */
#define RTU_PCR2_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 3 */
/* definitions for field: Learning enable in reg: Port Control Register 3 */
#define RTU_PCR3_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 3 */
#define RTU_PCR3_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 3 */
#define RTU_PCR3_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 3 */
#define RTU_PCR3_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 3 */
#define RTU_PCR3_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR3_PRIO_VAL_SHIFT 4
#define RTU_PCR3_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR3_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 3 */
#define RTU_PCR3_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 4 */
/* definitions for field: Learning enable in reg: Port Control Register 4 */
#define RTU_PCR4_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 4 */
#define RTU_PCR4_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 4 */
#define RTU_PCR4_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 4 */
#define RTU_PCR4_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 4 */
#define RTU_PCR4_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR4_PRIO_VAL_SHIFT 4
#define RTU_PCR4_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR4_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 4 */
#define RTU_PCR4_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 5 */
/* definitions for field: Learning enable in reg: Port Control Register 5 */
#define RTU_PCR5_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 5 */
#define RTU_PCR5_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 5 */
#define RTU_PCR5_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 5 */
#define RTU_PCR5_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 5 */
#define RTU_PCR5_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR5_PRIO_VAL_SHIFT 4
#define RTU_PCR5_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR5_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 5 */
#define RTU_PCR5_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 6 */
/* definitions for field: Learning enable in reg: Port Control Register 6 */
#define RTU_PCR6_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 6 */
#define RTU_PCR6_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 6 */
#define RTU_PCR6_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 6 */
#define RTU_PCR6_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 6 */
#define RTU_PCR6_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR6_PRIO_VAL_SHIFT 4
#define RTU_PCR6_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR6_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 6 */
#define RTU_PCR6_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 7 */
/* definitions for field: Learning enable in reg: Port Control Register 7 */
#define RTU_PCR7_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 7 */
#define RTU_PCR7_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 7 */
#define RTU_PCR7_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 7 */
#define RTU_PCR7_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 7 */
#define RTU_PCR7_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR7_PRIO_VAL_SHIFT 4
#define RTU_PCR7_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR7_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 7 */
#define RTU_PCR7_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 8 */
/* definitions for field: Learning enable in reg: Port Control Register 8 */
#define RTU_PCR8_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 8 */
#define RTU_PCR8_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 8 */
#define RTU_PCR8_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 8 */
#define RTU_PCR8_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 8 */
#define RTU_PCR8_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR8_PRIO_VAL_SHIFT 4
#define RTU_PCR8_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR8_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 8 */
#define RTU_PCR8_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Port Control Register 9 */
/* definitions for field: Learning enable in reg: Port Control Register 9 */
#define RTU_PCR9_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register 9 */
#define RTU_PCR9_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register 9 */
#define RTU_PCR9_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register 9 */
#define RTU_PCR9_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register 9 */
#define RTU_PCR9_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR9_PRIO_VAL_SHIFT 4
#define RTU_PCR9_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR9_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register 9 */
#define RTU_PCR9_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: Interrupt disable register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt disable register */
#define RTU_EIC_IDR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt enable register */
#define RTU_EIC_IER_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt mask register */
#define RTU_EIC_IMR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt status register */
#define RTU_EIC_ISR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
/* definitions for field: Destination MAC address least-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
#define RTU_UFIFO_R0_DMAC_LO_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_UFIFO_R0_DMAC_LO_SHIFT 0
#define RTU_UFIFO_R0_DMAC_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_UFIFO_R0_DMAC_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
/* definitions for field: Destination MAC address most-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
#define RTU_UFIFO_R1_DMAC_HI_MASK WBGEN2_GEN_MASK(0, 16)
#define RTU_UFIFO_R1_DMAC_HI_SHIFT 0
#define RTU_UFIFO_R1_DMAC_HI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_UFIFO_R1_DMAC_HI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
/* definitions for field: Source MAC address least-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
#define RTU_UFIFO_R2_SMAC_LO_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_UFIFO_R2_SMAC_LO_SHIFT 0
#define RTU_UFIFO_R2_SMAC_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_UFIFO_R2_SMAC_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
/* definitions for field: Source MAC address most-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
#define RTU_UFIFO_R3_SMAC_HI_MASK WBGEN2_GEN_MASK(0, 16)
#define RTU_UFIFO_R3_SMAC_HI_SHIFT 0
#define RTU_UFIFO_R3_SMAC_HI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_UFIFO_R3_SMAC_HI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
/* definitions for field: VLAN Identifier in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_VID_MASK WBGEN2_GEN_MASK(0, 12)
#define RTU_UFIFO_R4_VID_SHIFT 0
#define RTU_UFIFO_R4_VID_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define RTU_UFIFO_R4_VID_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Priority in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_PRIO_MASK WBGEN2_GEN_MASK(12, 3)
#define RTU_UFIFO_R4_PRIO_SHIFT 12
#define RTU_UFIFO_R4_PRIO_W(value) WBGEN2_GEN_WRITE(value, 12, 3)
#define RTU_UFIFO_R4_PRIO_R(reg) WBGEN2_GEN_READ(reg, 12, 3)
/* definitions for field: Port ID in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_PID_MASK WBGEN2_GEN_MASK(16, 4)
#define RTU_UFIFO_R4_PID_SHIFT 16
#define RTU_UFIFO_R4_PID_W(value) WBGEN2_GEN_WRITE(value, 16, 4)
#define RTU_UFIFO_R4_PID_R(reg) WBGEN2_GEN_READ(reg, 16, 4)
/* definitions for field: VID valid in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_HAS_VID WBGEN2_GEN_MASK(20, 1)
/* definitions for field: PRIO valid in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_HAS_PRIO WBGEN2_GEN_MASK(21, 1)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_UFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_UFIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 7)
#define RTU_UFIFO_CSR_USEDW_SHIFT 0
#define RTU_UFIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define RTU_UFIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
/* definitions for field: Address/data select in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
#define RTU_MFIFO_R0_AD_SEL WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
/* definitions for field: Address/data value in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
#define RTU_MFIFO_R1_AD_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_MFIFO_R1_AD_VAL_SHIFT 0
#define RTU_MFIFO_R1_AD_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_MFIFO_R1_AD_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 6)
#define RTU_MFIFO_CSR_USEDW_SHIFT 0
#define RTU_MFIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define RTU_MFIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for RAM: Hash collisions memory (HCAM) */
#define RTU_HCAM_BYTES 0x00000800 /* size in bytes */
#define RTU_HCAM_WORDS 0x00000200 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: Aging bitmap for main hashtable */
#define RTU_ARAM_MAIN_BYTES 0x00000400 /* size in bytes */
#define RTU_ARAM_MAIN_WORDS 0x00000100 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: VLAN table (VLAN_TAB) */
#define RTU_VLAN_TAB_BYTES 0x00004000 /* size in bytes */
#define RTU_VLAN_TAB_WORDS 0x00001000 /* size in 32-bit words, 32-bit aligned */
PACKED struct RTU_WB {
/* [0x0]: REG RTU Global Control Register */
uint32_t GCR;
/* [0x4]: REG Aging register for HCAM */
uint32_t AGR_HCAM;
/* [0x8]: REG Port Control Register 0 */
uint32_t PCR0;
/* [0xc]: REG Port Control Register 1 */
uint32_t PCR1;
/* [0x10]: REG Port Control Register 2 */
uint32_t PCR2;
/* [0x14]: REG Port Control Register 3 */
uint32_t PCR3;
/* [0x18]: REG Port Control Register 4 */
uint32_t PCR4;
/* [0x1c]: REG Port Control Register 5 */
uint32_t PCR5;
/* [0x20]: REG Port Control Register 6 */
uint32_t PCR6;
/* [0x24]: REG Port Control Register 7 */
uint32_t PCR7;
/* [0x28]: REG Port Control Register 8 */
uint32_t PCR8;
/* [0x2c]: REG Port Control Register 9 */
uint32_t PCR9;
/* padding to: 16 words */
uint32_t __padding_0[4];
/* [0x40]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x44]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x48]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x4c]: REG Interrupt status register */
uint32_t EIC_ISR;
/* [0x50]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
uint32_t UFIFO_R0;
/* [0x54]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
uint32_t UFIFO_R1;
/* [0x58]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
uint32_t UFIFO_R2;
/* [0x5c]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
uint32_t UFIFO_R3;
/* [0x60]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
uint32_t UFIFO_R4;
/* [0x64]: REG FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
uint32_t UFIFO_CSR;
/* [0x68]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
uint32_t MFIFO_R0;
/* [0x6c]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
uint32_t MFIFO_R1;
/* [0x70]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
uint32_t MFIFO_CSR;
/* padding to: 4096 words */
uint32_t __padding_1[4067];
/* [0x4000 - 0x47ff]: RAM Hash collisions memory (HCAM), 512 32-bit words, 32-bit aligned, word-addressable */
uint32_t HCAM [512];
/* padding to: 8192 words */
uint32_t __padding_2[4096];
/* [0x8000 - 0x83ff]: RAM Aging bitmap for main hashtable, 256 32-bit words, 32-bit aligned, word-addressable */
uint32_t ARAM_MAIN [256];
/* padding to: 12288 words */
uint32_t __padding_3[4096];
/* [0xc000 - 0xffff]: RAM VLAN table (VLAN_TAB), 4096 32-bit words, 32-bit aligned, word-addressable */
uint32_t VLAN_TAB [4096];
};
#endif
kernel/wbgen-regs/rtu-regs.wb 0 → 100644
View file @ ca1c8911
-- -*- Mode: LUA; tab-width: 2 -*-
PCR_template = reg {
name = "Port Control Register";
description = "Register controlling the mode of certain RTU port.";
prefix = "PCR";
field {
name = "Learning enable";
description = "1: enables learning process on this port. Unrecognized requests will be put into UFIFO\
0: disables learning. Unrecognized requests will be either broadcast or dropped.";
prefix = "LEARN_EN";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Pass all packets";
description = "1: all packets are passed (depending on the rules in RT table). \
0: all packets are dropped on this port.";
prefix = "PASS_ALL";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Pass BPDUs";
description = "1: BPDU packets (with dst MAC 01:80:c2:00:00:00) are passed according to RT rules. This setting overrides PASS_ALL.\
0: BPDU packets are passed according to RTU rules only if PASS_ALL is set.[ML by modified]";
prefix = "PASS_BPDU";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Fix priority";
description = "1: Port has fixed priority of value PRIO_VAL. It overrides the priority coming from the endpoint\
0: Use priority from the endpoint";
prefix = "FIX_PRIO";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Priority value";
description = "Fixed priority value for the port. Used instead the endpoint-assigned priority when FIX_PRIO = 1";
prefix = "PRIO_VAL";
type = SLV;
align = 4;
size =3 ;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Unrecognized request behaviour";
description = "Sets the port behaviour for all unrecognized requests:\
0: packet is dropped\
1: packet is broadcast";
prefix = "B_UNREC";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
-- Mirroring Control fields go here.
};
peripheral {
name = "Routing Table Unit (RTU)";
prefix="rtu";
hdl_entity="wrsw_rtu_wb";
-- Port Configuration Register
reg {
name = "RTU Global Control Register";
description = "Control register containing global (port-independent) settings of the RTU.";
prefix = "GCR";
field {
name = "Main table bank select";
description = "Selects active bank of RTU hashtable (ZBT).\
0: bank 0 is used by lookup engine and bank 1 can be accessed using MFIFO\
1: bank 1 is used by lookup engine and bank 0 can be accessed using MFIFO";
type = BIT;
prefix = "HT_BSEL";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Hash collision table (HCAM) bank select";
description = "Selects active bank of RTU extra memory for colliding hashes.\
0: bank 0 is used by lookup engine\
1: bank 1 is used by lookup engine";
type = BIT;
prefix = "HCAM_BSEL";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "RTU Global Enable";
description = "Global RTU enable bit. Overrides all port settings.\
0: RTU is disabled. All packets are dropped.\
1: RTU is enabled.";
type = BIT;
prefix = "G_ENA";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Hash Poly";
description = "Determines the polynomial used for hash computation. Currently available: 0x1021, 0x8005, 0x0589 ";
type = SLV;
prefix = "POLY_VAL";
align = 8;
size = 16 ;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
clock = "zbt_clk_i";
};
-- TXTSU interrupts
irq {
name = "UFIFO Not Empty IRQ";
description = "Interrupt active when there are some requests in UFIFO.";
prefix = "nempty";
trigger = LEVEL_0;
};
fifo_reg {
name = "Unrecognized request FIFO (UFIFO)";
description = "FIFO containing all RTU requests for which matching entries haven't been found. CPU reads these requests,\
evaluates them and updates the RTU tables accordingly.";
prefix = "UFIFO";
direction = CORE_TO_BUS;
size = 128;
flags_dev = {FIFO_FULL, FIFO_EMPTY};
flags_bus = {FIFO_EMPTY, FIFO_COUNT};
--clock = "zbt_clk_i";
-- clock = ""; - make it asynchronous if you want
field {
name = "Destination MAC address least-significant part";
description = "Bits [31:0] of packet destination MAC address";
prefix = "DMAC_LO";
type = SLV;
size = 32;
};
field {
name = "Destination MAC address most-significant part";
description = "Bits [47:32] of packet destination MAC address";
prefix = "DMAC_HI";
type = SLV;
size = 16;
};
field {
name = "Source MAC address least-significant part";
description = "Bits [31:0] of packet source MAC address";
prefix = "SMAC_LO";
type = SLV;
size = 32;
};
field {
name = "Source MAC address most-significant part";
description = "Bits [47:32] of packet source MAC address";
prefix = "SMAC_HI";
type = SLV;
size = 16;
};
field {
name = "VLAN Identifier";
description = "VLAN ID of the packet (from the endpoint)";
prefix = "VID";
size = 12;
type = SLV;
align = 32;
};
field {
name = "Priority";
description = "Priority value (from the endpoint)";
prefix = "PRIO";
size = 3;
align = 4;
type = SLV;
};
field {
name = "Port ID";
description = "Identifier of RTU port to which came the request.";
prefix = "PID";
size = 4;
align = 4;
type = SLV;
};
field {
name = "VID valid";
description = "1: VID value is valid\
0: packet had no VLAN ID";
prefix = "HAS_VID";
align = 4;
type = BIT;
};
field {
name = "PRIO valid";
description = "1: PRIO value is valid\
0: packet had no priority assigned";
prefix = "HAS_PRIO";
type = BIT;
};
};
ram {
name = "Hash collisions memory (HCAM)";
description = "Memory block containing the 'tails' for hashes which have more than 4 entries and don't fit into a single bucket of main ZBT hashtable. \
<b>Note:</b> MSB of the address is the bank select bit. ";
prefix = "HCAM";
width = 32;
size = 32 * 8 * 2; -- 32 entries * 8 words per entry * 2 banks
access_dev = READ_ONLY;
access_bus = READ_WRITE;
clock = "zbt_clk_i"; --async?
};
ram {
name = "Aging bitmap for main hashtable";
description = "Each bit in this memory reflects the state of corresponding entry in main hashtable:\
0: entry wasn't matched\
1: entry was matched at least once.\
CPU reads this bitmap and subsequently clears it every few seconds to update the aging counters.";
prefix = "ARAM_MAIN";
width = 32;
size = 8192 / 32; -- 8192 bits
access_dev = READ_WRITE;
access_bus = READ_WRITE;
--[changed 6/10/2010] clock = "zbt_clk_i";
--clock = "zbt_clk_i"; --async?
};
ram {
name = "VLAN table (VLAN_TAB)";
description = "It stores VLAN-related information identified by VLAN ID (VID)";
prefix = "VLAN_TAB";
width = 32;
size = 4096 ; -- 4096 entries as defined in 802.1Q-2005, page 12
access_dev = READ_ONLY;
access_bus = READ_WRITE;
-- --[changed 6/10/2010] clock = "zbt_clk_i";
--clock = "zbt_clk_i"; --async?
};
reg {
name = "Aging register for HCAM";
description = "Each bit in this register reflects the state of corresponding entry in HCAM:\
0: entry wasn't matched\
1: entry was matched at least once.\
CPU reads this bitmap and subsequently clears it every few seconds to update the aging counters.";
prefix = "AGR_HCAM";
field {
name = "Aging register value";
type = SLV;
size = 32;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
clock = "zbt_clk_i";
-- clock = "zbt_clk_i"; --async?
};
fifo_reg {
name = "Main hashtable CPU access FIFO (MFIFO)";
description = "FIFO for writing to main hashtable";
prefix = "MFIFO";
direction = BUS_TO_CORE;
size = 64;
flags_dev = {FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_EMPTY, FIFO_FULL, FIFO_COUNT};
field {
name = "Address/data select";
description = "1: AD_VAL contains new memory address\
0: AD_VAL contains data word to be written at current memory address. Then, the address is incremented";
prefix = "AD_SEL";
type = BIT;
};
field {
name = "Address/data value";
description = "Value of new memory address (when AD_SEL = 1) or data word to be written (when AD_SEL = 0)";
prefix = "AD_VAL";
type = SLV;
align =32;
size = 32;
};
clock = "zbt_clk_i";
};
};
function gen_PCRs(num_pcrs)
local i;
for i=0,num_pcrs-1 do
local rp = deepcopy(PCR_template);
rp.name = rp.name.." "..i;
rp.prefix = rp.prefix..i;
table.insert(periph, rp);
end
end
gen_PCRs(10);
kernel/wbgen-regs/tstamp-regs.h 0 → 100644
View file @ ca1c8911
/*
Register definitions for slave core: Shared TX Timestamping Unit (TXTSU)
* File : tstamp-regs.h
* Author : auto-generated by wbgen2 from tstamp-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tstamp-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_TSTAMP
#define __WBGEN2_REGDEFS_TSTAMP
#include <linux/types.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: TXTSU fifo not-empty in reg: Interrupt disable register */
#define TXTSU_EIC_IDR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: TXTSU fifo not-empty in reg: Interrupt enable register */
#define TXTSU_EIC_IER_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: TXTSU fifo not-empty in reg: Interrupt mask register */
#define TXTSU_EIC_IMR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: TXTSU fifo not-empty in reg: Interrupt status register */
#define TXTSU_EIC_ISR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 0 */
/* definitions for field: Rising edge timestamp in reg: FIFO 'Timestamp FIFO' data output register 0 */
#define TXTSU_TSF_R0_VAL_R_MASK WBGEN2_GEN_MASK(0, 28)
#define TXTSU_TSF_R0_VAL_R_SHIFT 0
#define TXTSU_TSF_R0_VAL_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define TXTSU_TSF_R0_VAL_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: Falling edge timestamp in reg: FIFO 'Timestamp FIFO' data output register 0 */
#define TXTSU_TSF_R0_VAL_F_MASK WBGEN2_GEN_MASK(28, 4)
#define TXTSU_TSF_R0_VAL_F_SHIFT 28
#define TXTSU_TSF_R0_VAL_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define TXTSU_TSF_R0_VAL_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 1 */
/* definitions for field: Physical port ID in reg: FIFO 'Timestamp FIFO' data output register 1 */
#define TXTSU_TSF_R1_PID_MASK WBGEN2_GEN_MASK(0, 5)
#define TXTSU_TSF_R1_PID_SHIFT 0
#define TXTSU_TSF_R1_PID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define TXTSU_TSF_R1_PID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Frame ID in reg: FIFO 'Timestamp FIFO' data output register 1 */
#define TXTSU_TSF_R1_FID_MASK WBGEN2_GEN_MASK(16, 16)
#define TXTSU_TSF_R1_FID_SHIFT 16
#define TXTSU_TSF_R1_FID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define TXTSU_TSF_R1_FID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: FIFO 'Timestamp FIFO' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Timestamp FIFO' control/status register */
#define TXTSU_TSF_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Timestamp FIFO' control/status register */
#define TXTSU_TSF_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Timestamp FIFO' control/status register */
#define TXTSU_TSF_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define TXTSU_TSF_CSR_USEDW_SHIFT 0
#define TXTSU_TSF_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define TXTSU_TSF_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
PACKED struct TXTSU_WB {
/* [0x0]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x4]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x8]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0xc]: REG Interrupt status register */
uint32_t EIC_ISR;
/* [0x10]: REG FIFO 'Timestamp FIFO' data output register 0 */
uint32_t TSF_R0;
/* [0x14]: REG FIFO 'Timestamp FIFO' data output register 1 */
uint32_t TSF_R1;
/* [0x18]: REG FIFO 'Timestamp FIFO' control/status register */
uint32_t TSF_CSR;
};
#endif
kernel/wbgen-regs/tstamp-regs.wb 0 → 100644
View file @ ca1c8911
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Shared TX Timestamping Unit (TXTSU)";
prefix="txtsu";
hdl_entity="wrsw_txtsu_wb";
-- TXTSU shared FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf";
name = "Timestamp FIFO";
description = "This FIFO holds the TX packet timestamps gathered from all switch endpoints. Each entry contains a single timestamp value consisting of 2 numbers:\
- VAL_R - the timestamp taken at rising clock edge. This is the main timestamp value\
- VAL_F - few LSBs of timestamp taken at falling clock edge. It's used in conjunction with VAL_R to determine if the timestamp has been taken\
properly (there was no metastability/setup/hold violation)\
Entries also contain information required to identify the endpoint and frame for which the timestamp was taken:\
- FID - Frame identifier assigned by the NIC\
- PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "Rising edge timestamp";
descritpion = "Timestamp value taken on rising clock edge (full word)";
prefix = "val_r";
type = SLV;
size = 28;
};
field {
name = "Falling edge timestamp";
description = "Timestamp value taken on falling clock edge (few LSBs)";
prefix = "val_f";
type = SLV;
size = 4;
};
field {
name ="Physical port ID";
description = "Identifier of the TXTSU port to which came the timestamp. There may be multiple timestamps sharing the same FID value for broadcast/multicast packets.";
prefix = "pid";
type = SLV;
size = 5;
align= 16;
};
field {
name = "Frame ID";
description = "OOB Frame Identifier. Used to associate the timestamp value with transmitted packet.";
prefix = "fid";
type = SLV;
size = 16;
align = 16;
};
};
-- TXTSU interrupts
irq {
name = "TXTSU fifo not-empty";
description = "Interrupt active when TXTSU shared FIFO contains any timestamps.";
prefix = "nempty";
trigger = LEVEL_0;
};
};
\ No newline at end of file
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