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White Rabbit Network Interface Card
Commit efa4401c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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update top level testbench to test Tx and Rx path of the WR-NIC

parent bfdaff40
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Showing with 709 additions and 132 deletions
sim/regs/dio_regs.vh 0 → 100644
View file @ efa4401c
`define ADDR_DIO_TRIG0 8'h0
`define DIO_TRIG0_SECONDS_OFFSET 0
`define DIO_TRIG0_SECONDS 32'hffffffff
`define ADDR_DIO_TRIGH0 8'h4
`define DIO_TRIGH0_SECONDS_OFFSET 0
`define DIO_TRIGH0_SECONDS 32'h000000ff
`define ADDR_DIO_CYC0 8'h8
`define DIO_CYC0_CYC_OFFSET 0
`define DIO_CYC0_CYC 32'h0fffffff
`define ADDR_DIO_TRIG1 8'hc
`define DIO_TRIG1_SECONDS_OFFSET 0
`define DIO_TRIG1_SECONDS 32'hffffffff
`define ADDR_DIO_TRIGH1 8'h10
`define DIO_TRIGH1_SECONDS_OFFSET 0
`define DIO_TRIGH1_SECONDS 32'h000000ff
`define ADDR_DIO_CYC1 8'h14
`define DIO_CYC1_CYC_OFFSET 0
`define DIO_CYC1_CYC 32'h0fffffff
`define ADDR_DIO_TRIG2 8'h18
`define DIO_TRIG2_SECONDS_OFFSET 0
`define DIO_TRIG2_SECONDS 32'hffffffff
`define ADDR_DIO_TRIGH2 8'h1c
`define DIO_TRIGH2_SECONDS_OFFSET 0
`define DIO_TRIGH2_SECONDS 32'h000000ff
`define ADDR_DIO_CYC2 8'h20
`define DIO_CYC2_CYC_OFFSET 0
`define DIO_CYC2_CYC 32'h0fffffff
`define ADDR_DIO_TRIG3 8'h24
`define DIO_TRIG3_SECONDS_OFFSET 0
`define DIO_TRIG3_SECONDS 32'hffffffff
`define ADDR_DIO_TRIGH3 8'h28
`define DIO_TRIGH3_SECONDS_OFFSET 0
`define DIO_TRIGH3_SECONDS 32'h000000ff
`define ADDR_DIO_CYC3 8'h2c
`define DIO_CYC3_CYC_OFFSET 0
`define DIO_CYC3_CYC 32'h0fffffff
`define ADDR_DIO_TRIG4 8'h30
`define DIO_TRIG4_SECONDS_OFFSET 0
`define DIO_TRIG4_SECONDS 32'hffffffff
`define ADDR_DIO_TRIGH4 8'h34
`define DIO_TRIGH4_SECONDS_OFFSET 0
`define DIO_TRIGH4_SECONDS 32'h000000ff
`define ADDR_DIO_CYC4 8'h38
`define DIO_CYC4_CYC_OFFSET 0
`define DIO_CYC4_CYC 32'h0fffffff
`define ADDR_DIO_OUT 8'h3c
`define DIO_OUT_MODE_OFFSET 0
`define DIO_OUT_MODE 32'h0000001f
`define ADDR_DIO_LATCH 8'h40
`define DIO_LATCH_TIME_CH0_OFFSET 0
`define DIO_LATCH_TIME_CH0 32'h00000001
`define DIO_LATCH_TIME_CH1_OFFSET 1
`define DIO_LATCH_TIME_CH1 32'h00000002
`define DIO_LATCH_TIME_CH2_OFFSET 2
`define DIO_LATCH_TIME_CH2 32'h00000004
`define DIO_LATCH_TIME_CH3_OFFSET 3
`define DIO_LATCH_TIME_CH3 32'h00000008
`define DIO_LATCH_TIME_CH4_OFFSET 4
`define DIO_LATCH_TIME_CH4 32'h00000010
`define ADDR_DIO_TRIG 8'h44
`define DIO_TRIG_RDY_OFFSET 0
`define DIO_TRIG_RDY 32'h0000001f
`define ADDR_DIO_PROG0_PULSE 8'h48
`define DIO_PROG0_PULSE_LENGTH_OFFSET 0
`define DIO_PROG0_PULSE_LENGTH 32'h0fffffff
`define ADDR_DIO_PROG1_PULSE 8'h4c
`define DIO_PROG1_PULSE_LENGTH_OFFSET 0
`define DIO_PROG1_PULSE_LENGTH 32'h0fffffff
`define ADDR_DIO_PROG2_PULSE 8'h50
`define DIO_PROG2_PULSE_LENGTH_OFFSET 0
`define DIO_PROG2_PULSE_LENGTH 32'h0fffffff
`define ADDR_DIO_PROG3_PULSE 8'h54
`define DIO_PROG3_PULSE_LENGTH_OFFSET 0
`define DIO_PROG3_PULSE_LENGTH 32'h0fffffff
`define ADDR_DIO_PROG4_PULSE 8'h58
`define DIO_PROG4_PULSE_LENGTH_OFFSET 0
`define DIO_PROG4_PULSE_LENGTH 32'h0fffffff
`define ADDR_DIO_PULSE 8'h5c
`define DIO_PULSE_IMM_0_OFFSET 0
`define DIO_PULSE_IMM_0 32'h00000001
`define DIO_PULSE_IMM_1_OFFSET 1
`define DIO_PULSE_IMM_1 32'h00000002
`define DIO_PULSE_IMM_2_OFFSET 2
`define DIO_PULSE_IMM_2 32'h00000004
`define DIO_PULSE_IMM_3_OFFSET 3
`define DIO_PULSE_IMM_3 32'h00000008
`define DIO_PULSE_IMM_4_OFFSET 4
`define DIO_PULSE_IMM_4 32'h00000010
`define ADDR_DIO_EIC_IDR 8'h60
`define DIO_EIC_IDR_NEMPTY_0_OFFSET 0
`define DIO_EIC_IDR_NEMPTY_0 32'h00000001
`define DIO_EIC_IDR_NEMPTY_1_OFFSET 1
`define DIO_EIC_IDR_NEMPTY_1 32'h00000002
`define DIO_EIC_IDR_NEMPTY_2_OFFSET 2
`define DIO_EIC_IDR_NEMPTY_2 32'h00000004
`define DIO_EIC_IDR_NEMPTY_3_OFFSET 3
`define DIO_EIC_IDR_NEMPTY_3 32'h00000008
`define DIO_EIC_IDR_NEMPTY_4_OFFSET 4
`define DIO_EIC_IDR_NEMPTY_4 32'h00000010
`define DIO_EIC_IDR_TRIGGER_READY_0_OFFSET 5
`define DIO_EIC_IDR_TRIGGER_READY_0 32'h00000020
`define DIO_EIC_IDR_TRIGGER_READY_1_OFFSET 6
`define DIO_EIC_IDR_TRIGGER_READY_1 32'h00000040
`define DIO_EIC_IDR_TRIGGER_READY_2_OFFSET 7
`define DIO_EIC_IDR_TRIGGER_READY_2 32'h00000080
`define DIO_EIC_IDR_TRIGGER_READY_3_OFFSET 8
`define DIO_EIC_IDR_TRIGGER_READY_3 32'h00000100
`define DIO_EIC_IDR_TRIGGER_READY_4_OFFSET 9
`define DIO_EIC_IDR_TRIGGER_READY_4 32'h00000200
`define ADDR_DIO_EIC_IER 8'h64
`define DIO_EIC_IER_NEMPTY_0_OFFSET 0
`define DIO_EIC_IER_NEMPTY_0 32'h00000001
`define DIO_EIC_IER_NEMPTY_1_OFFSET 1
`define DIO_EIC_IER_NEMPTY_1 32'h00000002
`define DIO_EIC_IER_NEMPTY_2_OFFSET 2
`define DIO_EIC_IER_NEMPTY_2 32'h00000004
`define DIO_EIC_IER_NEMPTY_3_OFFSET 3
`define DIO_EIC_IER_NEMPTY_3 32'h00000008
`define DIO_EIC_IER_NEMPTY_4_OFFSET 4
`define DIO_EIC_IER_NEMPTY_4 32'h00000010
`define DIO_EIC_IER_TRIGGER_READY_0_OFFSET 5
`define DIO_EIC_IER_TRIGGER_READY_0 32'h00000020
`define DIO_EIC_IER_TRIGGER_READY_1_OFFSET 6
`define DIO_EIC_IER_TRIGGER_READY_1 32'h00000040
`define DIO_EIC_IER_TRIGGER_READY_2_OFFSET 7
`define DIO_EIC_IER_TRIGGER_READY_2 32'h00000080
`define DIO_EIC_IER_TRIGGER_READY_3_OFFSET 8
`define DIO_EIC_IER_TRIGGER_READY_3 32'h00000100
`define DIO_EIC_IER_TRIGGER_READY_4_OFFSET 9
`define DIO_EIC_IER_TRIGGER_READY_4 32'h00000200
`define ADDR_DIO_EIC_IMR 8'h68
`define DIO_EIC_IMR_NEMPTY_0_OFFSET 0
`define DIO_EIC_IMR_NEMPTY_0 32'h00000001
`define DIO_EIC_IMR_NEMPTY_1_OFFSET 1
`define DIO_EIC_IMR_NEMPTY_1 32'h00000002
`define DIO_EIC_IMR_NEMPTY_2_OFFSET 2
`define DIO_EIC_IMR_NEMPTY_2 32'h00000004
`define DIO_EIC_IMR_NEMPTY_3_OFFSET 3
`define DIO_EIC_IMR_NEMPTY_3 32'h00000008
`define DIO_EIC_IMR_NEMPTY_4_OFFSET 4
`define DIO_EIC_IMR_NEMPTY_4 32'h00000010
`define DIO_EIC_IMR_TRIGGER_READY_0_OFFSET 5
`define DIO_EIC_IMR_TRIGGER_READY_0 32'h00000020
`define DIO_EIC_IMR_TRIGGER_READY_1_OFFSET 6
`define DIO_EIC_IMR_TRIGGER_READY_1 32'h00000040
`define DIO_EIC_IMR_TRIGGER_READY_2_OFFSET 7
`define DIO_EIC_IMR_TRIGGER_READY_2 32'h00000080
`define DIO_EIC_IMR_TRIGGER_READY_3_OFFSET 8
`define DIO_EIC_IMR_TRIGGER_READY_3 32'h00000100
`define DIO_EIC_IMR_TRIGGER_READY_4_OFFSET 9
`define DIO_EIC_IMR_TRIGGER_READY_4 32'h00000200
`define ADDR_DIO_EIC_ISR 8'h6c
`define DIO_EIC_ISR_NEMPTY_0_OFFSET 0
`define DIO_EIC_ISR_NEMPTY_0 32'h00000001
`define DIO_EIC_ISR_NEMPTY_1_OFFSET 1
`define DIO_EIC_ISR_NEMPTY_1 32'h00000002
`define DIO_EIC_ISR_NEMPTY_2_OFFSET 2
`define DIO_EIC_ISR_NEMPTY_2 32'h00000004
`define DIO_EIC_ISR_NEMPTY_3_OFFSET 3
`define DIO_EIC_ISR_NEMPTY_3 32'h00000008
`define DIO_EIC_ISR_NEMPTY_4_OFFSET 4
`define DIO_EIC_ISR_NEMPTY_4 32'h00000010
`define DIO_EIC_ISR_TRIGGER_READY_0_OFFSET 5
`define DIO_EIC_ISR_TRIGGER_READY_0 32'h00000020
`define DIO_EIC_ISR_TRIGGER_READY_1_OFFSET 6
`define DIO_EIC_ISR_TRIGGER_READY_1 32'h00000040
`define DIO_EIC_ISR_TRIGGER_READY_2_OFFSET 7
`define DIO_EIC_ISR_TRIGGER_READY_2 32'h00000080
`define DIO_EIC_ISR_TRIGGER_READY_3_OFFSET 8
`define DIO_EIC_ISR_TRIGGER_READY_3 32'h00000100
`define DIO_EIC_ISR_TRIGGER_READY_4_OFFSET 9
`define DIO_EIC_ISR_TRIGGER_READY_4 32'h00000200
`define ADDR_DIO_TSF0_R0 8'h70
`define DIO_TSF0_R0_TAG_SECONDS_OFFSET 0
`define DIO_TSF0_R0_TAG_SECONDS 32'hffffffff
`define ADDR_DIO_TSF0_R1 8'h74
`define DIO_TSF0_R1_TAG_SECONDSH_OFFSET 0
`define DIO_TSF0_R1_TAG_SECONDSH 32'h000000ff
`define ADDR_DIO_TSF0_R2 8'h78
`define DIO_TSF0_R2_TAG_CYCLES_OFFSET 0
`define DIO_TSF0_R2_TAG_CYCLES 32'h0fffffff
`define ADDR_DIO_TSF0_CSR 8'h7c
`define DIO_TSF0_CSR_FULL_OFFSET 16
`define DIO_TSF0_CSR_FULL 32'h00010000
`define DIO_TSF0_CSR_EMPTY_OFFSET 17
`define DIO_TSF0_CSR_EMPTY 32'h00020000
`define DIO_TSF0_CSR_USEDW_OFFSET 0
`define DIO_TSF0_CSR_USEDW 32'h000000ff
`define ADDR_DIO_TSF1_R0 8'h80
`define DIO_TSF1_R0_TAG_SECONDS_OFFSET 0
`define DIO_TSF1_R0_TAG_SECONDS 32'hffffffff
`define ADDR_DIO_TSF1_R1 8'h84
`define DIO_TSF1_R1_TAG_SECONDSH_OFFSET 0
`define DIO_TSF1_R1_TAG_SECONDSH 32'h000000ff
`define ADDR_DIO_TSF1_R2 8'h88
`define DIO_TSF1_R2_TAG_CYCLES_OFFSET 0
`define DIO_TSF1_R2_TAG_CYCLES 32'h0fffffff
`define ADDR_DIO_TSF1_CSR 8'h8c
`define DIO_TSF1_CSR_FULL_OFFSET 16
`define DIO_TSF1_CSR_FULL 32'h00010000
`define DIO_TSF1_CSR_EMPTY_OFFSET 17
`define DIO_TSF1_CSR_EMPTY 32'h00020000
`define DIO_TSF1_CSR_USEDW_OFFSET 0
`define DIO_TSF1_CSR_USEDW 32'h000000ff
`define ADDR_DIO_TSF2_R0 8'h90
`define DIO_TSF2_R0_TAG_SECONDS_OFFSET 0
`define DIO_TSF2_R0_TAG_SECONDS 32'hffffffff
`define ADDR_DIO_TSF2_R1 8'h94
`define DIO_TSF2_R1_TAG_SECONDSH_OFFSET 0
`define DIO_TSF2_R1_TAG_SECONDSH 32'h000000ff
`define ADDR_DIO_TSF2_R2 8'h98
`define DIO_TSF2_R2_TAG_CYCLES_OFFSET 0
`define DIO_TSF2_R2_TAG_CYCLES 32'h0fffffff
`define ADDR_DIO_TSF2_CSR 8'h9c
`define DIO_TSF2_CSR_FULL_OFFSET 16
`define DIO_TSF2_CSR_FULL 32'h00010000
`define DIO_TSF2_CSR_EMPTY_OFFSET 17
`define DIO_TSF2_CSR_EMPTY 32'h00020000
`define DIO_TSF2_CSR_USEDW_OFFSET 0
`define DIO_TSF2_CSR_USEDW 32'h000000ff
`define ADDR_DIO_TSF3_R0 8'ha0
`define DIO_TSF3_R0_TAG_SECONDS_OFFSET 0
`define DIO_TSF3_R0_TAG_SECONDS 32'hffffffff
`define ADDR_DIO_TSF3_R1 8'ha4
`define DIO_TSF3_R1_TAG_SECONDSH_OFFSET 0
`define DIO_TSF3_R1_TAG_SECONDSH 32'h000000ff
`define ADDR_DIO_TSF3_R2 8'ha8
`define DIO_TSF3_R2_TAG_CYCLES_OFFSET 0
`define DIO_TSF3_R2_TAG_CYCLES 32'h0fffffff
`define ADDR_DIO_TSF3_CSR 8'hac
`define DIO_TSF3_CSR_FULL_OFFSET 16
`define DIO_TSF3_CSR_FULL 32'h00010000
`define DIO_TSF3_CSR_EMPTY_OFFSET 17
`define DIO_TSF3_CSR_EMPTY 32'h00020000
`define DIO_TSF3_CSR_USEDW_OFFSET 0
`define DIO_TSF3_CSR_USEDW 32'h000000ff
`define ADDR_DIO_TSF4_R0 8'hb0
`define DIO_TSF4_R0_TAG_SECONDS_OFFSET 0
`define DIO_TSF4_R0_TAG_SECONDS 32'hffffffff
`define ADDR_DIO_TSF4_R1 8'hb4
`define DIO_TSF4_R1_TAG_SECONDSH_OFFSET 0
`define DIO_TSF4_R1_TAG_SECONDSH 32'h000000ff
`define ADDR_DIO_TSF4_R2 8'hb8
`define DIO_TSF4_R2_TAG_CYCLES_OFFSET 0
`define DIO_TSF4_R2_TAG_CYCLES 32'h0fffffff
`define ADDR_DIO_TSF4_CSR 8'hbc
`define DIO_TSF4_CSR_FULL_OFFSET 16
`define DIO_TSF4_CSR_FULL 32'h00010000
`define DIO_TSF4_CSR_EMPTY_OFFSET 17
`define DIO_TSF4_CSR_EMPTY 32'h00020000
`define DIO_TSF4_CSR_USEDW_OFFSET 0
`define DIO_TSF4_CSR_USEDW 32'h000000ff
sim/regs/vic_regs.vh 0 → 100644
View file @ efa4401c
`define ADDR_VIC_CTL 8'h0
`define VIC_CTL_ENABLE_OFFSET 0
`define VIC_CTL_ENABLE 32'h00000001
`define VIC_CTL_POL_OFFSET 1
`define VIC_CTL_POL 32'h00000002
`define VIC_CTL_EMU_EDGE_OFFSET 2
`define VIC_CTL_EMU_EDGE 32'h00000004
`define VIC_CTL_EMU_LEN_OFFSET 3
`define VIC_CTL_EMU_LEN 32'h0007fff8
`define ADDR_VIC_RISR 8'h4
`define ADDR_VIC_IER 8'h8
`define ADDR_VIC_IDR 8'hc
`define ADDR_VIC_IMR 8'h10
`define ADDR_VIC_VAR 8'h14
`define ADDR_VIC_SWIR 8'h18
`define ADDR_VIC_EOIR 8'h1c
`define BASE_VIC_IVT_RAM 8'h80
`define SIZE_VIC_IVT_RAM 32'h20
testbench/top_level/Manifest.py
View file @ efa4401c
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
vlog_opt="+incdir+../../sim +incdir+gn4124_bfm +incdir+../../sim/wr-hdl +incdir+../../sim/regs"
files = [ "main.sv" ]
......
testbench/top_level/main.sv
View file @ efa4401c
......@@ -3,16 +3,18 @@
`include "gn4124_bfm.svh"
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
`include "drivers/simdrv_wrsw_nic.svh"
`include "wb_packet_source.svh"
`include "wb_packet_sink.svh"
`include "endpoint_phy_wrapper.svh"
`include "nic_regs.vh"
`include "vic_regs.vh"
`include "dio_regs.vh"
`include "endpoint_regs.v"
`include "endpoint_mdio.v"
`include "regs/dio_regs.vh"
`include "regs/vic_regs.vh"
`include "endpoint_phy_wrapper.svh"
const uint64_t BASE_WRPC = 'h0080000;
const uint64_t BASE_EP = 'h00a0100;
const uint64_t BASE_NIC = 'h00c0000;
const uint64_t BASE_VIC = 'h00e0000;
const uint64_t BASE_TXTSU ='h00e1000;
......@@ -21,23 +23,53 @@ const uint64_t BASE_DIO = 'h00e2300;
module main;
reg clk_125m_pllref = 0;
reg clk_20m_vcxo = 0;
reg clk_sys = 0;
// reg clk_sys = 0;
reg rst_n = 0;
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
always #8ns clk_sys <= ~clk_sys;
// always #8ns clk_sys <= ~clk_sys;
always #20ns clk_20m_vcxo <= ~clk_20m_vcxo;
initial #200ns rst_n = 1;
IGN4124PCIMaster I_Gennum ();
reg [4:0] dio_in = 0;
wr_nic_sdb_top
#(
.g_simulation(1))
DUT (
.clk_125m_pllref_p_i(clk_125m_pllref),
.clk_125m_pllref_n_i(~clk_125m_pllref),
. fpga_pll_ref_clk_101_p_i(clk_125m_pllref),
. fpga_pll_ref_clk_101_n_i(~clk_125m_pllref),
.clk_20m_vcxo_i(clk_20m_vcxo),
`GENNUM_WIRE_SPEC_PINS(I_Gennum),
.sfp_txp_o(txp),
.sfp_txn_o(txn),
.sfp_rxp_i(rxp),
.sfp_rxn_i(rxn),
.dio_n_i(~dio_in),
.dio_p_i(dio_in)
);
IWishboneMaster
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_source
(
.clk_i(clk_sys),
.clk_i(DUT.clk_sys),
.rst_n_i(rst_n)
);
......@@ -47,7 +79,7 @@ module main;
.g_addr_width(2))
U_wrf_sink
(
.clk_i(clk_sys),
.clk_i(DUT.clk_sys),
.rst_n_i(rst_n)
);
......@@ -58,18 +90,18 @@ module main;
.g_addr_width(7))
U_sys_bus_master
(
.clk_i(clk_sys),
.clk_i(DUT.clk_sys),
.rst_n_i(rst_n)
);
/* -----\/----- EXCLUDED -----\/-----
/* -----\/----- EXCLUDED -----\/-----*/
endpoint_phy_wrapper
#(
.g_phy_type("GTP"))
U_Wrapped_EP_GTP
(
.clk_sys_i(clk_sys),
.clk_sys_i(DUT.clk_sys),
.clk_ref_i(clk_125m_pllref),
.clk_rx_i(clk_125m_pllref),
.rst_n_i(rst_n),
......@@ -84,102 +116,93 @@ module main;
.rxn_i(txn),
.rxp_i(txp)
);
-----/\----- EXCLUDED -----/\----- */
IGN4124PCIMaster I_Gennum ();
reg [4:0] dio_in = 0;
wr_nic_sdb_top
DUT (
.clk_125m_pllref_p_i(clk_125m_pllref),
.clk_125m_pllref_n_i(~clk_125m_pllref),
. fpga_pll_ref_clk_101_p_i(clk_125m_pllref),
. fpga_pll_ref_clk_101_n_i(~clk_125m_pllref),
.clk_20m_vcxo_i(clk_20m_vcxo),
`GENNUM_WIRE_SPEC_PINS(I_Gennum),
.sfp_txp_o(txp),
.sfp_txn_o(txn),
.sfp_rxp_i(rxp),
.sfp_rxn_i(rxn),
.dio_n_i(~dio_in),
.dio_p_i(dio_in)
);
task automatic tx_test(int n_tries, int is_q, int unvid, EthPacketSource src, EthPacketSink sink);
EthPacketGenerator gen = new;
EthPacket pkt, tmpl, pkt2;
EthPacket arr[];
int i;
arr = new[n_tries](arr);
tmpl = new;
tmpl.src = '{1,2,3,4,5,6};
tmpl.dst = '{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe};
tmpl.has_smac = 1;
tmpl.is_q = is_q;
tmpl.vid = 100;
tmpl.ethertype = 'h88f7;
//
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD /* | EthPacketGenerator::TX_OOB*/) ;
gen.set_template(tmpl);
gen.set_size(64,64);
for(i=0;i<n_tries;i++)
begin
pkt = gen.gen();
// $display("Tx %d", i);
// pkt.dump();
src.send(pkt);
// $display("Send: %d [dsize %d]", i+1,pkt.payload.size() + 14);
arr[i] = pkt;
end
for(i=0;i<n_tries;i++)
begin
sink.recv(pkt2);
// $display("rx %d", i);
if(unvid)
arr[i].is_q = 0;
if(!arr[i].equal(pkt2))
begin
$display("Fault at %d", i);
arr[i].dump();
pkt2.dump();
$stop;
end
end // for (i=0;i<n_tries;i++)
endtask // tx_test
task send_random(WBPacketSource src);
/* -----/\----- EXCLUDED -----/\----- */
// task automatic tx_test(int n_tries, int is_q, int unvid, EthPacketSource src, EthPacketSink sink);
// EthPacketGenerator gen = new;
// EthPacket pkt, tmpl, pkt2;
// EthPacket arr[];
// int i;
//
// arr = new[n_tries](arr);
//
//
// tmpl = new;
// tmpl.src = '{1,2,3,4,5,6};
// tmpl.dst = '{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe};
// tmpl.has_smac = 1;
// tmpl.is_q = is_q;
// tmpl.vid = 100;
// tmpl.ethertype = 'h88f7;
// //
// gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD /* | EthPacketGenerator::TX_OOB*/) ;
// gen.set_template(tmpl);
// gen.set_size(64,64);
//
// for(i=0;i<n_tries;i++)
// begin
// pkt = gen.gen();
// // $display("Tx %d", i);
// // pkt.dump();
// src.send(pkt);
// // $display("Send: %d [dsize %d]", i+1,pkt.payload.size() + 14);
//
// arr[i] = pkt;
// end
//
// for(i=0;i<n_tries;i++)
// begin
// sink.recv(pkt2);
//// $display("rx %d", i);
//
// if(unvid)
// arr[i].is_q = 0;
//
// if(!arr[i].equal(pkt2))
// begin
// $display("Fault at %d", i);
//
// arr[i].dump();
// pkt2.dump();
// $stop;
// end
// end // for (i=0;i<n_tries;i++)
//
// endtask // tx_test
task send_random(WBPacketSource src, int t);
EthPacketGenerator gen = new;
EthPacket pkt, tmpl;
tmpl = new;
tmpl.src = '{1,2,3,4,5,6};
tmpl.dst = '{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe};
if(t==0) begin
tmpl.dst = '{'h01, 'h1b, 'h19, 'h00, 'h00, 'h00};
tmpl.ethertype = 'h88f7;
end;
if(t==1) begin
tmpl.dst = '{'hff, 'hff, 'hff, 'hff, 'hff, 'hff};
tmpl.ethertype = 'hdbff;
end;
if(t==2) begin
tmpl.dst = '{'hff, 'hff, 'hff, 'hff, 'hff, 'hff};
tmpl.ethertype = 'h0800;
end;
tmpl.src = '{'h3c,'h97,'h0e, 'h7a, 'ha3, 'h79};
//tmpl.dst = '{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe};
tmpl.has_smac = 1;
tmpl.vid = 100;
tmpl.ethertype = 'h88f7;
//tmpl.ethertype = 'h0806;
//tmpl.payload = '{'h00, 'h01, 'h08, 'h00, 'h06, 'h04, 'h00, 'h01, 'h3c,
//'h97, 'h0e, 'h7a, 'ha3, 'h79, 'hc0, 'ha8, 'h05, 'h01, 'h00, 'h00, 'h00,
//'h00, 'h00, 'h00, 'hc0, 'ha8, 'h05, 'h02};
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD /* | EthPacketGenerator::TX_OOB*/) ;
//gen.set_randomization(0);
gen.set_template(tmpl);
gen.set_size(64,64);
......@@ -207,18 +230,31 @@ module main;
WBPacketSource src = new(U_wrf_source.get_accessor());
WBPacketSink sink = new(U_wrf_sink.get_accessor());
// CSimDrv_WR_Endpoint ep_drv;
EthPacket pkt;
// EthPacket pkt;
CBusAccessor acc ;
int i;
acc = I_Gennum.get_accessor();
acc.set_default_xfer_size(4);
$display("GnPreReady\n");
@(posedge I_Gennum.ready);
$display("GnReady\n");
#5us;
//acc.write('h20510, 'ha5);
// acc.write(BASE_EP + `ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN);
// acc.write(BASE_EP + `ADDR_EP_RFCR, 1518 << `EP_RFCR_MRU_OFFSET);
// acc.write(BASE_EP + `ADDR_EP_VCR0, 3 << `EP_VCR0_QMODE_OFFSET);
// acc.write(BASE_EP + `ADDR_EP_TSCR, `EP_TSCR_EN_RXTS);
$display(BASE_NIC + `ADDR_NIC_CR);
$display(`NIC_CR_RX_EN | `NIC_CR_TX_EN);
acc.write(BASE_NIC + `ADDR_NIC_CR, `NIC_CR_RX_EN | `NIC_CR_TX_EN);
acc.write(BASE_NIC + `ADDR_NIC_EIC_IER, 'h7);
acc.write(BASE_NIC + `BASE_NIC_DRX + 8, (1000) << 16);
......@@ -231,42 +267,41 @@ module main;
acc.write(BASE_VIC + `ADDR_VIC_EOIR, 'h1);
#1us;
#5us;
$stop;
//$stop;
#150us;
$display("ConfigDIO");
acc.write(BASE_DIO + `ADDR_DIO_TRIG0, 0);
acc.write(BASE_DIO + `ADDR_DIO_TRIGH0, 0);
acc.write(BASE_DIO + `ADDR_DIO_CYC0, 'h3000);
acc.write(BASE_DIO + `ADDR_DIO_OUT, 'h01);
acc.write(BASE_DIO + `ADDR_DIO_PROG0_PULSE, 'h10);
acc.write(BASE_DIO + `ADDR_DIO_LATCH, 'h1);
acc.write(BASE_DIO + `ADDR_DIO_EIC_IER, 'hff);
#100us;
dio_in[0] = 1'b1;
#100ns;
dio_in[0] = 1'b0;
// #150us;
//
// $display("ConfigDIO");
//
//
// acc.write(BASE_DIO + `ADDR_DIO_TRIG0, 0);
// acc.write(BASE_DIO + `ADDR_DIO_TRIGH0, 0);
// acc.write(BASE_DIO + `ADDR_DIO_CYC0, 'h3000);
// acc.write(BASE_DIO + `ADDR_DIO_OUT, 'h01);
// acc.write(BASE_DIO + `ADDR_DIO_PROG0_PULSE, 'h10);
// acc.write(BASE_DIO + `ADDR_DIO_LATCH, 'h1);
// acc.write(BASE_DIO + `ADDR_DIO_EIC_IER, 'hff);
//
// #100us;
// dio_in[0] = 1'b1;
// #100ns;
// dio_in[0] = 1'b0;
//
//
// @(posedge rst_n);
@(posedge clk_sys);
@(posedge DUT.clk_sys);
$display("EPInit!\n");
sys_bus = U_sys_bus_master.get_accessor();
sys_bus.set_mode(CLASSIC);
sys_bus.write(`ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN);
sys_bus.write(`ADDR_EP_RFCR, 1518 << `EP_RFCR_MRU_OFFSET);
......@@ -276,12 +311,96 @@ module main;
#700us;
#300us;
// TEST RX PATH
forever begin
send_random(src);
#1us;
uint64_t ret;
send_random(src, 0);
#10us;
send_random(src, 1);
#5us;
acc.read(BASE_NIC + `BASE_NIC_DRX, ret);
acc.read(BASE_NIC + `BASE_NIC_DRX + 4, ret);
acc.read(BASE_NIC + `BASE_NIC_DRX + 8, ret);
#5us;
send_random(src, 2);
#10us;
end
// TEST TX PATH (quick and messy, we need nice code here)
// forever begin
// acc.write(BASE_NIC + 'h8000, 'hffffffff);
// acc.write(BASE_NIC + 'h8004, 'hffff3c97);
// acc.write(BASE_NIC + 'h8008, 'h0e7aa379);
// acc.write(BASE_NIC + 'h800c, 'hdbff0001);
// acc.write(BASE_NIC + 'h8010, 'h02030405);
// acc.write(BASE_NIC + 'h8014, 'h06070809);
// acc.write(BASE_NIC + 'h8018, 'h0a0b0c0d);
// acc.write(BASE_NIC + 'h801c, 'h0e0f1011);
// acc.write(BASE_NIC + 'h8020, 'h12131415);
// acc.write(BASE_NIC + 'h8024, 'h16171819);
// acc.write(BASE_NIC + 'h8028, 'h1a1b1c1d);
// acc.write(BASE_NIC + 'h802c, 'h1e1f2021);
// acc.write(BASE_NIC + 'h8030, 'h22232425);
// acc.write(BASE_NIC + 'h8034, 'h26272829);
// acc.write(BASE_NIC + 'h8038, 'h2a2b2c2d);
// acc.write(BASE_NIC + 'h803c, 'h2e2f3031);
// acc.write(BASE_NIC + 'h8040, 'h32333435);
// acc.write(BASE_NIC + 'h8044, 'h36373839);
// acc.write(BASE_NIC + 'h8048, 'h3a3b3c3d);
// acc.write(BASE_NIC + 'h804c, 'h3e3f4041);
//
// ///////////////////////////////////////////////////////
// acc.write(BASE_NIC + `BASE_NIC_DTX+4, 'h00400000);
// acc.write(BASE_NIC + `BASE_NIC_DTX+8, 'h1);
// acc.write(BASE_NIC + `BASE_NIC_DTX, 'h12340001);
// #2us;
// //acc.write(BASE_NIC + `ADDR_NIC_SR, 'h4);
// //acc.write(BASE_NIC + `ADDR_NIC_EIC_ISR, 'h2);
// #8us;
// ///////////////////////////////////////////////////////
// acc.write(BASE_NIC + `BASE_NIC_DTX+14, 'h00400000);
// acc.write(BASE_NIC + `BASE_NIC_DTX+18, 'h1);
// acc.write(BASE_NIC + `BASE_NIC_DTX+10, 'h12340001);
// #2us;
// //acc.write(BASE_NIC + `ADDR_NIC_SR, 'h4);
// //acc.write(BASE_NIC + `ADDR_NIC_EIC_ISR, 'h2);
// #8us;
// ///////////////////////////////////////////////////////
// acc.write(BASE_NIC + `BASE_NIC_DTX+24, 'h00400000);
// acc.write(BASE_NIC + `BASE_NIC_DTX+28, 'h1);
// acc.write(BASE_NIC + `BASE_NIC_DTX+20, 'h12340001);
// #2us;
// //acc.write(BASE_NIC + `ADDR_NIC_SR, 'h4);
// //acc.write(BASE_NIC + `ADDR_NIC_EIC_ISR, 'h2);
// #8us;
// ///////////////////////////////////////////////////////
// acc.write(BASE_NIC + `BASE_NIC_DTX+34, 'h00400000);
// acc.write(BASE_NIC + `BASE_NIC_DTX+38, 'h1);
// acc.write(BASE_NIC + `BASE_NIC_DTX+30, 'h12340001);
// #2us;
// //acc.write(BASE_NIC + `ADDR_NIC_SR, 'h4);
// //acc.write(BASE_NIC + `ADDR_NIC_EIC_ISR, 'h2);
// #8us;
// ///////////////////////////////////////////////////////
// acc.write(BASE_NIC + `BASE_NIC_DTX+44, 'h00400000);
// acc.write(BASE_NIC + `BASE_NIC_DTX+48, 'h1);
// acc.write(BASE_NIC + `BASE_NIC_DTX+40, 'h12340001);
// #2us;
// //acc.write(BASE_NIC + `ADDR_NIC_SR, 'h4);
// //acc.write(BASE_NIC + `ADDR_NIC_EIC_ISR, 'h2);
// #8us;
// ///////////////////////////////////////////////////////
// acc.write(BASE_NIC + `BASE_NIC_DTX+54, 'h00400000);
// acc.write(BASE_NIC + `BASE_NIC_DTX+58, 'h1);
// acc.write(BASE_NIC + `BASE_NIC_DTX+50, 'h12340001);
// #2us;
// //acc.write(BASE_NIC + `ADDR_NIC_SR, 'h4);
// //acc.write(BASE_NIC + `ADDR_NIC_EIC_ISR, 'h2);
// #8us;
// end
end
......
testbench/top_level/run.do
View file @ efa4401c
vlog -sv main.sv +incdir+"." +incdir+gn4124_bfm +incdir+../../sim
vlog -sv main.sv +incdir+"." +incdir+gn4124_bfm +incdir+../../sim +incdir+../../sim/wr-hdl +incdir+../../sim/regs
#make -f Makefile
vsim -t 10fs -L secureip -L unisim work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
do wave_nic_rx.do
radix -hexadecimal
run 25us
run 500us
wave zoomfull
radix -hexadecimal
testbench/top_level/wave_nic_rx.do 0 → 100644
View file @ efa4401c
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/U_wrf_source/clk_i
add wave -noupdate /main/U_wrf_source/rst_n_i
add wave -noupdate -expand -group EP_STIM /main/U_wrf_source/adr
add wave -noupdate -expand -group EP_STIM /main/U_wrf_source/dat_o
add wave -noupdate -expand -group EP_STIM /main/U_wrf_source/ack
add wave -noupdate -expand -group EP_STIM /main/U_wrf_source/stall
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_k
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_err
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_comma
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_epd
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_spd
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_extend
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_idle
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_lcr
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_sfd_char
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_preamble_char
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_data
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_even
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_cal
add wave -noupdate /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/rxpcs_fab_o
add wave -noupdate -expand -group pfilter /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass
add wave -noupdate -expand -group pfilter /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop
add wave -noupdate -expand -group pfilter /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_rd
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_valid
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_drop
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_hp
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_pause
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_full
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d0
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d1
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_class
add wave -noupdate -group RX_PATH -expand -subitemconfig {/main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe(8) -expand} /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/fab_pipe
add wave -noupdate -group RX_PATH -expand /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/dreq_pipe
add wave -noupdate -group WRF_MUX -height 16 /main/DUT/U_WR_CORE/WRPC/U_WBP_Mux/demux
add wave -noupdate -group WRF_MUX /main/DUT/U_WR_CORE/WRPC/U_WBP_Mux/dmux_sel
add wave -noupdate -group EP_FABRIC -expand /main/DUT/U_WR_CORE/WRPC/U_Endpoint/src_o
add wave -noupdate -group EP_FABRIC /main/DUT/U_WR_CORE/WRPC/U_Endpoint/src_i
add wave -noupdate -expand -group EXT_FABRIC -expand /main/DUT/U_WR_CORE/wrf_src_o
add wave -noupdate -expand -group EXT_FABRIC /main/DUT/U_WR_CORE/wrf_src_i
add wave -noupdate -group MINIC_FABRIC /main/DUT/U_WR_CORE/WRPC/MINI_NIC/snk_o
add wave -noupdate -group MINIC_FABRIC -expand /main/DUT/U_WR_CORE/WRPC/MINI_NIC/snk_i
add wave -noupdate -expand -group NIC -height 16 /main/DUT/U_NIC/U_RX_FSM/state
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/rxdesc_request_next
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/rxdesc_grant
add wave -noupdate -expand -group NIC -expand /main/DUT/U_NIC/rxdesc_current
add wave -noupdate -expand -group NIC -expand /main/DUT/U_NIC/rxdesc_new
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/rxdesc_write
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/rxdesc_write_done
add wave -noupdate -expand -group NIC -height 16 /main/DUT/U_NIC/U_RX_DESC_MANAGER/state
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/nic_drx_addr
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/nic_drx_wr_data
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/nic_drx_rd
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/nic_drx_rd_data
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/nic_drx_wr
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(0)
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(1)
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(2)
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(3)
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(4)
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(5)
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(6)
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(7)
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(8)
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(9)
add wave -noupdate -expand -group NIC -expand -group RXD_RAM /main/DUT/U_NIC/U_WB_SLAVE/nic_drx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(10)
add wave -noupdate -expand -group NIC -expand /main/DUT/U_NIC/U_RX_DESC_MANAGER/granted_desc_rx
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_BUFFER/addr_i
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_BUFFER/data_i
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_BUFFER/wr_i
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_BUFFER/data_o
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_RX_FSM/rx_rdreg_toggle
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_RX_FSM/fab_in.data
add wave -noupdate -expand -group nic_buffer -height 16 /main/DUT/U_NIC/U_RX_FSM/state
add wave -noupdate -expand -group CBAR /main/DUT/cbar_slave_i
add wave -noupdate -expand -group CBAR /main/DUT/cbar_slave_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {379266620970 fs} 0} {{Cursor 2} {313309014010 fs} 0}
configure wave -namecolwidth 207
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {525 us}
testbench/top_level/wave_nic_tx.do 0 → 100644
View file @ efa4401c
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/U_wrf_source/clk_i
add wave -noupdate /main/U_wrf_source/rst_n_i
add wave -noupdate -expand -group EP_STIM /main/U_wrf_source/adr
add wave -noupdate -expand -group EP_STIM /main/U_wrf_source/dat_o
add wave -noupdate -expand -group EP_STIM /main/U_wrf_source/ack
add wave -noupdate -expand -group EP_STIM /main/U_wrf_source/stall
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_k
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_err
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_comma
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_epd
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_spd
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_extend
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_idle
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_lcr
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_sfd_char
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_preamble_char
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_data
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_even
add wave -noupdate -group RX_PCS /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_RX_PCS/d_is_cal
add wave -noupdate /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/rxpcs_fab_o
add wave -noupdate -expand -group pfilter /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pfilter_pclass
add wave -noupdate -expand -group pfilter /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pfilter_drop
add wave -noupdate -expand -group pfilter /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/pfilter_done
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_rd
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_valid
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_drop
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_hp
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_is_pause
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_full
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d0
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_we_d1
add wave -noupdate -group mbuf /main/DUT/U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/mbuf_pf_class
add wave -noupdate -group WRF_MUX -height 16 /main/DUT/U_WR_CORE/WRPC/U_WBP_Mux/demux
add wave -noupdate -group WRF_MUX /main/DUT/U_WR_CORE/WRPC/U_WBP_Mux/dmux_sel
add wave -noupdate -expand -group EP_FABRIC -expand /main/DUT/U_WR_CORE/WRPC/U_Endpoint/snk_i
add wave -noupdate -expand -group EP_FABRIC -expand /main/DUT/U_WR_CORE/WRPC/U_Endpoint/snk_o
add wave -noupdate -expand -group EXT_FABRIC -expand /main/DUT/U_WR_CORE/wrf_snk_i
add wave -noupdate -expand -group EXT_FABRIC -expand /main/DUT/U_WR_CORE/wrf_snk_o
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/nic_dtx_addr
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/nic_dtx_wr_data
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/nic_dtx_rd
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/nic_dtx_rd_data
add wave -noupdate -expand -group NIC /main/DUT/U_NIC/nic_dtx_wr
add wave -noupdate -expand -group NIC_TXFSM -height 16 /main/DUT/U_NIC/U_TX_FSM/state
add wave -noupdate /main/DUT/U_NIC/U_TX_FSM/txdesc_request_next_o
add wave -noupdate /main/DUT/U_NIC/U_TX_FSM/txdesc_grant_i
add wave -noupdate /main/DUT/U_NIC/U_TX_FSM/txdesc_current_i
add wave -noupdate /main/DUT/U_NIC/U_TX_FSM/txdesc_new_o
add wave -noupdate /main/DUT/U_NIC/U_TX_FSM/txdesc_write_o
add wave -noupdate /main/DUT/U_NIC/U_TX_FSM/txdesc_write_done_i
add wave -noupdate -expand -group TXD -height 16 /main/DUT/U_NIC/U_TX_DESC_MANAGER/state
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_TX_DESC_MANAGER/granted_desc_tx
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(0)
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(1)
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(2)
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(3)
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(4)
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(5)
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(6)
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(7)
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(8)
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(9)
add wave -noupdate -expand -group TXD /main/DUT/U_NIC/U_WB_SLAVE/nic_dtx_raminst/wrapped_dpram/gen_single_clk/U_RAM_SC/ram(10)
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_BUFFER/addr_i
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_BUFFER/data_i
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_BUFFER/wr_i
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_BUFFER/data_o
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_RX_FSM/rx_rdreg_toggle
add wave -noupdate -expand -group nic_buffer /main/DUT/U_NIC/U_RX_FSM/fab_in.data
add wave -noupdate -expand -group nic_buffer -height 16 /main/DUT/U_NIC/U_RX_FSM/state
add wave -noupdate -expand -group CBAR /main/DUT/cbar_slave_i
add wave -noupdate -expand -group CBAR /main/DUT/cbar_slave_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {379266620970 fs} 0} {{Cursor 2} {313309014010 fs} 0}
configure wave -namecolwidth 413
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {187474297460 fs}
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