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f440fba2
Commit
f440fba2
authored
Jul 23, 2014
by
Grzegorz Daniluk
Committed by
Miguel Jimenez Lopez
Sep 04, 2019
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softpll: update header file to follow latest changes in ext SPLL
parent
7e8070eb
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2 changed files
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263 additions
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199 deletions
+263
-199
softpll-regs.h
kernel/wbgen-regs/softpll-regs.h
+113
-91
softpll-regs.wb
kernel/wbgen-regs/softpll-regs.wb
+150
-108
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kernel/wbgen-regs/softpll-regs.h
View file @
f440fba2
/*
Register definitions for slave core: WR Softcore PLL
* File : softpll-regs.h
* Author : auto-generated by wbgen2 from softpll-regs.wb
* File : softpll_regs.h
* Author : auto-generated by wbgen2 from spll_wb_slave.wb
* Created : Mon Jul 21 13:49:11 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE s
oftpll-regs
.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE s
pll_wb_slave
.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_SOFTPLL
#define __WBGEN2_REGDEFS_SOFTPLL
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#ifndef __WBGEN2_REGDEFS_SPLL_WB_SLAVE_WB
#define __WBGEN2_REGDEFS_SPLL_WB_SLAVE_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
...
...
@@ -37,88 +33,106 @@
/* definitions for register: SPLL Control/Status Register */
/* definitions for field:
Period detector reference select
in reg: SPLL Control/Status Register */
#define SPLL_CSR_
PER_SEL_MASK WBGEN2_GEN_MASK(0
, 6)
#define SPLL_CSR_
PER_SEL_SHIFT 0
#define SPLL_CSR_
PER_SEL_W(value) WBGEN2_GEN_WRITE(value, 0
, 6)
#define SPLL_CSR_
PER_SEL_R(reg) WBGEN2_GEN_READ(reg, 0
, 6)
/* definitions for field:
Unused (kept for software compatibility).
in reg: SPLL Control/Status Register */
#define SPLL_CSR_
UNUSED0_MASK WBGEN2_GEN_MASK(8
, 6)
#define SPLL_CSR_
UNUSED0_SHIFT 8
#define SPLL_CSR_
UNUSED0_W(value) WBGEN2_GEN_WRITE(value, 8
, 6)
#define SPLL_CSR_
UNUSED0_R(reg) WBGEN2_GEN_READ(reg, 8
, 6)
/* definitions for field: Number of reference channels (max: 32) in reg: SPLL Control/Status Register */
#define SPLL_CSR_N_REF_MASK WBGEN2_GEN_MASK(
8
, 6)
#define SPLL_CSR_N_REF_SHIFT
8
#define SPLL_CSR_N_REF_W(value) WBGEN2_GEN_WRITE(value,
8
, 6)
#define SPLL_CSR_N_REF_R(reg) WBGEN2_GEN_READ(reg,
8
, 6)
#define SPLL_CSR_N_REF_MASK WBGEN2_GEN_MASK(
16
, 6)
#define SPLL_CSR_N_REF_SHIFT
16
#define SPLL_CSR_N_REF_W(value) WBGEN2_GEN_WRITE(value,
16
, 6)
#define SPLL_CSR_N_REF_R(reg) WBGEN2_GEN_READ(reg,
16
, 6)
/* definitions for field: Number of output channels (max: 8) in reg: SPLL Control/Status Register */
#define SPLL_CSR_N_OUT_MASK WBGEN2_GEN_MASK(
16
, 3)
#define SPLL_CSR_N_OUT_SHIFT
16
#define SPLL_CSR_N_OUT_W(value) WBGEN2_GEN_WRITE(value,
16
, 3)
#define SPLL_CSR_N_OUT_R(reg) WBGEN2_GEN_READ(reg,
16
, 3)
#define SPLL_CSR_N_OUT_MASK WBGEN2_GEN_MASK(
24
, 3)
#define SPLL_CSR_N_OUT_SHIFT
24
#define SPLL_CSR_N_OUT_W(value) WBGEN2_GEN_WRITE(value,
24
, 3)
#define SPLL_CSR_N_OUT_R(reg) WBGEN2_GEN_READ(reg,
24
, 3)
/* definitions for field:
Enable Period Measurement
in reg: SPLL Control/Status Register */
#define SPLL_CSR_
PER_EN WBGEN2_GEN_MASK(19
, 1)
/* definitions for field:
Debug queue supported
in reg: SPLL Control/Status Register */
#define SPLL_CSR_
DBG_SUPPORTED WBGEN2_GEN_MASK(27
, 1)
/* definitions for register: External Clock Control Register */
/* definitions for field: Enable External Clock
BB Detector
in reg: External Clock Control Register */
/* definitions for field: Enable External Clock
PLL
in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: External Clock Input Available in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_SUPPORTED WBGEN2_GEN_MASK(1, 1)
/* definitions for field: E
nable PPS/phase alignm
ent in reg: External Clock Control Register */
#define SPLL_ECCR_
ALIGN_EN
WBGEN2_GEN_MASK(2, 1)
/* definitions for field: E
xternal Clock Reference Pres
ent in reg: External Clock Control Register */
#define SPLL_ECCR_
EXT_REF_PRESENT
WBGEN2_GEN_MASK(2, 1)
/* definitions for field: PPS/phase alignment done in reg: External Clock Control Register */
#define SPLL_ECCR_ALIGN_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Aligner Control Register */
/* definitions for field: External Clock Reference Present in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_REF_PRESENT WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Aligner sample valid/select on channel in reg: Aligner Control Register */
#define SPLL_AL_CR_VALID_MASK WBGEN2_GEN_MASK(0, 9)
#define SPLL_AL_CR_VALID_SHIFT 0
#define SPLL_AL_CR_VALID_W(value) WBGEN2_GEN_WRITE(value, 0, 9)
#define SPLL_AL_CR_VALID_R(reg) WBGEN2_GEN_READ(reg, 0, 9)
/* definitions for register: DMTD Clock Control Register */
/* definitions for field: Aligner required on channel in reg: Aligner Control Register */
#define SPLL_AL_CR_REQUIRED_MASK WBGEN2_GEN_MASK(9, 9)
#define SPLL_AL_CR_REQUIRED_SHIFT 9
#define SPLL_AL_CR_REQUIRED_W(value) WBGEN2_GEN_WRITE(value, 9, 9)
#define SPLL_AL_CR_REQUIRED_R(reg) WBGEN2_GEN_READ(reg, 9, 9)
/* definitions for field: DMTD Clock Undersampling Divider in reg: DMTD Clock Control Register */
#define SPLL_DCCR_GATE_DIV_MASK WBGEN2_GEN_MASK(0, 6)
#define SPLL_DCCR_GATE_DIV_SHIFT 0
#define SPLL_DCCR_GATE_DIV_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define SPLL_DCCR_GATE_DIV_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for register: Aligner Counter REF register */
/* definitions for register:
Reference Channel Undersampling Enable R
egister */
/* definitions for register:
Aligner Counter IN r
egister */
/* definitions for field: Reference Channel Undersampling Enable in reg: Reference Channel Undersampling Enable Register */
#define SPLL_RCGER_GATE_SEL_MASK WBGEN2_GEN_MASK(0, 32)
#define SPLL_RCGER_GATE_SEL_SHIFT 0
#define SPLL_RCGER_GATE_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SPLL_RCGER_GATE_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: DMTD VCO Frequency */
/* definitions for register: Output Channel Control Register */
/* definitions for field: FREQ in reg: DMTD VCO Frequency */
#define SPLL_F_DMTD_FREQ_MASK WBGEN2_GEN_MASK(0, 28)
#define SPLL_F_DMTD_FREQ_SHIFT 0
#define SPLL_F_DMTD_FREQ_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define SPLL_F_DMTD_FREQ_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: Output Channel HW enable flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_EN_MASK WBGEN2_GEN_MASK(0, 8)
#define SPLL_OCCR_OUT_EN_SHIFT 0
#define SPLL_OCCR_OUT_EN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SPLL_OCCR_OUT_EN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: VALID in reg: DMTD VCO Frequency */
#define SPLL_F_DMTD_VALID WBGEN2_GEN_MASK(28, 1)
/* definitions for field: Output Channel locked flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_LOCK_MASK WBGEN2_GEN_MASK(8, 8)
#define SPLL_OCCR_OUT_LOCK_SHIFT 8
#define SPLL_OCCR_OUT_LOCK_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define SPLL_OCCR_OUT_LOCK_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for register: REF VCO Frequency */
/* definitions for field: FREQ in reg: REF VCO Frequency */
#define SPLL_F_REF_FREQ_MASK WBGEN2_GEN_MASK(0, 28)
#define SPLL_F_REF_FREQ_SHIFT 0
#define SPLL_F_REF_FREQ_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define SPLL_F_REF_FREQ_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: Reference Channel Enable Register */
/* definitions for field: VALID in reg: REF VCO Frequency */
#define SPLL_F_REF_VALID WBGEN2_GEN_MASK(28, 1)
/* definitions for register:
Output Channel Enable Register
*/
/* definitions for register:
EXT VCO Frequency
*/
/* definitions for register: HPLL Period Error */
/* definitions for field: FREQ in reg: EXT VCO Frequency */
#define SPLL_F_EXT_FREQ_MASK WBGEN2_GEN_MASK(0, 28)
#define SPLL_F_EXT_FREQ_SHIFT 0
#define SPLL_F_EXT_FREQ_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define SPLL_F_EXT_FREQ_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: Period error value in reg: HPLL Period Error */
#define SPLL_PER_HPLL_ERROR_MASK WBGEN2_GEN_MASK(0, 16)
#define SPLL_PER_HPLL_ERROR_SHIFT 0
#define SPLL_PER_HPLL_ERROR_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SPLL_PER_HPLL_ERROR_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: VALID in reg: EXT VCO Frequency */
#define SPLL_F_EXT_VALID WBGEN2_GEN_MASK(28, 1)
/* definitions for field: Period Error Valid in reg: HPLL Period Error */
#define SPLL_PER_HPLL_VALID WBGEN2_GEN_MASK(16, 1)
/* definitions for register: Output Channel Control Register */
/* definitions for field: Output Channel HW enable flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_EN_MASK WBGEN2_GEN_MASK(8, 8)
#define SPLL_OCCR_OUT_EN_SHIFT 8
#define SPLL_OCCR_OUT_EN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define SPLL_OCCR_OUT_EN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Output Channel locked flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_LOCK_MASK WBGEN2_GEN_MASK(16, 8)
#define SPLL_OCCR_OUT_LOCK_SHIFT 16
#define SPLL_OCCR_OUT_LOCK_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define SPLL_OCCR_OUT_LOCK_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for register: Reference Channel Tagging Enable Register */
/* definitions for register: Output Channel Tagging Enable Register */
/* definitions for register: Helper DAC Output */
...
...
@@ -136,7 +150,7 @@
#define SPLL_DAC_MAIN_DAC_SEL_W(value) WBGEN2_GEN_WRITE(value, 16, 4)
#define SPLL_DAC_MAIN_DAC_SEL_R(reg) WBGEN2_GEN_READ(reg, 16, 4)
/* definitions for register: Deglitcher threshold */
/* definitions for register: D
DMTD D
eglitcher threshold */
/* definitions for register: Debug FIFO Register - SPLL side */
...
...
@@ -229,45 +243,53 @@ PACKED struct SPLL_WB {
uint32_t
CSR
;
/* [0x4]: REG External Clock Control Register */
uint32_t
ECCR
;
/* [0x8]: REG DMTD Clock Control Register */
uint32_t
DCCR
;
/* [0xc]: REG Reference Channel Undersampling Enable Register */
uint32_t
RCGER
;
/* [0x10]: REG Output Channel Control Register */
/* [0x8]: REG Aligner Control Register */
uint32_t
AL_CR
;
/* [0xc]: REG Aligner Counter REF register */
uint32_t
AL_CREF
;
/* [0x10]: REG Aligner Counter IN register */
uint32_t
AL_CIN
;
/* [0x14]: REG DMTD VCO Frequency */
uint32_t
F_DMTD
;
/* [0x18]: REG REF VCO Frequency */
uint32_t
F_REF
;
/* [0x1c]: REG EXT VCO Frequency */
uint32_t
F_EXT
;
/* [0x20]: REG Output Channel Control Register */
uint32_t
OCCR
;
/* [0x
14]: REG Reference Channel
Enable Register */
/* [0x
24]: REG Reference Channel Tagging
Enable Register */
uint32_t
RCER
;
/* [0x
18]: REG Output Channel
Enable Register */
/* [0x
28]: REG Output Channel Tagging
Enable Register */
uint32_t
OCER
;
/*
[0x1c]: REG HPLL Period Error
*/
uint32_t
PER_HPLL
;
/* [0x
2
0]: REG Helper DAC Output */
/*
padding to: 16 words
*/
uint32_t
__padding_0
[
5
]
;
/* [0x
4
0]: REG Helper DAC Output */
uint32_t
DAC_HPLL
;
/* [0x
2
4]: REG Main DAC Output */
/* [0x
4
4]: REG Main DAC Output */
uint32_t
DAC_MAIN
;
/* [0x
28]: REG
Deglitcher threshold */
/* [0x
48]: REG DDMTD
Deglitcher threshold */
uint32_t
DEGLITCH_THR
;
/* [0x
2
c]: REG Debug FIFO Register - SPLL side */
/* [0x
4
c]: REG Debug FIFO Register - SPLL side */
uint32_t
DFR_SPLL
;
/* padding to:
16
words */
uint32_t
__padding_
0
[
4
];
/* [0x
4
0]: REG Interrupt disable register */
/* padding to:
24
words */
uint32_t
__padding_
1
[
4
];
/* [0x
6
0]: REG Interrupt disable register */
uint32_t
EIC_IDR
;
/* [0x
4
4]: REG Interrupt enable register */
/* [0x
6
4]: REG Interrupt enable register */
uint32_t
EIC_IER
;
/* [0x
4
8]: REG Interrupt mask register */
/* [0x
6
8]: REG Interrupt mask register */
uint32_t
EIC_IMR
;
/* [0x
4
c]: REG Interrupt status register */
/* [0x
6
c]: REG Interrupt status register */
uint32_t
EIC_ISR
;
/* [0x
5
0]: REG FIFO 'Debug FIFO Register - Host side' data output register 0 */
/* [0x
7
0]: REG FIFO 'Debug FIFO Register - Host side' data output register 0 */
uint32_t
DFR_HOST_R0
;
/* [0x
5
4]: REG FIFO 'Debug FIFO Register - Host side' data output register 1 */
/* [0x
7
4]: REG FIFO 'Debug FIFO Register - Host side' data output register 1 */
uint32_t
DFR_HOST_R1
;
/* [0x
5
8]: REG FIFO 'Debug FIFO Register - Host side' control/status register */
/* [0x
7
8]: REG FIFO 'Debug FIFO Register - Host side' control/status register */
uint32_t
DFR_HOST_CSR
;
/* [0x
5
c]: REG FIFO 'Tag Readout Register' data output register 0 */
/* [0x
7
c]: REG FIFO 'Tag Readout Register' data output register 0 */
uint32_t
TRR_R0
;
/* [0x
6
0]: REG FIFO 'Tag Readout Register' control/status register */
/* [0x
8
0]: REG FIFO 'Tag Readout Register' control/status register */
uint32_t
TRR_CSR
;
};
...
...
kernel/wbgen-regs/softpll-regs.wb
View file @
f440fba2
...
...
@@ -9,17 +9,16 @@ peripheral {
name = "SPLL Control/Status Register";
prefix = "CSR";
field {
align = 8;
name = "Period detector reference select
";
prefix = "PER_SEL
";
name = "Unused (kept for software compatibility).
";
prefix = "UNUSED0
";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = CONSTANT;
value = 0;
};
field {
align = 8;
name = "Number of reference channels (max: 32)";
...
...
@@ -41,11 +40,11 @@ peripheral {
};
field {
name = "
Enable Period Measurement
";
prefix = "
PER_EN
";
name = "
Debug queue supported
";
prefix = "
DBG_SUPPORTED
";
type = BIT;
access_bus = READ_
WRITE
;
access_dev =
READ
_ONLY;
access_bus = READ_
ONLY
;
access_dev =
WRITE
_ONLY;
};
};
...
...
@@ -58,14 +57,12 @@ peripheral {
prefix = "ECCR";
field {
name = "Enable External Clock
BB Detector
";
name = "Enable External Clock
PLL
";
prefix = "EXT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "External Clock Input Available";
description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\
...
...
@@ -76,71 +73,138 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Enable PPS/phase alignment";
description = "write 1: starts aligning the external and local oscillator clock edges to be in phase\
right after the pulse on SYNC (PPS) input.\
write 0: no effect.";
prefix = "ALIGN_EN";
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
0: reference input dead";
prefix = "EXT_REF_PRESENT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Control Register";
prefix = "AL_CR";
field {
name = "Aligner sample valid/select on channel";
prefix = "VALID";
type = SLV;
size = 9;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "PPS/phase alignment done";
description = "1: phase alignment triggered by writing to ALIGN_EN done.\
0: phase alignment in progress.";
prefix = "ALIGN_DONE";
type = BIT;
name = "Aligner required on channel";
prefix = "REQUIRED";
type = SLV;
size = 9;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Counter REF register";
prefix = "AL_CREF";
field {
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
0: reference input dead";
prefix = "EXT_REF_PRESENT";
type = BIT;
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Counter IN register";
prefix = "AL_CIN";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "DMTD VCO Frequency";
prefix = "F_DMTD";
field {
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
---------------------------------------------
-- DMTD gating/undersampling configuration
---------------------------------------------
reg {
name = "
DMTD Clock Control Register
";
prefix = "
DCCR
";
name = "
REF VCO Frequency
";
prefix = "
F_REF
";
field {
name = "DMTD Clock Undersampling Divider";
prefix = "GATE_DIV";
size = 6;
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Reference Channel Undersampling Enable Register
";
prefix = "RCGER
";
name = "EXT VCO Frequency
";
prefix = "F_EXT
";
field {
name = "Reference Channel Undersampling Enable";
prefix = "GATE_SEL";
size = 32;
type = PASS_THROUGH;
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
align = 4;
name = "Output Channel Control Register";
prefix = "OCCR";
...
...
@@ -165,7 +229,7 @@ peripheral {
};
reg {
name = "Reference Channel
Enable Register";
name = "Reference Channel Tagging
Enable Register";
prefix = "RCER";
field {
...
...
@@ -181,7 +245,7 @@ peripheral {
};
reg {
name = "Output Channel
Enable Register";
name = "Output Channel Tagging
Enable Register";
prefix = "OCER";
field {
...
...
@@ -196,32 +260,8 @@ peripheral {
};
};
reg {
name = "HPLL Period Error";
prefix = "PER_HPLL";
field {
name = "Period error value";
prefix = "ERROR";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tag_hpll_rd_period_o";
};
field {
name = "Period Error Valid";
prefix = "VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
align = 8;
name = "Helper DAC Output";
prefix = "DAC_HPLL";
...
...
@@ -253,7 +293,7 @@ peripheral {
};
reg {
name = "Deglitcher threshold";
name = "D
DMTD D
eglitcher threshold";
prefix = "DEGLITCH_THR";
field {
...
...
@@ -284,12 +324,15 @@ peripheral {
};
};
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
direction = CORE_TO_BUS;
size = 8192;
optional = "g_with_debug_fifo";
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
...
...
@@ -340,7 +383,6 @@ peripheral {
};
irq {
name = "Got a tag";
prefix = "TAG";
...
...
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