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White Rabbit Network Interface Card
Commit f440fba2 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk Committed by Miguel Jimenez Lopez
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softpll: update header file to follow latest changes in ext SPLL

parent 7e8070eb
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Showing with 263 additions and 199 deletions
kernel/wbgen-regs/softpll-regs.h
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kernel/wbgen-regs/softpll-regs.wb
View file @ f440fba2
......@@ -9,17 +9,16 @@ peripheral {
name = "SPLL Control/Status Register";
prefix = "CSR";
field {
align = 8;
name = "Period detector reference select";
prefix = "PER_SEL";
name = "Unused (kept for software compatibility).";
prefix = "UNUSED0";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = CONSTANT;
value = 0;
};
field {
align = 8;
name = "Number of reference channels (max: 32)";
......@@ -41,11 +40,11 @@ peripheral {
};
field {
name = "Enable Period Measurement";
prefix = "PER_EN";
name = "Debug queue supported";
prefix = "DBG_SUPPORTED";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -58,14 +57,12 @@ peripheral {
prefix = "ECCR";
field {
name = "Enable External Clock BB Detector";
name = "Enable External Clock PLL";
prefix = "EXT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "External Clock Input Available";
description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\
......@@ -76,71 +73,138 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Enable PPS/phase alignment";
description = "write 1: starts aligning the external and local oscillator clock edges to be in phase\
right after the pulse on SYNC (PPS) input.\
write 0: no effect.";
prefix = "ALIGN_EN";
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
0: reference input dead";
prefix = "EXT_REF_PRESENT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Control Register";
prefix = "AL_CR";
field {
name = "Aligner sample valid/select on channel";
prefix = "VALID";
type = SLV;
size = 9;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "PPS/phase alignment done";
description = "1: phase alignment triggered by writing to ALIGN_EN done.\
0: phase alignment in progress.";
prefix = "ALIGN_DONE";
type = BIT;
name = "Aligner required on channel";
prefix = "REQUIRED";
type = SLV;
size = 9;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Counter REF register";
prefix = "AL_CREF";
field {
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
0: reference input dead";
prefix = "EXT_REF_PRESENT";
type = BIT;
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Counter IN register";
prefix = "AL_CIN";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "DMTD VCO Frequency";
prefix = "F_DMTD";
field {
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
---------------------------------------------
-- DMTD gating/undersampling configuration
---------------------------------------------
reg {
name = "DMTD Clock Control Register";
prefix = "DCCR";
name = "REF VCO Frequency";
prefix = "F_REF";
field {
name = "DMTD Clock Undersampling Divider";
prefix = "GATE_DIV";
size = 6;
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Reference Channel Undersampling Enable Register";
prefix = "RCGER";
name = "EXT VCO Frequency";
prefix = "F_EXT";
field {
name = "Reference Channel Undersampling Enable";
prefix = "GATE_SEL";
size = 32;
type = PASS_THROUGH;
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
align = 4;
name = "Output Channel Control Register";
prefix = "OCCR";
......@@ -165,7 +229,7 @@ peripheral {
};
reg {
name = "Reference Channel Enable Register";
name = "Reference Channel Tagging Enable Register";
prefix = "RCER";
field {
......@@ -181,7 +245,7 @@ peripheral {
};
reg {
name = "Output Channel Enable Register";
name = "Output Channel Tagging Enable Register";
prefix = "OCER";
field {
......@@ -196,32 +260,8 @@ peripheral {
};
};
reg {
name = "HPLL Period Error";
prefix = "PER_HPLL";
field {
name = "Period error value";
prefix = "ERROR";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tag_hpll_rd_period_o";
};
field {
name = "Period Error Valid";
prefix = "VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
align = 8;
name = "Helper DAC Output";
prefix = "DAC_HPLL";
......@@ -253,7 +293,7 @@ peripheral {
};
reg {
name = "Deglitcher threshold";
name = "DDMTD Deglitcher threshold";
prefix = "DEGLITCH_THR";
field {
......@@ -284,12 +324,15 @@ peripheral {
};
};
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
direction = CORE_TO_BUS;
size = 8192;
optional = "g_with_debug_fifo";
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
......@@ -340,7 +383,6 @@ peripheral {
};
irq {
name = "Got a tag";
prefix = "TAG";
......
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