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White Rabbit Network Interface Card
Commit fe284dff authored by Miguel Jimenez Lopez's avatar Miguel Jimenez Lopez
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hdl: Update top-level design of the NIC project. 

- The wr_nic_wrapper block is now included in the top-level design.
- The memory layout of the main WB crossbar has been also updated.
parent 91fd7ad6
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Showing with 57 additions and 13 deletions
wr-cores @ 6f9c1177
Subproject commit e2f7cce74217c61f4e02f0b80b55deeb92d8b6f4
Subproject commit 6f9c1177a98f50fed036c6650305b936597895a9
hdl/top/nic/nic_top.vhd
View file @ fe284dff
......@@ -46,9 +46,12 @@ use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.gn4124_core_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
use work.wr_nic_wrapper_pkg.all;
library unisim;
use unisim.vcomponents.all;
......@@ -215,33 +218,32 @@ architecture top of nic_top is
-----------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 2;
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves on the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
constant c_NUM_WB_SLAVES : integer := 2;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_PCIE : integer := 0;
constant c_WB_MASTER_ETHBONE : integer := 1;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_WRC : integer := 0;
-- SDB meta info
constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_SLAVES;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_SLAVES;
constant c_WB_SLAVE_NIC : integer := 1;
-- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_SDB_ADDRESS : t_wishbone_address := x"00070000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_WRC_BRIDGE_SDB : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_NIC_BRIDGE_SDB : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0001ffff", x"00011000");
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_WRC_BRIDGE_SDB, x"00040000"));
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_WRC_BRIDGE_SDB, x"00000000"),
c_WB_SLAVE_NIC => f_sdb_embed_bridge(c_NIC_BRIDGE_SDB, x"00040000"));
-----------------------------------------------------------------------------
-- Signals
......@@ -286,6 +288,8 @@ architecture top of nic_top is
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
signal wrc_pps_out : std_logic;
signal wrc_pps_csync_out : std_logic;
signal wrc_pps_valid_out : std_logic;
signal wrc_pps_led : std_logic;
signal wrc_pps_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
......@@ -295,6 +299,16 @@ architecture top of nic_top is
signal dio_out : std_logic_vector(4 downto 0);
signal vic_irq : std_logic;
-- WR Fabric I/F
signal wrc_wrf_src_out : t_wrf_source_out;
signal wrc_wrf_src_in : t_wrf_source_in;
signal wrc_wrf_snk_out : t_wrf_sink_out;
signal wrc_wrf_snk_in : t_wrf_sink_in;
-- Tx Timestamp
signal wrc_timestamps_out : t_txtsu_timestamp;
signal wrc_timestamps_ack_in : std_logic := '1';
begin -- architecture top
......@@ -415,7 +429,7 @@ begin -- architecture top
g_simulation => g_simulation,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_dpram_initf,
g_fabric_iface => NIC)
g_fabric_iface => PLAIN)
port map (
areset_n_i => button1_i,
areset_edge_n_i => gn_rst_n,
......@@ -467,16 +481,25 @@ begin -- architecture top
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WRC),
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WRC),
wrf_src_o => wrc_wrf_src_out,
wrf_src_i => wrc_wrf_src_in,
wrf_snk_o => wrc_wrf_snk_out,
wrf_snk_i => wrc_wrf_snk_in,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
timestamps_o => wrc_timestamps_out,
timestamps_ack_i => wrc_timestamps_ack_in,
pps_ext_i => wrc_pps_in,
pps_p_o => wrc_pps_out,
pps_csync_o => wrc_pps_csync_out,
pps_valid_o => wrc_pps_valid_out,
pps_led_o => wrc_pps_led,
led_link_o => led_link_o,
led_act_o => led_act_o,
vic_int_o => vic_irq);
led_act_o => led_act_o);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
......@@ -552,5 +575,26 @@ begin -- architecture top
extended_o => dio_led_top_o);
dio_led_bot_o <= '0';
cmp_nic_wrapper : wr_nic_wrapper
generic map(
g_num_irqs => 1,
g_num_ports => 1
)
port map(
clk_sys_i => clk_sys_62m5,
resetn_i => rst_sys_62m5_n,
ext_slave_i => cnx_slave_in(c_WB_SLAVE_NIC),
ext_slave_o => cnx_slave_out(c_WB_SLAVE_NIC),
nic_snk_i => wrc_wrf_src_out,
nic_snk_o => wrc_wrf_src_in,
nic_src_i => wrc_wrf_snk_out,
nic_src_o => wrc_wrf_snk_in,
pps_p_i => wrc_pps_csync_out,
pps_valid_i => wrc_pps_valid_out,
vic_irqs_i => (others => '0'),
vic_int_o => vic_irq,
txtsu_timestamps_i(0) => wrc_timestamps_out,
txtsu_timestamps_ack_o(0) => wrc_timestamps_ack_in);
end architecture top;
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