White Rabbit Network Interface Card
This project is concerned with the development of gateware and software to make the combination of a SPEC and a DIO mezzanine behave as a Network Interface Card (NIC) under Linux.
The WR-NIC block diagram with all the gateware components is shown in the figure above. Then, a quick description of them is presented:
- The Digital Input Output (DIO) core allows configuration of each one of the 5 channels of the DIO mezzanine as input or output. For inputs, it provides an accurate UTC time stamp (using UTC from the WRPC, not shown in the diagram) and optionally a host (PCIe) interrupt via the IRQ Gen block. For outputs, it allows the user to schedule the generation of a pulse at a given future UTC time, or to generate it immediately.
- The Interrupt Request Generator (IRQ Gen) block receives one-tick-long pulses from other blocks and generates interrupt requests to the GN4124 core. It also includes interrupt source and mask registers.
- The Wishbone interconector (WB intercon) block ensures seamless interconnection of Wishbone masters and slaves using a crossbar topology.
- The GN4124 core is a bridge between the GN4124 PCIe interface chip and the internal Wishbone bus, allowing communication with the host and interrupts.
- The White Rabbit PTP Core (WRPC) communicates with the outside world through the SFP socket in the SPEC, typically using fiber optics. It deals with the WR PTP using an internal LM32 CPU running a PTP stack. It forwards/receives non-PTP frames to/from the NIC block, using two pipelined Wishbone interfaces (master and slave for forwarding and receiving respectively). It also provides UTC time to other cores (not represented in the diagram), and time-tags for transmitted and received frames that can be read through Wishbone for diagnostics purposes.
- The Network Interface Component (NIC) core ensures communication between the host and the WRPC. More precisely, it interrupts the host and provides a descriptor that the host can use to fetch incoming frames. For outgoing frames, it receives a descriptor from the host, fetches the frame using PCIe DMA via the GN4124 core and sends it to the WRPC using a pipelined Wishbone interface.
- The TxTSU module collects timestamps with associated Ethernet frame identifiers and puts them in a shared FIFO.
- The Etherbone (EB) core is a component that allows remote device configuration through the network using conventional UDP packets. It is necessary to allow the WR-NIC to work in standalone mode without the need of being connected to the computer PCIe port.
- The Multiplexer (MUX) core inspects the incoming packets and routes them to the Etherbone or NIC component depending on its class. Each received packet from the network is classified by the WRPC to decide which is the component that will process it. For this reason, the software for the WRPC must be modified in order to set the different classes and the rules to identify them.
A caution to be considered in this release is that the first DIO FMC output channel is reserved for 1-PPS signal from the WRPC. This is the simplest way to avoid the delay between the 1-PPS input and 1-PPS output when the Grand Master mode is used.*
This project focus on the HDL but It is currently fully supported in terms of additional software (board drivers, applications examples, etc...) as well as documentation. Please check the White Rabbit Starting kit project for additional details.
Related projects
- White-Rabbit PTP core
- SPEC board (simple PCIe carrier)
- FMC-DIO card
- FPGA Configuration Space Specification SDB
- White-Rabbit Starting kit
Contacts
Main developers
- Javier Díaz - Seven Solutions / University of Granada
- Rafael Rodriguez - Seven Solutions
- Tomasz Wlostowski & Grzegorz Daniluk - CERN
- Alessandro Rubini - Gnudd
- Miguel Jiménez López - University of Granada
General questions about project
- Javier Díaz - Seven Solutions / University of Granada
Releases
Version | Date | Description |
1.0 | 17-12-2012 | First gateware implementation |
1.1 | 07-01-2013 | Update to new HDL lib and fix the version |
2.0 | 17-02-2014 | Standalone mode, Etherbone Network configuration, PPS delay corrected |
3.0 | Planned | Add the DMA support in order to improve the performance |
Note:* The current gateware version is indicated in bold.
Project status
Date | Event |
09-02-2012 | Project definition |
14-05-2012 | Preliminary gateware development |
30-09-2012 | Gateware delivery with sdb support |
07-01-2013 | Software/gateware first release |
17-02-2014 | Gateware second release |
Javier Díaz - 30 July 2014