Commit 6091858b authored by Maciej Lipinski's avatar Maciej Lipinski

wrspec: added appendices: extract from Tomeks MSc + incorporation WR Link Model…

wrspec: added appendices: extract from Tomeks MSc + incorporation WR Link Model into PTP calculations
parent 54df63f8
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%%EndData
showpage
%%Trailer
end
%%EOF
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% \def\us{\char`\_}
\subsection{WR link model}
\label{s:link_model}
Knowledge of the physical model of links connecting the clocks is a
prerequisite for achieving the required synchronization accuracy. The model
of a WR optical link is depicted in Figure~\ref{fig:link_model}.
\begin{figure}[ht!]
\centering
\includegraphics[width=15cm]{fig/tomeksDrawings/link_model.eps}
\caption{Model of a WR link (a) and relations between master and slave
clocks (b)}
\label{fig:link_model}
\end{figure}
[...]
% \textit{Delta} values shown in Figure~\ref{fig:link_model} express the delays
% introduced by various elements of the system. Big deltas ($\Delta_{txm},
% \Delta_{rxs}, \Delta_{txs}, \Delta_{rxm}$) indicate constant delays
% (e.g. the delays which never change when the link is active), while small
% deltas ($\delta_{ms}, \delta_{sm}$) express the delays which can vary during
% the operation of the link.
WR employs the clock loopback technique to measure the round-trip phase shift
$phase_{MM}$, which is a starting point for determining the precise two-way
delay $delay_{MM}$ and thus the clock offset $offset_{MS}$. The clock signal is
transferred between the master and the slave according to the following scheme:
\begin{enumerate}
\item The reference clock (1) is used to encode the master's transmitter
output and then extracted from the data stream at the slave's receiver. The
recovered clock (2) is a copy of clock (1) delayed by $delay_{MS}$, where
\begin{equation}
\label{eq:delayms}
delay_{MS} = \Delta_{txm} + \delta_{ms} + \Delta_{rxs}
\end{equation}
expresses the master-to-slave latency introduced by the transceivers and
the link.
\item The recovered clock (2) is fed to a clock adjustment unit which shifts
its phase by a programmable value $phase_{S}$ to obtain the phase-compensated
clock (3) -- the final result of WR synchronization.
\item Clock (3) encodes the slave's outgoing data stream and is recovered
at the master side as signal (4).
\item The master measures the phase shift $phase_{MM}$ between its outgoing
(1) and incoming (4) clocks using a phase detector.
\end{enumerate}
The value of $phase_{MM}$ can be expressed as:
\begin{equation}
\label{eq:phasemm}
phase_{MM} = \{\Delta + \delta_{ms} + \delta_{sm} + phase_{S}\} \bmod
T_{ref}
\end{equation}
where $\Delta = \Delta_{txm} + \Delta_{rxs} + \Delta_{txs} + \Delta_{rxm}$
and $T_{ref}$ is the period of Gigabit Ethernet 125 MHz reference clock (8 ns).
The goal of the presented model is to calculate the precise value of
master-to-slave offset $offset_{MS}$ by combining a coarse timestamp-based
round-trip delay \ref{eq:meanPath} with precise phase measurement
$phase_{MM}.$ Once the offset is computed, the WR slave can phase-shift its
recovered clock (deriving $phase_{S}$ from $offset_{MS}$) to match the phase
of the master clock, completing the synchronization.
\begin{figure}[ht!]
\centering
\includegraphics[width=15cm]{fig/tomeksDrawings/sync_flow.eps}
\caption{WR synchronization flow}
\label{fig:sync_flow}
\end{figure}
Determining the precise offset, however, is not a trivial task. Figure
\ref{fig:sync_flow} shows the steps needed to achieve and maintain
synchronization of a single WR link. The synchronization process can be
split into two parts: \begin{itemize}
\item \textbf{initial synchronization}, which determines the value of
$offset_{MS}$ and fixes the slave's phase shift to compensate the offset.
\item \textbf{phase tracking} which monitors the changes of $phase_{MM}$
over time and updates the phase shifter in the slave to follow these changes
and sustain synchronization.
\end{itemize}
\newpage
\subsection{Link detection and syntonization}
During the first two steps of the synchronization flow
\ref{fig:sync_flow}, a syntonized WR connection is established. Drawing
\ref{fig:link_detect_and_syntonization} shows the order of hardware operations
and message exchanges which result in a syntonized link.
\begin{figure}[ht!]
\centering
\includegraphics[width=7cm]{fig/tomeksDrawings/link_detect_and_syntonization.eps}
\caption{WR Link detection and syntonization}
\label{fig:link_detect_and_syntonization}
\end{figure}
At the initial moment, the master and the slave are not connected to
each other. Their PHYs are transmitting an Ethernet idle pattern (see Table 3.1 \cite{tomekMSC}),
but are not receiving any meaningful bitstreams. As soon
as the physical connection is present, the PHYs will start receiving valid
idle patterns and the Ethernet link will become active (see \cite{IEEE802.3}
section 36.2.5.2.6). Presence of a valid physical link will trigger the
following sequence:
\begin{enumerate}
\item The master starts broadcasting \textit{ANNOUNCE} messages to look for
a WR slave,
\item Eventually, the slave will respond with a \textit{SLAVE\us PRESENT}
message, indicating that it supports WR. If no response has been received
within a predefined time, the master assumes that the slave is not WR
compatible and aborts the synchronization process,
\item The master issues a \textit{LOCK} message, commanding the slave to
begin recovering the clock from its received data stream,
\item The slave sets up its PLL to use the RX clock as a reference and as
soon as the PLL is locked, responds with a \textit{LOCKED} message.
\end{enumerate}
Upon successful completion of the above process, both nodes are syntonized
and the delay measurements can begin.
\subsection{Coarse delay measurement}
\label{s:coarse_delay}
The coarse delay measurement produces a set of timestamps $t_{1} ... t_{4}$
which are obtained using the PTP End-to-End, two-way clock method as shown
in fig. \ref{fig:ptp_exchange}. The timestamps are generated in the hardware
in fig. \ref{fig:wrPTPmsgs}. The timestamps are generated in the hardware
with a circuit depicted in fig. \ref{fig:coarse_measurement}, guaranteeing
single-cycle timestamping accuracy, which is necessary for reliably merging the
coarse delay with the $phase_{MM}$ phase shift during fine delay calculation.
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=17cm]{Tomeksdrawings/coarse_measurement.eps}
\includegraphics[width=17cm]{fig/tomeksDrawings/coarse_measurement.eps}
\caption{Structure of a WR timestamping unit (TSU)}
\label{fig:coarse_measurement}
\end{figure}
Timestamps in WR are taken when the PCS detects a Start-of-Frame Delimiter
(SFD) character in the incoming (RX timestamps) or outgoing (TX timestamps)
data stream (see \ref{s:ether_pcs}).
data stream (see section 3.2.2 \cite{tomekMSC}).
Let's first focus on the blocks marked blue in
fig. \ref{fig:coarse_measurement}. Each time an SFD character is detected,
Figure~\ref{fig:coarse_measurement}. Each time an SFD character is detected,
the PCS produces a timestamp trigger pulse which causes the timestaming unit
to take a snapshot of the free running counter CNTR\us R with the D-type
register DREG\us R. The counter is counting from 0 to 124999999 which (given
the reference clock frequency of 125 MHz) gives a period of one full second.
The counter CNTR\us R works synchronously to the reference clock (master side,
signal 1 in fig. \ref{fig:link_model}) or the compensated clock (slave side,
signal 1 in Figure~\ref{fig:link_model}) or the compensated clock (slave side,
signal 5). Since RX trigger pulses come from different clock domains (2 or
4), they need to be synchronized to the reference clock with a chain of
D flip-flops (SYNC). Single-cycle long trigger pulses are widened by the
......@@ -38,15 +151,15 @@ chain to obtain identical trigger reaction latency.
Unfortunately, due to the jitter of clock signals, crossing clock domains
can make the gathered timestamps useless by causing a random $\pm 1$ LSB
error when the RX clock and the reference clocks are almost in phase. The
problem is illustrated in figure \ref{fig:ts_jitter} Dashed lines show
problem is illustrated in Figure~\ref{fig:ts_jitter}. Dashed lines show
the transitions of ideal (jitter-free) clocks. If the jitter is neglected,
the reference clock transition should be slightly ahead of the RX clock
transition and the gathered timestamp should be equal to 2. However, if the
clocks are jittery, the transitions may sometimes occur in reverse order,
producing an erroneous timestamp of value 1.
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=10cm]{drawings/ts_jitter.pdf}
\includegraphics[width=10cm]{fig/tomeksDrawings/ts_jitter.eps}
\caption{Timestamping errors caused by clock jitter}
\label{fig:ts_jitter}
\end{figure}
......@@ -56,12 +169,12 @@ reference clock edges. The falling edge part of the TSU is marked pink in
instead, the current value of the rising edge counter is latched in register
CNTR\us F on the falling edge of the reference clock, making the CNTR\us
F a copy of CNTR\us R delayed by a half of the clock period. This method
ensures that at least one of the timestamps is valid at any moment (see
\ref{fig:ts_dualedge}). The correct timestamp is chosen depending on the
ensures that at least one of the timestamps is valid at any moment
(see Figure~\ref{fig:ts_dualedge}). The correct timestamp is chosen depending on the
current phase shift between clocks (see section \ref{s:fine_delay}).
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=12cm]{drawings/ts_dualedge.pdf}
\includegraphics[width=12cm]{fig/tomeksDrawings/ts_dualedge.eps}
\caption{Dual-edge timestamping in WR}
\label{fig:ts_dualedge}
\end{figure}
......@@ -85,9 +198,9 @@ software using the algorithm shown in listing \ref{lst:utc_gen}.
The fine delay measurements in WR are based on a Dual Mixer Time Difference
(DMTD) phase detector. Therefore, in this section a short introduction to
DMTD technology will be presented.
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=11cm]{drawings/analog_dmtd.pdf}
\includegraphics[width=11cm]{fig/tomeksDrawings/analog_dmtd.eps}
\caption{Structure of an analog DMTD phase detector}
\label{fig:analog_dmtd}
\end{figure}
......@@ -123,9 +236,9 @@ external discrete components (mixers and filters), which can be troublesome,
especially in multi-port applications such as the WR switch. Fortunately, the
analog mixing operation can be transformed into a digital sampling operation,
resulting in a digital DMTD detector, shown on fig. \ref{fig:digital_dmtd}
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=12cm]{drawings/digital_dmtd.pdf}
\includegraphics[width=12cm]{fig/tomeksDrawings/digital_dmtd.eps}
\caption{Structure of a digital DMTD phase detector}
\label{fig:digital_dmtd}
\end{figure}
......@@ -135,9 +248,9 @@ clock is generated with a PLL from one of the input clocks. The sampling
operation performed by the flip-flops can be mathematically proved to be
equivalent to analog mixing (\ref{eq:mixing2}), but the principle of a DDMTD
can be explained in a more intuitive way.
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=15cm]{drawings/dmtd_vernier.pdf}
\includegraphics[width=15cm]{fig/tomeksDrawings/dmtd_vernier.eps}
\caption{A vernier (a) and signals generated by DDMTD (b)}
\label{fig:dmtd_vernier}
\end{figure}
......@@ -167,16 +280,16 @@ clock) which is shared among all measurement channels. This opens the way
for low-cost FPGA implementations. If a picosecond-level accuracy is not
required, even a PLL integrated inside an FPGA can be used, eliminating all
external components.
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=8cm]{drawings/dmtd_glitches.png}
\includegraphics[width=8cm]{fig/tomeksDrawings/dmtd_glitches.eps}
\caption{Glitches in the DMTD output caused by clock jitter}
\label{fig:dmtd_glitches}
\end{figure}
In practical DDMTD implementations, the output signals need to be additionally
conditioned as the input clock jitter can introduce glitches, as shown
on fig. \ref{fig:dmtd_glitches}a. More details about the deglitching and
postprocessing algorithm can be found in section \ref{s:ddmtd_impl}.
postprocessing algorithm can be found in section 4.3.5 of \cite{tomekMSC}.
\subsection{Fine delay measurement}
\label{s:fine_delay}
......@@ -201,8 +314,8 @@ within clock domains asynchronous to the reference (or compensated) clock
because packets are transmitted and timestamped using the same clock.
The flow graph of the algorithm used to merge PTP timestamps with
phase measurements is shown on fig. \ref{fig:merging_timestamps}. Figure
\ref{fig:merging_example} depicts sample measurements of inputs and results
phase measurements is shown on Figure~\ref{fig:merging_timestamps}.
Figure~\ref{fig:merging_example} depicts sample measurements of inputs and results
of the enhancement algorithm for $t_{4p}$ timestamps, where the varying link
delay was simulated using the slave's phase shifter.
......@@ -221,9 +334,9 @@ delay was simulated using the slave's phase shifter.
\end{tabular}
\label{tab:ts_domains}
\end{table}
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=13cm]{drawings/merging_timestamps.pdf}
\includegraphics[width=13cm]{fig/tomeksDrawings/merging_timestamps.eps}
\caption{Algorithm for enhancing coarse timestamps with DMTD phase.}
\label{fig:merging_timestamps}
\end{figure}
......@@ -232,7 +345,7 @@ RX timestamps, by choosing either the rising or falling edge timestamp
depending on the phase between the RX clock and the reference clock. The
key parameter of this step, $\phi_{trans}$ provides an approximate
value of $phase_{MM}$ at which a transition should occur in the value of
$t_{4r}$. In fig. \ref{fig:merging_example}, it is equal to 6.6 ns - it's
$t_{4r}$. In Figure~\ref{fig:merging_example}, it is equal to 6.6 ns - it's
the approximate intersection point of $phase_{MM}$ (blue, sawtooth-like
trace) and the transition of the rising edge timestamp (red trace). The
value of $\phi_{trans}$ is a device-specific constant. It can be determined
......@@ -258,9 +371,9 @@ the coarse deglitched timestamp $t_{4}$. If the resulting picosecond part
($\phi$) is negative, an additional full cycle is added to the result. The
final output of the merging algorithm is shown in \ref{fig:merging_example}
as the thick navy trace.
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=12cm]{drawings/merging_example.pdf}
\includegraphics[width=12cm]{fig/tomeksDrawings/merging_example.eps}
\caption{Example of $t_{4p}$ timestamp enhancing.}
\label{fig:merging_example}
\end{figure}
......@@ -301,20 +414,20 @@ asymmetry),
\item Difference between TX and RX wavelengths in the fiber,
\item Internal structure and clocking of the PHY (SerDes) chips.
\end{itemize}
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=\textwidth]{drawings/asymmetries.pdf}
\includegraphics[width=\textwidth]{fig/tomeksDrawings/asymmetries.eps}
\caption{Delay asymmetries in WR optical link.}
\label{fig:asymmetries}
\end{figure}
Figure \ref{fig:asymmetries} shows the reference asymmetry model used in WR
devices. The device's asymmetric delays (as shown in fig. \ref{fig:link_model})
devices. The device's asymmetric delays (as shown in Figure~\ref{fig:link_model})
are expressed as sums of circuit, SFP and PHY delays between the phase detector
inputs (the PD measuring $delta_{MM}$ on the master side and the PD in the
phase shifting PLL on the slave side) and the SFP optical input/output. The
fiber asymmetry is compensated separately in the slave's PTP servo.
\begin{eqnarray}
\Delta_{tx(m/s))} = \delta_{TX\us PHY(M/S)} + \delta_{TX\us CIR(M/S)} +
\Delta_{tx(m/s)} = \delta_{TX\us PHY(M/S)} + \delta_{TX\us CIR(M/S)} +
\delta_{TX\us SFP(M/S)}
\\
\Delta_{rx(m/s)} = \delta_{RX\us PHY(M/S)} + \delta_{RX\us CIR(M/S)} +
......@@ -362,7 +475,7 @@ together give minimum clock offset.
\subsubsection{WDM fiber asymmetry}
\label{s:wdm_asymmetry}
As mentioned in section \ref{s:physical_layer}, WR uses different wavelengths
As mentioned in section 3.2 of \cite{tomekMSC}, WR uses different wavelengths
for transmitting and receiving the data (for example 1550/1310 nm). Due
to chromatic dispersion of the fiber, the refractive indexes for these
wavelengths are slightly different, causing different propagation speeds
......@@ -381,7 +494,7 @@ where $B_{i}$ and $C_{i}$ are material-specific coefficients.
For a standard G.652 telecom fiber, the refractive indexes are respectively:
$n_{1550} = 1.467$ and $n_{1310} = 1.466$. In order to simplify the asymmetry
calculations in the hardware, the WR specification \cite{wr_spec} defines
calculations in the hardware, the WR specification defines
a custom fiber asymmetry coefficient \ref{eq:fiber_alpha1} expressing the
ratio between the M-S and S-M fiber propagation delays:
......@@ -416,14 +529,18 @@ value of $\alpha$:
\subsubsection{Transceiver asymmetry}
\label{s:xcvr_asymmetry}
\label{sec:calibForGigbitE}
\textit{[This chapter has been modified to add clarity]}
Transceiver asymmetry is a result of the internal structure of the SerDes's
circuitry. Most of the SerDes chips nowadays are optimized for low power
consumption and fast locking to the incoming data stream. Unfortunately,
because of these optimizations, PHYs may not keep constant transmit/receive
latencies. The problem is illustrated in fig. \ref{fig:phy_asymmetry}.
\begin{figure}[htb]
latencies. The problem is illustrated in Figure~\ref{fig:phy_asymmetry}.
\begin{figure}[ht!]
\centering
\includegraphics[width=11cm]{drawings/phy_asymmetry.pdf}
\includegraphics[width=11cm]{fig/tomeksDrawings/phy_asymmetry.eps}
\caption{Random delays in gigabit SerDes devices (a) and blocks causing them
(b).}
\label{fig:phy_asymmetry}
......@@ -450,20 +567,42 @@ the parallel-to-serial register (blue, observed for TLK1221).
Alignment latency can be measured every time the link goes up by disabling
automatic comma alignment and bit-shifting the unaligned output data
until a valid 8B10B code sequence is detected (\textit{bitslip trick},
see \cite{jansweijer}). Compensation of the latter two latencies, however,
see \cite{Peek2010}). Compensation of the latter two latencies, however,
requires additional calibration logic. An example method (used in the WR
switch) is shown in fig. \ref{fig:phy_latency_measurement}.
\begin{figure}[htb]
switch) is shown in Figure~\ref{fig:phy_latency_measurement}.
\begin{figure}[ht!]
\centering
\includegraphics[width=\textwidth]{drawings/phy_latency_measurement.pdf}
% \includegraphics[width=\textwidth]{fig/tomeksDrawings/phy_latency_measurement.eps}
\includegraphics[width=0.60\textwidth]{fig/calibrate.ps}
\caption{PHY latency measurement using calibration patterns.}
\label{fig:phy_latency_measurement}
\end{figure}
The PHY transmit path is fed with a sequence of K28.5 characters (1111100000),
effectively producing a 125 MHz square wave on the serial outputs. The phase
Such methods can by applied to the
PHYs whose maximum ($\delta_{PHY(M/S)_{max}}$) and minimum ($\delta_{PHY(M/S)_{min}}$) delays are known
(provided in the datasheet) and the delay's variation is
\begin{equation}
\label{eq:fixedDelayVariation}
\delta_{\{TX, RX\}\_PHY(M/S)_{variable}} \in \langle 0 :\delta_{PHY(M/S)_{max}} - \delta_{PHY(M/S)_{min}} \rangle
\end{equation}
e.g. below 10 bit times in case of Gigabit Ethernet.
Therefore, a fixed delay can be expressed as a sum of a constant value
($\delta_{\{TX, RX\}\_PHY(M/S)_{min}}$) and a variable part ($\delta_{\{TX, RX\}\_PHY(M/S)_{variable}}$) which needs to be measured:
\begin{equation}
\label{eq:fixedDelay}
\delta_{\{TX, RX\}\_PHY(M/S)} = \delta_{\{TX, RX\}\_PHY(M/S)_{min}} + \delta_{\{TX, RX\}\_PHY(M/S)_{variable}}
\end{equation}
The PHY transmit path is fed with a sequence of RD+ K28.5 characters (1111100000),
effectively producing a 125 MHz square wave on the serial outputs.
The repeated pattern of five "0" and five "1" is defined by the IEEE 802.3 standard \cite{IEEE802.3}
as \textit{Low-frequency test pattern} (Appendix~36A.2). The phase
shift between the TX clock and the output bitstream can be measured using
a DDMTD phase detector, giving the value of the TX latency. The same method
can be used to measure the RX latency by commanding the link partner to send
a DDMTD phase detector, giving the value of the TX variable latency
($\delta_{TX\_PHY(M/S)_{variable}}$). The same method
can be used to measure the RX variable latency ($\delta_{RX\_PHY(M/S)_{variable}}$)
by commanding the link partner to send
the calibration pattern. Note that since the K28.5 character contains a comma
(5 consecutive ones), a burst of subsequent K28.5 symbols will cause improper
operation of the PHY's comma alignment unit. Therefore, comma alignment must
......@@ -506,9 +645,9 @@ servo design can be found in fig. \ref{fig:adjustment_and_servo}b. The
algorithm assumes that the frequency has been already syntonized by means
of Sync-E and only the clock offset needs to be corrected. Offset correction
is split into 3 steps:
\begin{figure}[htb]
\begin{figure}[ht!]
\centering
\includegraphics[width=\textwidth]{drawings/adjustment_and_servo.pdf}
\includegraphics[width=\textwidth]{fig/tomeksDrawings/adjustment_and_servo.eps}
\caption{WR slave offset adjustment (a) and clock servo (b)}
\label{fig:adjustment_and_servo}
\end{figure}
......@@ -553,31 +692,5 @@ no "jumps" in the signal when the value of $corr_{phase}$ crosses the
inter-cycle boundary. For example, one can use a PLL with a phase detector
capable of handling wrap-around phase transitions, but not a programmable
delay line. An example design of such phase detector and PLL is described
in section \ref{s:main_pll}.
\section{Integration of White Rabbit into PTP}
\label{s:ptp_integration}
As mentioned in section \ref{s:ptp}, WR extends the PTP standard with
several custom messages to enable frequency syntonization and PHY delay
calibration. These messages utilize the user-definable Type-Length-Value
fields in the PTP version 2 Announce and Management messages. A WR master
is therefore fully compatible with any PTPv2-compliant device.
Figure \ref{fig:ptp_wr_flow} shows the order of the PTP message exchanges
during all the phases of the synchronization process, indicating which
messages are standard PTP (black) and WR-specific (red). Note that the
calibration stages involving the exchange of calibration patterns are only
required if the remote node's PHY has type 2 (CDR) asymmetry.
The drawing is intended to complement the synchronization flow described
in the chapter and give the reader an overview of the entire WR-PTP
synchronization process. A detailed description of the data flow, packet
formats and master's and slave's state machines falls out of the scope of
this thesis. A complete description of the protocol can be found in the WR
specification \cite{wr_spec}.
\begin{figure}[htb]
\centering
\includegraphics[width=\textwidth]{drawings/ptp_wr_flow.pdf}
\caption{PTP message flow during WR synchronization.}
\label{fig:ptp_wr_flow}
\end{figure}
in section 4.3.7 of \cite{tomekMSC}.
......@@ -11,6 +11,7 @@
% Give the values of different constants in tables.
% Use thicker line for combined state in wr state machine figure.
% Take cursor out of PTP state machine figure.
\def\us{\char`\_}
\documentclass[a4paper, 12pt]{article}
%\documentclass{article}
......@@ -26,6 +27,11 @@
\usepackage{amsmath}
\usepackage{times,mathptmx}
\usepackage{chngcntr}
%%%%%5% used in Tomeks %%%%%%%
\usepackage{listings}
\usepackage{cancel}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% fig/tomeksDrawings
%\usepackage{morefloats}
%\usepackage{amsfonts}
......@@ -367,11 +373,13 @@ the form \cite{Peek2010}:
Let us start from the PTP sync timestamps, represented by the familiar
set $t_1$, $t_2$, $t_3$ and $t_4$. The mean path delay is then defined as
\begin{equation}
\label{eq:meanPath}
\mu = \frac{(t_2 - t_1) + (t_4 - t_3)}{2}
\end{equation}
Note that the transmission delays $t_2 - t_1$ and $t_4 - t_3$ can be
expressed in terms of WR's Delay Model:
\begin{align}
\
t_2 - t_1 = \Delta_{tx_m} + \delta_{ms} + \Delta_{rx_s} + \eqoffset{ms}\\
t_4 - t_3 = \Delta_{tx_s} + \delta_{sm} + \Delta_{rx_m} - \eqoffset{ms}
\end{align} where \eqoffset{ms} is the time offset between the
......@@ -398,6 +406,7 @@ notation by using equations \eqref{eq:delayms},
\subsection{Solution for Ethernet over a Single-mode Optical Fiber}
\label{sec:EthernetOverSingleModeFiber}
Combining equations \eqref{eq:singlefiber} and \eqref{eq:mu} we obtain:
\begin{gather}
\delta_{ms} = \frac{1 + \alpha}{2 + \alpha} \, (2\mu - \Delta)
......@@ -461,13 +470,15 @@ the transmit/receive (Rx/Tx) fixed delays introduced by PHY (section~\ref{sec:fi
\subsection{Fixed delays}
\label{sec:fixedDelays}
The knowledge of fixed delays $\Delta_{\{tx_m, rx_s, tx_s, rx_m\}}$ is necessary to calculate
delay asymmetry using WR Link Model (section~\ref{sec:delaymodel}). Such delays may be constant for
delay asymmetry using WR Link Model (section~\ref{sec:delaymodel}). They might include circuit,
components (ex. PHY, SFP) and FPGA internal latencies (see Appendix~\ref{s:asymmetry}
for fixed delays in WR optical link model). Such delays may be constant for
the lifetime of the hardware, its up-time or the duration of the link connection. Therefore,
the method for obtaining fixed delays is medium-specific and implementation-dependent.
The WR protocol requires the information about the fixed delays values and enables their
The WR protocol requires the information about the fixed delays values and enables PHY's delays
measurement, but does not specify how they shall be obtained.
The delays are measured (if necessary) and their values are distributed across the link during
The PHY's delays are measured (if necessary) and their values are distributed across the link during
the process of establishing the WR link, which is called \textit{WR Link Setup} in this document.
A WR~node participates in the measurement of another
WR node's reception fixed delay ($\Delta_{\{rx_m, rx_s\}}$) upon request, e.g. by sending
......@@ -503,7 +514,7 @@ and falling edges of the clock. It is provided with the phase measurement of the
The phase measurement is used by the timestamping unit to choose the correct edge timestamp and
enhance it to the precision allowed by the phase detector.
Details of the implementation of the presented solution are presented in
Appendix~\ref{sec:FineDelayMeasurement}.
Appendix~\ref{s:fine_delay}.
......@@ -1462,6 +1473,11 @@ executed in the PTP UNCALIBRATED state on the WR Slave (WR Port in WR Slave mode
the PTP MASTER state on the WR Master (WR Port in WR Master mode).
The WR FSM is depicted in Figure~\ref{fig:wrFSM} and described in the rest of this section.
Successful completion of WR FSM results in the validation (\textit{wrModeON} set to TRUE)
of recommended WR mode (\textit{wrMode}) and WRPTP synchronization. If EXC\_TIMEOUT\_RETRY
(section \ref{sec:wrEventsAndConditions}) occurs, it means that WR Link Setup failed,
WRPTP synchronisation cannot be established and standard PTP is performed.
A typical flow of a complete WR Signaling Message exchange between a WR Slave and a WR Master
during WR Link Setup is presented in Appendix~\ref{ap:wr_lsu_flow}. For clarity, the cooperation of
PTP and WR state machines from power up is presented in Appendix~\ref{ap:ptpAndWrFSMS}.
......@@ -1653,9 +1669,9 @@ WR\_LINK\_ON & Upon entering this state by the WR Master, it sends WR\_LI
\textit{wrStateTimeout} shall be used.
After the timeout expires, the state is re-entered. A state can be re-entered for a maximum
number of \\
$n_{\{M\_LOCK, REQ\_CAL,CALIBed, PRESENT, S\_LOCK, LOCKED, RESP\_CALIB\_RESP\}}$ times defined
by \\wrStateRetry parameter (\ref{par:wrStateRetry}).
number of
$n_{\{M\_LOCK, REQ\_CAL,CALIBed, PRESENT, S\_LOCK, LOCKED, RESP\_CALIB\_RESP\}}$ \\
times defined by \\wrStateRetry parameter (\ref{par:wrStateRetry}).
\item[EXCEED TIMEOUT RETRIES] (abrv. EXC\_TIMEOUT\_RETRY) Indicates that the state
has been re-entered for a set number of times (wrStateRetry, \ref{par:wrStateRetry}) and
......@@ -1766,7 +1782,7 @@ in the local Data Set, as defined in Table~\ref{tab:outputWrCommWithHW}.
\begin{table}[tbp]
\caption{Input to hardware.}
\centering
\begin{tabular}{| p{3.4cm} | p{1.8cm} | p{4cm} | p{2cm} | p{3.2cm} |} \hline
\begin{tabular}{| p{3.4cm} | p{2cm} | p{4cm} | p{2cm} | p{3.2cm} |} \hline
\textbf{Hardware output}
&\textbf{Type}& \textbf{Evaluated} & \textbf{Evaluated by port} & \textbf{Action} \\
......@@ -1775,9 +1791,9 @@ HW\_CALIBRATED & event notification & in REQ\_CALIBRATION
WR~State & WR~Slave and WR~Master& $calibrated$ Data Set field is set to TRUE, consequently WR State Machine transition is triggered\\ \hline
HW\_LOCKED & even notification & in S\_LOCK~WR State & WR~Slave& Triggers transition in WR State Machine\\ \hline
HW\_LINK\_DOWN & even notification & always & WR~Slave and WR~Master & Set wrModeON to FALSE, and wrMode to NON\_WR \\ \hline
$deltaTx$ & UInteger64 & on reception of
$deltaTx$ & UInteger64~\footnotemark[4] & on reception of
HW\_CALIBRATED & WR~Slave and WR~Master& Save the value in deltaTx data field on evaluation\\ \hline
$deltaRx$ & UInteger64 & on reception of
$deltaRx$ & UInteger64~\footnotemark[4] & on reception of
HW\_CALIBRATED & WR~Slave and WR~Master& Save value in deltaTx data field on evaluation \\ \hline
% $t_{1}$ & Integer64 & on sending Sync message& WR~Master & Send in FollowUp (nanosecond part in correctionField)\\ \hline
% $t_{p2}$ & Integer64 & on receiving Sync message & WR~Slave & Save\\ \hline
......@@ -1789,6 +1805,9 @@ $deltaRx$ & UInteger64 & on reception of
\label{tab:outputWrCommWithHW}
\end{table}
\footnotetext[4]{The value of $\Delta_{tx_m,rx_s,rx_m,tx_s}$ measured in picoseconds and
multiplied by $2^{16}$.}
\addtocounter{footnote}{1}
\subsubsection{Re-establishing WR Link}
\label{sec:reestablishingWRLink}
......@@ -1960,59 +1979,80 @@ SLAVE & \small The port is synchronizing to the selected master po
\section{Sample White Rabbit Hardware Support Implementation}
\label{sec:sampleHW}
% \include{from_tomeks_msc}
%\subsection{Introduction}
\subsection{Measurement of fixed delays for Gigabit Ethernet over Optic Fiber}
\label{sec:calibForGigbitE}
A White Rabbit switch, described in Tomasz's Wlostowski Master Thesis \cite{tomekMSC},
implements WRPTP and WR Hardware Support for Gigabit Ethernet over fiber.
The most important fragments of the document are cited below (with necessary modifications).
The variation of $\Delta_{\{tx_m, rx_s, tx_s, rx_m\}}$ delays is often caused by
the PHY's serializer / deserializer (SerDes), phase locked loop (PLL) or clock and
data recovery circuitry (CDR). The delay on the PHY can be measured by detecting
the phase shift between SerDes I/O and Tx/Rx clock. Such methods can by applied to the
PHYs whose maximum ($\Delta_{max}$) and minimum ($\Delta_{min}$) delays are known
(provided in the datasheet) and the delay's variation is
\begin{equation}
\label{eq:fixedDelayVariation}
\Delta_{variable} \in \langle 0 : \Delta_{max} - \Delta_{min} \rangle
\end{equation}
e.g. below 10 bit times in case of Gigabit Ethernet.
Therefore, a fixed delay can be expressed as a sum of a constant value
($\Delta_{min}$) and a variable part ($\Delta_{variable}$) which needs to be measured:
\begin{equation}
\label{eq:fixedDelay}
\Delta_{\{tx_m, rx_s, tx_s, rx_m\}} = \Delta_{min\_\{tx_m, rx_s, tx_s, rx_m\}} + \Delta_{variable\_\{tx_m, rx_s, tx_s, rx_m\}}
\end{equation}
In White Rabbit, the measurement of fixed delay's variable part ($\Delta_{variable}$) is done by
sending a repeated pattern of five "0" and five "1" (0000011111) over Gigabit Ethernet.
Such signal creates a 125~MHz clock on the SerDes I/O. Since the Tx/Rx clock
frequency is 125~MHz, the phase shift between the SerDes I/O and the Tx/Rx
clocks is equal to $\Delta_{variable}$ of the PHY (see Figure~\ref{fig:wrCalibration}).
The repeated pattern of five "0" and five "1" is defined by the IEEE 802.3 standard \cite{IEEE802.3}
as \textit{Low-frequency test pattern} (Appendix~36A.2). It shall be generated in WR nodes
by a repeated transmission of RD+ K28.7 code-group.
\begin{figure}[ht!]
\centering
\includegraphics[width=0.60\textwidth]{fig/calibrate.ps}
\caption{Measurement of fixed delays $\Delta_{\{tx, rx\}}$ in Gigabit Ethernet-based WR node with
not fully-deterministic PHY.}
\label{fig:wrCalibration}
\end{figure}
% Figure \ref{fig:ptp_wr_flow} shows the order of the PTP message exchanges
% during all the phases of the synchronization process, indicating which
% messages are standard PTP (black) and WR-specific (red). The drawing is an overview of
% the entire WR-PTP synchronization flow described in below.
%
% \begin{figure}[htb]
% \centering
% \includegraphics[width=0.8\textwidth]{fig/tomeksDrawings/ptp_wr_flow.eps}
% \caption{PTP message flow during WR synchronization.}
% \label{fig:ptp_wr_flow}
% \end{figure}
Measurement of fixed delays for Gigabit Ethernet over optic fiber, and any other medium, is optional.
It is not needed if deterministic PHYs or internal FPGA transceivers which can be internally
characterized \cite{Peek2010} are used. In such case, the information about the fixed delays is
distributed across the link without preceding measurement.
\newpage
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%5
\input{from_tomeks_msc}
% \include{from_tomeks_msc}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Fine Delay Measurement}
\label{sec:FineDelayMeasurement}
% \subsection{Measurement of fixed delays for Gigabit Ethernet over Optic Fiber}
% \label{sec:calibForGigbitE}
%
% The variation of $\Delta_{\{tx_m, rx_s, tx_s, rx_m\}}$ delays is often caused by
% the PHY's serializer / deserializer (SerDes), phase locked loop (PLL) or clock and
% data recovery circuitry (CDR). The delay on the PHY can be measured by detecting
% the phase shift between SerDes I/O and Tx/Rx clock. Such methods can by applied to the
% PHYs whose maximum ($\Delta_{max}$) and minimum ($\Delta_{min}$) delays are known
% (provided in the datasheet) and the delay's variation is
% \begin{equation}
% \label{eq:fixedDelayVariation}
% \Delta_{variable} \in \langle 0 : \Delta_{max} - \Delta_{min} \rangle
% \end{equation}
% e.g. below 10 bit times in case of Gigabit Ethernet.
% Therefore, a fixed delay can be expressed as a sum of a constant value
% ($\Delta_{min}$) and a variable part ($\Delta_{variable}$) which needs to be measured:
% \begin{equation}
% \label{eq:fixedDelay}
% \Delta_{\{tx_m, rx_s, tx_s, rx_m\}} = \Delta_{min\_\{tx_m, rx_s, tx_s, rx_m\}} + \Delta_{variable\_\{tx_m, rx_s, tx_s, rx_m\}}
% \end{equation}
%
% In White Rabbit, the measurement of fixed delay's variable part ($\Delta_{variable}$) is done by
% sending a repeated pattern of five "0" and five "1" (0000011111) over Gigabit Ethernet.
% Such signal creates a 125~MHz clock on the SerDes I/O. Since the Tx/Rx clock
% frequency is 125~MHz, the phase shift between the SerDes I/O and the Tx/Rx
% clocks is equal to $\Delta_{variable}$ of the PHY (see Figure~\ref{fig:wrCalibration}).
%
%
% The repeated pattern of five "0" and five "1" is defined by the IEEE 802.3 standard \cite{IEEE802.3}
% as \textit{Low-frequency test pattern} (Appendix~36A.2). It shall be generated in WR nodes
% by a repeated transmission of RD+ K28.7 code-group.
%
%
% \begin{figure}[ht!]
% \centering
% \includegraphics[width=0.60\textwidth]{fig/calibrate.ps}
% \caption{Measurement of fixed delays $\Delta_{\{tx, rx\}}$ in Gigabit Ethernet-based WR node with
% not fully-deterministic PHY.}
% \label{fig:wrCalibration}
% \end{figure}
%
% Measurement of fixed delays for Gigabit Ethernet over optic fiber, and any other medium, is optional.
% It is not needed if deterministic PHYs or internal FPGA transceivers which can be internally
% characterized \cite{Peek2010} are used. In such case, the information about the fixed delays is
% distributed across the link without preceding measurement.
%
% \newpage
%
% \subsection{Fine Delay Measurement}
% \label{sec:FineDelayMeasurement}
\newpage
......@@ -2046,7 +2086,7 @@ distributed across the link without preceding measurement.
\section{Primitive data types}
\label{ap:wrDataTypes}
\begin{table}[tbp]
\begin{table}[ht!]
\caption{Primitive data types}
\centering
\begin{tabular}{| c | c |} \hline
......@@ -2061,11 +2101,213 @@ UInteger64 & 64-bit unsigned integer \\ \hline
\label{tab:wrPtpProfile}
\end{table}
\section{Computations using the two-step delay request-response mechanism with asymmetry correction}
\label{ap:computationsExplanation}
Quite a challenge
The method of incorporating asymmetry obtained using WR Link Model by the WR Slave
is WRPTP-implementation specific. Below, a summary of PTP offset ($<offsetFromMaster>$)
and mean delay ($<meanDelayPath>$) calculations are presented. They are followed by
two methods of including WR asymmetry, with the later being recommended.
The method used can vary between WR Slaves.
\subsection{Overview of PTP offset and mean path delay calculations}
\label{ap:ptpComputations}
[Citing \cite{IEEE1588}] \\
The two-step delay request-response for a boundary or ordinary clock,:
\begin{enumerate}
\item Sync message transmission (section 9.5.9 of \cite{IEEE1588}):
\begin{itemize}
\item The $<syncEventEgressTimestamp>$ ($t_1$) shall be generated upon
transmission of the Sync message.
\item The originTimestamp field of the Sync message shall be 0.
\item The correctionField of the Sync message shall be set to 0.
\end{itemize}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{align}
\label{eq:Sync_tx}
Sync.originTimestamp = 0 \\
Sync.correctionField = 0
\end{align}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\item Sync message reception (section 9.5.4 and 11.6.2 of \cite{IEEE1588}):
\begin{itemize}
\item The $t_2$ shall be generated upon reception of the Sync message.
\item The sync message correctionField shall be adjusted for asymmetry by adding the value of
the ingress path delayAsymmetry prior to its any use in a computation.
\end{itemize}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{align}
\label{eq:Sync_rx}
Sync.correctionField = delayAsymmetry
\end{align}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\item Follow\_Up message transmission (section 9.5.10 of \cite{IEEE1588}):
\begin{itemize}
\item The preciseOriginTimestamp field of the Follow\_Up should be \\
the $<syncEventEgressTimestamp>$ of the associated Sync message excluding
any fractional nanoseconds of the associated Sync message.
\item The correctionField field of the Follow\_Up shall be the fractional nanoseconds part of
the $<syncEventEgressTimestamp>$ of the associated Sync message.
\end{itemize}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{align}
\label{eq:follow_up_tx}
Follow\_Up.preciseOriginTimestamp &= seconds\_and\_nanoseconds(t_1)\\
Follow\_Up.correctionField &= fractional\_ns\_part(t_1)\\
<syncEventEgressTimestamp>= t_1 &= Follow\_Up.preciseOriginTimestamp \\
\nonumber &+ Follow\_Up.correctionField
\end{align}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\item Delay\_Req message transmission (section 11.6.3 and 11.3.2 of \cite{IEEE1588}):
\begin{itemize}
\item Prior to transmission on an egress port the correctionField of
the Delay\_Req message shall be modified by subtracting the value of the egress
path delayAsymmetry from its correctionField.
\item The $t_3$ timestamp shall be generated upon transmission of the Delay\_Req message.
\end{itemize}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{align}
\label{eq:follow_up_rx}
Delay\_Req.correctionField &= -delayAsymmetry \\
Delay\_Req.originTimestamp &= 0
\end{align}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\item Delay\_Req message reception (section 9.5.6 of \cite{IEEE1588}):
\begin{itemize}
\item The $<delayReqEventIngressTimestamp>$ ($t_4$)
shall be generated upon receipt of the Delay\_Req message.
\end{itemize}
\item Delay\_Resp message transmission (section 9.5.12 and 11.3.2 of \cite{IEEE1588}):
\begin{itemize}
\item The receiveTimestamp field of the Delay\_Resp message shall be set to the seconds and
nanoseconds portion of the time $t_4$.
\item The correctionField of the Delay\_Req message shall be set to 0 and then
the correctionField of the Delay\_Resp message shall be added to it and
the fractional nanoseconds portion of $t_4$ shall be subtracted from the
corrctionField of Delay\_Resp message.
\end{itemize}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{align}
\label{eq:delay_resp_tx}
Delay\_Resp.correctionField &= Delay\_Req.correctionField \\
&- fractional\_ns\_part(t_4)\\
\nonumber &= -(delayAsymmetry + fractional\_ns\_part(t_4)) \\
Delay\_Resp.receiveTimestamp &= seconds\_and\_nanoseconds(t_4)
\end{align}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\item Delay\_Resp message reception (section 11.3.2 of \cite{IEEE1588}):
\begin{itemize}
\item The $<meanPathDelay>$ shall be computed as follows
\end{itemize}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{align}
\label{eq:meanPathDelay}
<meanPathDelay> &=[(t_2 - t_3) \\
\nonumber &+ (Delay\_Resp.receiveTimestamp \\
\nonumber &- Follow\_Up.preciseOeriginTrimestamp)\\
\nonumber &- Sync.correctionField \\
\nonumber &- Follow\_Up.correctionField \\
\nonumber &- Delay\_Resp.correctionField]/2
\end{align}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\item Computation of the clock offset (section 11.2 of \cite{IEEE1588}):
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{align}
\label{eq:offset}
<offsetFromMaster> &=t_2 \\
\nonumber &- Follow\_Up.preciseOriginTimestamp \\
\nonumber &- <meanPathDelay> \\
\nonumber &- Sync.correctionField \\
\nonumber &- Follow\_Up.correctionField
\end{align}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\end{enumerate}
\subsection{WR asymmetry as PTP communication path asymmetry}
The asymmetry obtained using WR Link Model ($asymmetry$, section \ref{sec:delayAsymCal})
can be seen as a communication path asymmetry $delayAsymmetry$ as defined in 7.4.2
of \cite{IEEE1588}
\begin{equation}
\label{eq:ptpAsym}
delayAsymmetry= asymmetry
\end{equation}
and incorporated into the PTP calculations as described in Appendix~\ref{ap:ptpComputations},
equations \eqref{eq:Sync_rx} and \eqref{eq:follow_up_rx}.
\subsubsection{Solution for Ethernet over a Single-mode Optical Fiber}
In case of the solution for Ethernet over a single-mode Optic Fiber
(section\ref{sec:EthernetOverSingleModeFiber}), it can be calculated using directly
the equation~\eqref{eq:aqasymm}, where $\mu$ is $<meanDelayPath>$ obtained using
equation~\eqref{eq:meanPathDelay}:
\begin{equation}
\label{eq:delayAsymmetry}
delayAsymmetry= \Delta_{tx_m} + \Delta_{rx_s} - \frac{\Delta - \alpha * <meanDelayPath>
+ \alpha * \Delta}{2 + \alpha}
\end{equation}
It needs to be noted, that the $delayAsymmetry$ used in calculation of $<meanDelayPath>$ and
$<offsetFromMaster>$ is computed based on a previous measurement of the $<meanDelayPath>$.
This is because the standard \cite{IEEE1588} seems to assume that, if available, the
$delayAsymmetry$ is constant and known in advance.
Therefore, a direct incorporation of the asymmetry calculated using WR Link Model into
$<meanDelayPath>$ and $<offsetFromMaster>$ is recommended.
\subsection{Direct WR asymmetry incorporation into PTP computations}
The asymmetry obtained using WR Link Model ($asymmetry$, section \ref{sec:delayAsymCal})
can be incorporated directly into the computation
of $<meanDelayPath>$ and $<offsetFromMaster>$. In such case, the $delayAsymmetry$ as defined
in 7.4.2 of \cite{IEEE1588}, is set to be 0 (equations \eqref{eq:Sync_rx} and
\eqref{eq:follow_up_rx}). The $<meanDelayPath>$ value is calculated using \eqref{eq:meanPathDelay}
and corrected with $asymmetry$ to obtain $<pathDelay_{MS}>$
\begin{equation}
\label{eq:pathDelayMS}
<pathDelay_{MS}>= <meanDelayPath> + asymmetry
\end{equation}
which is used to compute $<offsetFromMaster>$ using \eqref{eq:offset}:
\begin{align}
\label{eq:WRoffset}
<offsetFromMaster> &=t_2 \\
\nonumber &- Follow\_Up.preciseOriginTimestamp \\
\nonumber &- <pathDelay_{MS}> \\
\nonumber &- 0 \\
\nonumber &- Follow\_Up.correctionField \\
&=t_{2}-t_1 - <pathDelay_{MS}>
\end{align}
\subsubsection{Solution for Ethernet over a Single-mode Optical Fiber}
A WR Slave, which assumed communication path asymmetry to be 0 ($delayAsymmetry=0$) and measured
timestamps $t_2$ and $t_3$, can calculate the timestamps measured by the WR Master
and send with PTP messages as follows:
\begin{align}
\label{eq:t1}
t_1 &= Follow\_Up.preciseOriginTimestamp \\
\nonumber &+ Follow\_Up.correctionField
\end{align}
and
\begin{align}
\label{eq:t4}
t_{4} &= Delay\_Resp.receiveTimestamp \\
\nonumber &- Delay\_Resp.correctionField
\end{align}
Having all timestamps ($t_1$, $t_2$, $t_3$, $t_4$), the fixed delays
($\Delta_{txm}$,$\Delta_{rxs}$, $\Delta_{txs}$, $\Delta_{rxm}$) and relative delay coefficient
($\alpha$), the WR Link Model can be combined with PTP computation to obtain directly the
correct values of $<delayPath_{MS}>$ and $<offsetFromMaster>$ :
\begin{eqnarray}
<delayPath_{MS}> & = & \frac{1+\alpha}{2+\alpha}
[(t_4-t_1) + (t_3-t_2) - \Delta] + \Delta_{txm} + \Delta_{rxs} \\
<offsetFromMaster> & = & t_{2} - t_{1} - <delayPath_{MS}>
\end{eqnarray}
where
\begin{eqnarray}
\Delta & = & \Delta_{txm} + \Delta_{rxs} + \Delta_{txs} + \Delta_{rxm}
\end{eqnarray}
\newpage
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......
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