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White Rabbit Standardization
Commit edbb5e54 authored by Maciej Lipinski's avatar Maciej Lipinski
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wrspec: cleaning before moving to wr-std repo

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TODO:
- authors
- change format to A4
- wr bountry clock/ordinary clock/switch
Figure~\ref{fig:hybrid-network} depicts the topology of a \emph{hybrid}
WR/IEEE1588 network.
White Rabbit adds to PTP a mechanism (called \textit{White Rabbit Link Setup})
which enables to obtain the value of delay asymmetry.
The mechanism is active only at the beginning of each WR-to-WR node connection.
\subsubsection{wrPortMode}
TODO ?
\subsubsection{calibrated}
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\subsubsection{deltaTx}
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\subsubsection{deltaRx}
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\subsubsection{calPeriod}
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\subsubsection{calPattern}
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\subsubsection{calPatternLen}
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\subsubsection{wrMode}
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\subsubsection{wrAlpha}
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\subsubsection{grandmasterWrPortMode}
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\subsubsection{grandmasterDeltaTx}
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\subsubsection{grandmasterDeltaRx}
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\subsubsection{grandmasterWrMode}
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where the parentDS with index 0 is used as
parentDS defined in
the standard, the parentDS with index 1 and greater are used to store information about
backup sources of timing information, updated as defined by modified BMC, used by
platform-specific hardware support for topology redundancy.
==============================
It can be noted that if $\Delta << \mu$, the above equation can be simplified:
\begin{equation}
\label{eq:aqasymmSympl}
\eqasymm = \Delta_{tx_m} + \Delta_{rx_s} - \frac{\Delta - \alpha \mu}{2 + \alpha}
\end{equation}.
=============================
IEEE1588 standard allows its custamisation by the means of PTP profile which specifies set of
required and prohibited options as well as ranges and defaults of configurations. WRPTP takes a
full advantage of PTP profile defining WR TLVs, modification to Best Master Clock algorithm and
default attribut values.
=============================
\begin{table}[ph!]
\caption{WRPTP Data Sets fields}
\centering
\begin{tabular}{| c | p{2.0cm} | p{2.5cm} | p{1.5cm} | p{4cm}
|} \hline
\textbf{DS member} & \textbf{DS name}&\textbf{Values}& \textbf{D}ynamic or \textbf{S}tatic &
\textbf{Description}
\\
& & & &
\\ \hline
portWrConfig & portDS & NON\_WR,
WR\_S\_ONLY,
WR\_M\_ONLY
WR\_M\_AND\_S &S & Determines predefined
function of WR port
(static).\\ \hline
portCalibrated & portDS & TRUE, FALSE &D & Indicates whether fixed
delays of the given port
are known.\\ \hline
deltaTx & portDS & 64 bit value &D & Port's $\Delta_{tx}$
measured in picoseconds
and multiplied by
${2^{16}}$.\\ \hline
deltaRx & portDS & 64 bit value &D & Port's $\Delta_{rx}$
measured in picoseconds
and multiplied by
${2^{16}}$.\\ \hline
calPeriod & portDS & 32 bit value &S & Calibration period in
microseconds. \\ \hline
calPattern & portDS & 32 bit value &S & Medium specific
calibration pattern.
\\ \hline
calPatternLen & portDS & 16 bit value &S & Number of bits of
calPattern to be
repeated.\\ \hline
portWrMode & portDS & TRUE, FALSE &D & If TRUE, the port is
working in WR mode.
\\ \hline
wrAlpha & portDS & 32 bit value &S & \textit{Medium
correlation parameter} as
described in
section~\ref{sec:singlefiber}.
\\ \hline
parentPortWrConfig & portDS & NON\_WR,
WR\_S\_ONLY,
WR\_M\_ONLY
WR\_M\_AND\_S &D & Determines predefined
function of the PTP
parent.\\ \hline
parentPortDeltaTx & portDS & 64 bit value &D & Parent's
$\Delta_{tx}$ measured
in picoseconds and
multiplied by
${2^{16}}$. \\ \hline
parentPortDeltaRx & portDS & 64 bit value &D & Parent's
$\Delta_{rx}$ measured in
picoseconds and multiplied
by ${2^{16}}$. \\ \hline
parentPortWrMode & portDS & TRUE, FALSE &D & If TRUE, the parent port
is working in WR mode.
\\ \hline
primarySlavePortNumber & currentDS & 16 bits value &D & If 0, no
primary Slave is
selected. 1, 2 ,...N-value
of portNumber (clause
7.5.2.3 PTP), selected as
primary Slave.
\\ \hline
\end{tabular}
\label{tab:wrDS}
\end{table}
=============================
Hardware implementation of WR-Slave-enable port is much more complex then the implementation of
WR-Master-enabled port, while the usual number of ports acting as slaves in a WR Boundary
Clock is foreseen to be two or one (out of around 18 total). Therefore, it is justified to introduce
MasterOnly PTP state machine. Such solution enables to develop WR Boundary Clocks which implement
hardware support for Slave only on chose ports\footnote{This is the case of V2 of WR Switch. V3
WR Switch will enable all ports to act as Slaves}. A port running in MasterOnly mode can act only as
a source of timing information (so-called downlink). The MasterOnly PTP state machine is presented
in Figure~\ref{fig:ptpFSMmasterOnly}.
In case when SlaveOnly port is needed, the SlaveOnly PTP state machine defined in Figure~24 in PTP
standard is used (see Appendix~\ref{ptpFSM}, Figure~\ref{fig:ptpFSMslaveOnly}).
\begin{figure}[ht!]
\centering
\includegraphics[width=0.85\textwidth]{fig/ptpFSMmasterOnly.ps}
\caption{MasterOnly PTP state machine.}
\label{fig:ptpFSMmasterOnly}
\end{figure}
=============================
This pattern is defined by the IEEE 802.3 standard \cite{} as \textit{Low-frequency text pattern}
(Appendix~36A.2). It can be generated by the repeated transmission of K28.7 code-group.
=============================
Implementation of the method to obtain fixed delays for non-deterministic Gigabit
Ethernet PHY
is described in Appendix~\ref{sec:calibForGigbitE}. This fixed delay measurement is optional and in
principle needed only once, while the WR link is being set up.
==============================
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