Functional changes/problems:
- Output delay has different resolution (not sure about max value)
- Minimal frequency of MMCM reference clock is ~14 MHz. Can't be used in ext_pll


Alarmin warnings:

	[Timing 38-316] Clock period '16.000' specified during out-of-context synthesis of instance 'phy_block.phys' at clock pin 'rxusrclk2_in[0]' is different from the actual clock period '4.000', this can lead to different synthesis results.

	[Synth 8-3352] multi-driven net \rsp_o[18][port_mask] [0] with 1st driver pin 'U_Real_Top/gen_network_stuff.U_Nic/U_TX_FSM/cur_tx_desc_reg[dpm][18]/Q' ["/home/gumas/projects/cti/wr/wrs_evaluation/wr-switch-hdl/ip_cores/wr-cores-local/modules/wr_nic/nic_tx_fsm.vhd":186]

	[Synth 8-3352] multi-driven net O915[17] with 1st driver pin 'i_102136/O' ["/home/gumas/projects/cti/wr/wrs_evaluation/wr-switch-hdl/modules/wrsw_psu/psu_announce_snooper.vhd":188]
