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-- Title          : Wishbone slave core for Routing Table Unit (RTU)
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-- File           : rtu_wishbone_slave.vhd
-- Author         : auto-generated by wbgen2 from rtu_wishbone_slave_new.wb
-- Created        : Mon Aug  5 16:03:51 2013
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu_wishbone_slave_new.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;

use work.rtu_wbgen2_pkg.all;


entity rtu_wishbone_slave is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(8 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    wb_int_o                                 : out    std_logic;
    clk_match_i                              : in     std_logic;
-- Ports for RAM: Aging bitmap for main hashtable
    rtu_aram_addr_i                          : in     std_logic_vector(7 downto 0);
-- Read data output
    rtu_aram_data_o                          : out    std_logic_vector(31 downto 0);
-- Read strobe input (active high)
    rtu_aram_rd_i                            : in     std_logic;
-- Write data input
    rtu_aram_data_i                          : in     std_logic_vector(31 downto 0);
-- Write strobe (active high)
    rtu_aram_wr_i                            : in     std_logic;
    irq_nempty_i                             : in     std_logic;
    regs_i                                   : in     t_rtu_in_registers;
    regs_o                                   : out    t_rtu_out_registers
  );
end rtu_wishbone_slave;

architecture syn of rtu_wishbone_slave is

signal rtu_gcr_g_ena_int                        : std_logic      ;
signal rtu_gcr_g_ena_sync0                      : std_logic      ;
signal rtu_gcr_g_ena_sync1                      : std_logic      ;
signal rtu_gcr_mfifotrig_int_read               : std_logic      ;
signal rtu_gcr_mfifotrig_int_write              : std_logic      ;
signal rtu_gcr_mfifotrig_lw                     : std_logic      ;
signal rtu_gcr_mfifotrig_lw_delay               : std_logic      ;
signal rtu_gcr_mfifotrig_lw_read_in_progress    : std_logic      ;
signal rtu_gcr_mfifotrig_lw_s0                  : std_logic      ;
signal rtu_gcr_mfifotrig_lw_s1                  : std_logic      ;
signal rtu_gcr_mfifotrig_lw_s2                  : std_logic      ;
signal rtu_gcr_mfifotrig_rwsel                  : std_logic      ;
signal rtu_gcr_poly_val_int                     : std_logic_vector(15 downto 0);
signal rtu_gcr_poly_val_swb                     : std_logic      ;
signal rtu_gcr_poly_val_swb_delay               : std_logic      ;
signal rtu_gcr_poly_val_swb_s0                  : std_logic      ;
signal rtu_gcr_poly_val_swb_s1                  : std_logic      ;
signal rtu_gcr_poly_val_swb_s2                  : std_logic      ;
signal rtu_psr_port_sel_int                     : std_logic_vector(7 downto 0);
signal rtu_vtr1_vid_int                         : std_logic_vector(11 downto 0);
signal rtu_vtr1_fid_int                         : std_logic_vector(7 downto 0);
signal rtu_vtr1_drop_int                        : std_logic      ;
signal rtu_vtr1_has_prio_int                    : std_logic      ;
signal rtu_vtr1_prio_override_int               : std_logic      ;
signal rtu_vtr1_prio_int                        : std_logic_vector(2 downto 0);
signal rtu_vtr1_update_dly0                     : std_logic      ;
signal rtu_vtr1_update_int                      : std_logic      ;
signal rtu_vtr2_port_mask_int                   : std_logic_vector(31 downto 0);
signal rtu_ufifo_rst_n                          : std_logic      ;
signal rtu_ufifo_in_int                         : std_logic_vector(120 downto 0);
signal rtu_ufifo_out_int                        : std_logic_vector(120 downto 0);
signal rtu_ufifo_rdreq_int                      : std_logic      ;
signal rtu_ufifo_rdreq_int_d0                   : std_logic      ;
signal rtu_mfifo_rst_n                          : std_logic      ;
signal rtu_mfifo_in_int                         : std_logic_vector(32 downto 0);
signal rtu_mfifo_out_int                        : std_logic_vector(32 downto 0);
signal rtu_mfifo_wrreq_int                      : std_logic      ;
signal rtu_rx_ctr_ff_mac_br_int                 : std_logic      ;
signal rtu_rx_ctr_ff_mac_range_int              : std_logic      ;
signal rtu_rx_ctr_ff_mac_single_int             : std_logic      ;
signal rtu_rx_ctr_ff_mac_ll_int                 : std_logic      ;
signal rtu_rx_ctr_ff_mac_ptp_int                : std_logic      ;
signal rtu_rx_ctr_mr_ena_int                    : std_logic      ;
signal rtu_rx_ctr_at_fmatch_too_slow_int        : std_logic      ;
signal rtu_rx_ctr_prio_mask_int                 : std_logic_vector(7 downto 0);
signal rtu_rx_ctr_hp_fw_cpu_ena_int             : std_logic      ;
signal rtu_rx_ctr_urec_fw_cpu_ena_int           : std_logic      ;
signal rtu_rx_ctr_learn_dst_ena_int             : std_logic      ;
signal rtu_rx_ctr_force_fast_match_ena_int      : std_logic      ;
signal rtu_rx_ctr_force_full_match_ena_int      : std_logic      ;
signal rtu_rx_ff_mac_r0_lo_int                  : std_logic_vector(31 downto 0);
signal rtu_rx_ff_mac_r1_type_int                : std_logic      ;
signal rtu_rx_ff_mac_r1_valid_int               : std_logic      ;
signal rtu_rx_mp_r0_dst_src_int                 : std_logic      ;
signal rtu_rx_mp_r0_rx_tx_int                   : std_logic      ;
signal rtu_rx_mp_r0_mask_id_int                 : std_logic_vector(15 downto 0);
signal rtu_aram_rddata_int                      : std_logic_vector(31 downto 0);
signal rtu_aram_rd_int                          : std_logic      ;
signal rtu_aram_wr_int                          : std_logic      ;
signal eic_idr_int                              : std_logic_vector(0 downto 0);
signal eic_idr_write_int                        : std_logic      ;
signal eic_ier_int                              : std_logic_vector(0 downto 0);
signal eic_ier_write_int                        : std_logic      ;
signal eic_imr_int                              : std_logic_vector(0 downto 0);
signal eic_isr_clear_int                        : std_logic_vector(0 downto 0);
signal eic_isr_status_int                       : std_logic_vector(0 downto 0);
signal eic_irq_ack_int                          : std_logic_vector(0 downto 0);
signal eic_isr_write_int                        : std_logic      ;
signal rtu_ufifo_empty_int                      : std_logic      ;
signal rtu_ufifo_usedw_int                      : std_logic_vector(6 downto 0);
signal rtu_mfifo_full_int                       : std_logic      ;
signal rtu_mfifo_empty_int                      : std_logic      ;
signal rtu_mfifo_usedw_int                      : std_logic_vector(5 downto 0);
signal irq_inputs_vector_int                    : std_logic_vector(0 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(8 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      rtu_gcr_g_ena_int <= '0';
      rtu_gcr_mfifotrig_lw <= '0';
      rtu_gcr_mfifotrig_lw_delay <= '0';
      rtu_gcr_mfifotrig_lw_read_in_progress <= '0';
      rtu_gcr_mfifotrig_rwsel <= '0';
      rtu_gcr_mfifotrig_int_write <= '0';
      rtu_gcr_poly_val_int <= "0000000000000000";
      rtu_gcr_poly_val_swb <= '0';
      rtu_gcr_poly_val_swb_delay <= '0';
      rtu_psr_port_sel_int <= "00000000";
      regs_o.pcr_learn_en_load_o <= '0';
      regs_o.pcr_pass_all_load_o <= '0';
      regs_o.pcr_pass_bpdu_load_o <= '0';
      regs_o.pcr_fix_prio_load_o <= '0';
      regs_o.pcr_prio_val_load_o <= '0';
      regs_o.pcr_b_unrec_load_o <= '0';
      rtu_vtr1_vid_int <= "000000000000";
      rtu_vtr1_fid_int <= "00000000";
      rtu_vtr1_drop_int <= '0';
      rtu_vtr1_has_prio_int <= '0';
      rtu_vtr1_prio_override_int <= '0';
      rtu_vtr1_prio_int <= "000";
      rtu_vtr1_update_int <= '0';
      rtu_vtr2_port_mask_int <= "00000000000000000000000000000000";
      rtu_rx_ctr_ff_mac_br_int <= '0';
      rtu_rx_ctr_ff_mac_range_int <= '0';
      rtu_rx_ctr_ff_mac_single_int <= '0';
      rtu_rx_ctr_ff_mac_ll_int <= '0';
      rtu_rx_ctr_ff_mac_ptp_int <= '0';
      rtu_rx_ctr_mr_ena_int <= '0';
      rtu_rx_ctr_at_fmatch_too_slow_int <= '0';
      rtu_rx_ctr_prio_mask_int <= "00000000";
      rtu_rx_ctr_hp_fw_cpu_ena_int <= '0';
      rtu_rx_ctr_urec_fw_cpu_ena_int <= '0';
      rtu_rx_ctr_learn_dst_ena_int <= '0';
      rtu_rx_ctr_force_fast_match_ena_int <= '0';
      rtu_rx_ctr_force_full_match_ena_int <= '0';
      rtu_rx_ff_mac_r0_lo_int <= "00000000000000000000000000000000";
      regs_o.rx_ff_mac_r1_hi_id_load_o <= '0';
      regs_o.rx_ff_mac_r1_id_load_o <= '0';
      rtu_rx_ff_mac_r1_type_int <= '0';
      rtu_rx_ff_mac_r1_valid_int <= '0';
      rtu_rx_mp_r0_dst_src_int <= '0';
      rtu_rx_mp_r0_rx_tx_int <= '0';
      rtu_rx_mp_r0_mask_id_int <= "0000000000000000";
      regs_o.rx_mp_r1_mask_load_o <= '0';
      eic_idr_write_int <= '0';
      eic_ier_write_int <= '0';
      eic_isr_write_int <= '0';
      rtu_ufifo_rdreq_int <= '0';
      rtu_mfifo_wrreq_int <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          regs_o.pcr_learn_en_load_o <= '0';
          regs_o.pcr_pass_all_load_o <= '0';
          regs_o.pcr_pass_bpdu_load_o <= '0';
          regs_o.pcr_fix_prio_load_o <= '0';
          regs_o.pcr_prio_val_load_o <= '0';
          regs_o.pcr_b_unrec_load_o <= '0';
          rtu_vtr1_update_int <= '0';
          regs_o.rx_ff_mac_r1_hi_id_load_o <= '0';
          regs_o.rx_ff_mac_r1_id_load_o <= '0';
          regs_o.rx_mp_r1_mask_load_o <= '0';
          eic_idr_write_int <= '0';
          eic_ier_write_int <= '0';
          eic_isr_write_int <= '0';
          rtu_mfifo_wrreq_int <= '0';
          ack_in_progress <= '0';
        else
          rtu_gcr_mfifotrig_lw <= rtu_gcr_mfifotrig_lw_delay;
          rtu_gcr_mfifotrig_lw_delay <= '0';
          if ((ack_sreg(1) = '1') and (rtu_gcr_mfifotrig_lw_read_in_progress = '1')) then
            rddata_reg(1) <= rtu_gcr_mfifotrig_int_read;
            rtu_gcr_mfifotrig_lw_read_in_progress <= '0';
          end if;
          rtu_gcr_poly_val_swb <= rtu_gcr_poly_val_swb_delay;
          rtu_gcr_poly_val_swb_delay <= '0';
          regs_o.pcr_learn_en_load_o <= '0';
          regs_o.pcr_pass_all_load_o <= '0';
          regs_o.pcr_pass_bpdu_load_o <= '0';
          regs_o.pcr_fix_prio_load_o <= '0';
          regs_o.pcr_prio_val_load_o <= '0';
          regs_o.pcr_b_unrec_load_o <= '0';
          regs_o.rx_ff_mac_r1_hi_id_load_o <= '0';
          regs_o.rx_ff_mac_r1_id_load_o <= '0';
          regs_o.rx_mp_r1_mask_load_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(8) is
          when '0' => 
            case rwaddr_reg(4 downto 0) is
            when "00000" => 
              if (wb_we_i = '1') then
                rtu_gcr_g_ena_int <= wrdata_reg(0);
                rtu_gcr_mfifotrig_int_write <= wrdata_reg(1);
                rtu_gcr_mfifotrig_lw <= '1';
                rtu_gcr_mfifotrig_lw_delay <= '1';
                rtu_gcr_mfifotrig_lw_read_in_progress <= '0';
                rtu_gcr_mfifotrig_rwsel <= '1';
                rtu_gcr_poly_val_int <= wrdata_reg(23 downto 8);
                rtu_gcr_poly_val_swb <= '1';
                rtu_gcr_poly_val_swb_delay <= '1';
              end if;
              rddata_reg(0) <= rtu_gcr_g_ena_int;
              if (wb_we_i = '0') then
                rddata_reg(1) <= 'X';
                rtu_gcr_mfifotrig_lw <= '1';
                rtu_gcr_mfifotrig_lw_delay <= '1';
                rtu_gcr_mfifotrig_lw_read_in_progress <= '1';
                rtu_gcr_mfifotrig_rwsel <= '0';
              end if;
              rddata_reg(23 downto 8) <= rtu_gcr_poly_val_int;
              rddata_reg(27 downto 24) <= regs_i.gcr_rtu_version_i;
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(5) <= '1';
              ack_in_progress <= '1';
            when "00001" => 
              if (wb_we_i = '1') then
                rtu_psr_port_sel_int <= wrdata_reg(7 downto 0);
              end if;
              rddata_reg(7 downto 0) <= rtu_psr_port_sel_int;
              rddata_reg(15 downto 8) <= regs_i.psr_n_ports_i;
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "00010" => 
              if (wb_we_i = '1') then
                regs_o.pcr_learn_en_load_o <= '1';
                regs_o.pcr_pass_all_load_o <= '1';
                regs_o.pcr_pass_bpdu_load_o <= '1';
                regs_o.pcr_fix_prio_load_o <= '1';
                regs_o.pcr_prio_val_load_o <= '1';
                regs_o.pcr_b_unrec_load_o <= '1';
              end if;
              rddata_reg(0) <= regs_i.pcr_learn_en_i;
              rddata_reg(1) <= regs_i.pcr_pass_all_i;
              rddata_reg(2) <= regs_i.pcr_pass_bpdu_i;
              rddata_reg(3) <= regs_i.pcr_fix_prio_i;
              rddata_reg(6 downto 4) <= regs_i.pcr_prio_val_i;
              rddata_reg(7) <= regs_i.pcr_b_unrec_i;
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "00011" => 
              if (wb_we_i = '1') then
                rtu_vtr1_vid_int <= wrdata_reg(11 downto 0);
                rtu_vtr1_fid_int <= wrdata_reg(19 downto 12);
                rtu_vtr1_drop_int <= wrdata_reg(20);
                rtu_vtr1_has_prio_int <= wrdata_reg(21);
                rtu_vtr1_prio_override_int <= wrdata_reg(22);
                rtu_vtr1_prio_int <= wrdata_reg(25 downto 23);
                rtu_vtr1_update_int <= wrdata_reg(26);
              end if;
              rddata_reg(11 downto 0) <= rtu_vtr1_vid_int;
              rddata_reg(19 downto 12) <= rtu_vtr1_fid_int;
              rddata_reg(20) <= rtu_vtr1_drop_int;
              rddata_reg(21) <= rtu_vtr1_has_prio_int;
              rddata_reg(22) <= rtu_vtr1_prio_override_int;
              rddata_reg(25 downto 23) <= rtu_vtr1_prio_int;
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(2) <= '1';
              ack_in_progress <= '1';
            when "00100" => 
              if (wb_we_i = '1') then
                rtu_vtr2_port_mask_int <= wrdata_reg(31 downto 0);
              end if;
              rddata_reg(31 downto 0) <= rtu_vtr2_port_mask_int;
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "00101" => 
              if (wb_we_i = '1') then
                rtu_rx_ctr_ff_mac_br_int <= wrdata_reg(0);
                rtu_rx_ctr_ff_mac_range_int <= wrdata_reg(1);
                rtu_rx_ctr_ff_mac_single_int <= wrdata_reg(2);
                rtu_rx_ctr_ff_mac_ll_int <= wrdata_reg(3);
                rtu_rx_ctr_ff_mac_ptp_int <= wrdata_reg(4);
                rtu_rx_ctr_mr_ena_int <= wrdata_reg(5);
                rtu_rx_ctr_at_fmatch_too_slow_int <= wrdata_reg(6);
                rtu_rx_ctr_prio_mask_int <= wrdata_reg(15 downto 8);
                rtu_rx_ctr_hp_fw_cpu_ena_int <= wrdata_reg(16);
                rtu_rx_ctr_urec_fw_cpu_ena_int <= wrdata_reg(17);
                rtu_rx_ctr_learn_dst_ena_int <= wrdata_reg(18);
                rtu_rx_ctr_force_fast_match_ena_int <= wrdata_reg(24);
                rtu_rx_ctr_force_full_match_ena_int <= wrdata_reg(25);
              end if;
              rddata_reg(0) <= rtu_rx_ctr_ff_mac_br_int;
              rddata_reg(1) <= rtu_rx_ctr_ff_mac_range_int;
              rddata_reg(2) <= rtu_rx_ctr_ff_mac_single_int;
              rddata_reg(3) <= rtu_rx_ctr_ff_mac_ll_int;
              rddata_reg(4) <= rtu_rx_ctr_ff_mac_ptp_int;
              rddata_reg(5) <= rtu_rx_ctr_mr_ena_int;
              rddata_reg(6) <= rtu_rx_ctr_at_fmatch_too_slow_int;
              rddata_reg(15 downto 8) <= rtu_rx_ctr_prio_mask_int;
              rddata_reg(16) <= rtu_rx_ctr_hp_fw_cpu_ena_int;
              rddata_reg(17) <= rtu_rx_ctr_urec_fw_cpu_ena_int;
              rddata_reg(18) <= rtu_rx_ctr_learn_dst_ena_int;
              rddata_reg(24) <= rtu_rx_ctr_force_fast_match_ena_int;
              rddata_reg(25) <= rtu_rx_ctr_force_full_match_ena_int;
              rddata_reg(7) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "00110" => 
              if (wb_we_i = '1') then
                rtu_rx_ff_mac_r0_lo_int <= wrdata_reg(31 downto 0);
              end if;
              rddata_reg(31 downto 0) <= rtu_rx_ff_mac_r0_lo_int;
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "00111" => 
              if (wb_we_i = '1') then
                regs_o.rx_ff_mac_r1_hi_id_load_o <= '1';
                regs_o.rx_ff_mac_r1_id_load_o <= '1';
                rtu_rx_ff_mac_r1_type_int <= wrdata_reg(24);
                rtu_rx_ff_mac_r1_valid_int <= wrdata_reg(25);
              end if;
              rddata_reg(15 downto 0) <= regs_i.rx_ff_mac_r1_hi_id_i;
              rddata_reg(23 downto 16) <= regs_i.rx_ff_mac_r1_id_i;
              rddata_reg(24) <= rtu_rx_ff_mac_r1_type_int;
              rddata_reg(25) <= rtu_rx_ff_mac_r1_valid_int;
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "01000" => 
              if (wb_we_i = '1') then
              end if;
              rddata_reg(31 downto 0) <= regs_i.cpu_port_mask_i;
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "01001" => 
              if (wb_we_i = '1') then
                rtu_rx_mp_r0_dst_src_int <= wrdata_reg(0);
                rtu_rx_mp_r0_rx_tx_int <= wrdata_reg(1);
                rtu_rx_mp_r0_mask_id_int <= wrdata_reg(31 downto 16);
              end if;
              rddata_reg(0) <= rtu_rx_mp_r0_dst_src_int;
              rddata_reg(1) <= rtu_rx_mp_r0_rx_tx_int;
              rddata_reg(31 downto 16) <= rtu_rx_mp_r0_mask_id_int;
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "01010" => 
              if (wb_we_i = '1') then
                regs_o.rx_mp_r1_mask_load_o <= '1';
              end if;
              rddata_reg(31 downto 0) <= regs_i.rx_mp_r1_mask_i;
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "10000" => 
              if (wb_we_i = '1') then
                eic_idr_write_int <= '1';
              end if;
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "10001" => 
              if (wb_we_i = '1') then
                eic_ier_write_int <= '1';
              end if;
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "10010" => 
              if (wb_we_i = '1') then
              end if;
              rddata_reg(0) <= eic_imr_int(0);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "10011" => 
              if (wb_we_i = '1') then
                eic_isr_write_int <= '1';
              end if;
              rddata_reg(0) <= eic_isr_status_int(0);
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "10100" => 
              if (wb_we_i = '1') then
              end if;
              if (rtu_ufifo_rdreq_int_d0 = '0') then
                rtu_ufifo_rdreq_int <= not rtu_ufifo_rdreq_int;
              else
                rddata_reg(31 downto 0) <= rtu_ufifo_out_int(31 downto 0);
                ack_in_progress <= '1';
                ack_sreg(0) <= '1';
              end if;
            when "10101" => 
              if (wb_we_i = '1') then
              end if;
              rddata_reg(15 downto 0) <= rtu_ufifo_out_int(47 downto 32);
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "10110" => 
              if (wb_we_i = '1') then
              end if;
              rddata_reg(31 downto 0) <= rtu_ufifo_out_int(79 downto 48);
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "10111" => 
              if (wb_we_i = '1') then
              end if;
              rddata_reg(15 downto 0) <= rtu_ufifo_out_int(95 downto 80);
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "11000" => 
              if (wb_we_i = '1') then
              end if;
              rddata_reg(11 downto 0) <= rtu_ufifo_out_int(107 downto 96);
              rddata_reg(14 downto 12) <= rtu_ufifo_out_int(110 downto 108);
              rddata_reg(23 downto 16) <= rtu_ufifo_out_int(118 downto 111);
              rddata_reg(24) <= rtu_ufifo_out_int(119);
              rddata_reg(25) <= rtu_ufifo_out_int(120);
              rddata_reg(15) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "11001" => 
              if (wb_we_i = '1') then
              end if;
              rddata_reg(17) <= rtu_ufifo_empty_int;
              rddata_reg(6 downto 0) <= rtu_ufifo_usedw_int;
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "11010" => 
              if (wb_we_i = '1') then
                rtu_mfifo_in_int(0) <= wrdata_reg(0);
              end if;
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "11011" => 
              if (wb_we_i = '1') then
                rtu_mfifo_in_int(32 downto 1) <= wrdata_reg(31 downto 0);
                rtu_mfifo_wrreq_int <= '1';
              end if;
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when "11100" => 
              if (wb_we_i = '1') then
              end if;
              rddata_reg(16) <= rtu_mfifo_full_int;
              rddata_reg(17) <= rtu_mfifo_empty_int;
              rddata_reg(5 downto 0) <= rtu_mfifo_usedw_int;
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
              ack_sreg(0) <= '1';
              ack_in_progress <= '1';
            when others =>
-- prevent the slave from hanging the bus on invalid address
              ack_in_progress <= '1';
              ack_sreg(0) <= '1';
            end case;
          when '1' => 
            if (rd_int = '1') then
              ack_sreg(0) <= '1';
            else
              ack_sreg(0) <= '1';
            end if;
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Data output multiplexer process
  process (rddata_reg, rwaddr_reg, rtu_aram_rddata_int, wb_adr_i  )
  begin
    case rwaddr_reg(8) is
    when '1' => 
      wb_dat_o(31 downto 0) <= rtu_aram_rddata_int;
    when others =>
      wb_dat_o <= rddata_reg;
    end case;
  end process;
  
  
-- Read & write lines decoder for RAMs
  process (wb_adr_i, rd_int, wr_int  )
  begin
    if (wb_adr_i(8) = '1') then
      rtu_aram_rd_int <= rd_int;
      rtu_aram_wr_int <= wr_int;
    else
      rtu_aram_wr_int <= '0';
      rtu_aram_rd_int <= '0';
    end if;
  end process;
  
  
-- RTU Global Enable
-- synchronizer chain for field : RTU Global Enable (type RW/RO, clk_sys_i <-> clk_match_i)
  process (clk_match_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.gcr_g_ena_o <= '0';
      rtu_gcr_g_ena_sync0 <= '0';
      rtu_gcr_g_ena_sync1 <= '0';
    elsif rising_edge(clk_match_i) then
      rtu_gcr_g_ena_sync0 <= rtu_gcr_g_ena_int;
      rtu_gcr_g_ena_sync1 <= rtu_gcr_g_ena_sync0;
      regs_o.gcr_g_ena_o <= rtu_gcr_g_ena_sync1;
    end if;
  end process;
  
  
-- MFIFO Trigger
-- asynchronous BIT register : MFIFO Trigger (type RW/WO, clk_match_i <-> clk_sys_i)
  process (clk_match_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      rtu_gcr_mfifotrig_lw_s0 <= '0';
      rtu_gcr_mfifotrig_lw_s1 <= '0';
      rtu_gcr_mfifotrig_lw_s2 <= '0';
      rtu_gcr_mfifotrig_int_read <= '0';
      regs_o.gcr_mfifotrig_load_o <= '0';
      regs_o.gcr_mfifotrig_o <= '0';
    elsif rising_edge(clk_match_i) then
      rtu_gcr_mfifotrig_lw_s0 <= rtu_gcr_mfifotrig_lw;
      rtu_gcr_mfifotrig_lw_s1 <= rtu_gcr_mfifotrig_lw_s0;
      rtu_gcr_mfifotrig_lw_s2 <= rtu_gcr_mfifotrig_lw_s1;
      if ((rtu_gcr_mfifotrig_lw_s2 = '0') and (rtu_gcr_mfifotrig_lw_s1 = '1')) then
        if (rtu_gcr_mfifotrig_rwsel = '1') then
          regs_o.gcr_mfifotrig_o <= rtu_gcr_mfifotrig_int_write;
          regs_o.gcr_mfifotrig_load_o <= '1';
        else
          regs_o.gcr_mfifotrig_load_o <= '0';
          rtu_gcr_mfifotrig_int_read <= regs_i.gcr_mfifotrig_i;
        end if;
      else
        regs_o.gcr_mfifotrig_load_o <= '0';
      end if;
    end if;
  end process;
  
  
-- Hash Poly
-- asynchronous std_logic_vector register : Hash Poly (type RW/RO, clk_match_i <-> clk_sys_i)
  process (clk_match_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      rtu_gcr_poly_val_swb_s0 <= '0';
      rtu_gcr_poly_val_swb_s1 <= '0';
      rtu_gcr_poly_val_swb_s2 <= '0';
      regs_o.gcr_poly_val_o <= "0000000000000000";
    elsif rising_edge(clk_match_i) then
      rtu_gcr_poly_val_swb_s0 <= rtu_gcr_poly_val_swb;
      rtu_gcr_poly_val_swb_s1 <= rtu_gcr_poly_val_swb_s0;
      rtu_gcr_poly_val_swb_s2 <= rtu_gcr_poly_val_swb_s1;
      if ((rtu_gcr_poly_val_swb_s2 = '0') and (rtu_gcr_poly_val_swb_s1 = '1')) then
        regs_o.gcr_poly_val_o <= rtu_gcr_poly_val_int;
      end if;
    end if;
  end process;
  
  
-- Version
-- Port Select
  regs_o.psr_port_sel_o <= rtu_psr_port_sel_int;
-- Number of ports
-- Learning enable
  regs_o.pcr_learn_en_o <= wrdata_reg(0);
-- Pass all packets
  regs_o.pcr_pass_all_o <= wrdata_reg(1);
-- Pass BPDUs
  regs_o.pcr_pass_bpdu_o <= wrdata_reg(2);
-- Fix priority
  regs_o.pcr_fix_prio_o <= wrdata_reg(3);
-- Priority value
  regs_o.pcr_prio_val_o <= wrdata_reg(6 downto 4);
-- Unrecognized request behaviour
  regs_o.pcr_b_unrec_o <= wrdata_reg(7);
-- VLAN ID
  regs_o.vtr1_vid_o <= rtu_vtr1_vid_int;
-- Filtering Database ID
  regs_o.vtr1_fid_o <= rtu_vtr1_fid_int;
-- Drop
  regs_o.vtr1_drop_o <= rtu_vtr1_drop_int;
-- Has user-defined priority
  regs_o.vtr1_has_prio_o <= rtu_vtr1_has_prio_int;
-- Override endpoint-assigned priority
  regs_o.vtr1_prio_override_o <= rtu_vtr1_prio_override_int;
-- Priority value
  regs_o.vtr1_prio_o <= rtu_vtr1_prio_int;
-- Force VLAN table entry update
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      rtu_vtr1_update_dly0 <= '0';
      regs_o.vtr1_update_o <= '0';
    elsif rising_edge(clk_sys_i) then
      rtu_vtr1_update_dly0 <= rtu_vtr1_update_int;
      regs_o.vtr1_update_o <= rtu_vtr1_update_int and (not rtu_vtr1_update_dly0);
    end if;
  end process;
  
  
-- Port Mask
  regs_o.vtr2_port_mask_o <= rtu_vtr2_port_mask_int;
-- extra code for reg/fifo/mem: Unrecognized request FIFO (UFIFO)
  rtu_ufifo_in_int(31 downto 0) <= regs_i.ufifo_dmac_lo_i;
  rtu_ufifo_in_int(47 downto 32) <= regs_i.ufifo_dmac_hi_i;
  rtu_ufifo_in_int(79 downto 48) <= regs_i.ufifo_smac_lo_i;
  rtu_ufifo_in_int(95 downto 80) <= regs_i.ufifo_smac_hi_i;
  rtu_ufifo_in_int(107 downto 96) <= regs_i.ufifo_vid_i;
  rtu_ufifo_in_int(110 downto 108) <= regs_i.ufifo_prio_i;
  rtu_ufifo_in_int(118 downto 111) <= regs_i.ufifo_pid_i;
  rtu_ufifo_in_int(119) <= regs_i.ufifo_has_vid_i;
  rtu_ufifo_in_int(120) <= regs_i.ufifo_has_prio_i;
  rtu_ufifo_rst_n <= rst_n_i;
  rtu_ufifo_INST : wbgen2_fifo_sync
    generic map (
      g_size               => 128,
      g_width              => 121,
      g_usedw_size         => 7
    )
    port map (
      wr_req_i             => regs_i.ufifo_wr_req_i,
      wr_full_o            => regs_o.ufifo_wr_full_o,
      wr_empty_o           => regs_o.ufifo_wr_empty_o,
      rd_empty_o           => rtu_ufifo_empty_int,
      rd_usedw_o           => rtu_ufifo_usedw_int,
      rd_req_i             => rtu_ufifo_rdreq_int,
      rst_n_i              => rtu_ufifo_rst_n,
      clk_i                => clk_sys_i,
      wr_data_i            => rtu_ufifo_in_int,
      rd_data_o            => rtu_ufifo_out_int
    );
  
-- extra code for reg/fifo/mem: Main hashtable CPU access FIFO (MFIFO)
  regs_o.mfifo_ad_sel_o <= rtu_mfifo_out_int(0);
  regs_o.mfifo_ad_val_o <= rtu_mfifo_out_int(32 downto 1);
  rtu_mfifo_rst_n <= rst_n_i;
  rtu_mfifo_INST : wbgen2_fifo_async
    generic map (
      g_size               => 64,
      g_width              => 33,
      g_usedw_size         => 6
    )
    port map (
      rd_req_i             => regs_i.mfifo_rd_req_i,
      rd_empty_o           => regs_o.mfifo_rd_empty_o,
      rd_usedw_o           => regs_o.mfifo_rd_usedw_o,
      wr_full_o            => rtu_mfifo_full_int,
      wr_empty_o           => rtu_mfifo_empty_int,
      wr_usedw_o           => rtu_mfifo_usedw_int,
      wr_req_i             => rtu_mfifo_wrreq_int,
      rst_n_i              => rtu_mfifo_rst_n,
      rd_clk_i             => clk_match_i,
      wr_clk_i             => clk_sys_i,
      wr_data_i            => rtu_mfifo_in_int,
      rd_data_o            => rtu_mfifo_out_int
    );
  
-- Fast Forward for Broadcast
  regs_o.rx_ctr_ff_mac_br_o <= rtu_rx_ctr_ff_mac_br_int;
-- Fast Forward for MAC Range
  regs_o.rx_ctr_ff_mac_range_o <= rtu_rx_ctr_ff_mac_range_int;
-- Fast Forward for MAC Single Entries
  regs_o.rx_ctr_ff_mac_single_o <= rtu_rx_ctr_ff_mac_single_int;
-- Fast Forward for Link-Limited (Reserved) MACs
  regs_o.rx_ctr_ff_mac_ll_o <= rtu_rx_ctr_ff_mac_ll_int;
-- Fast Forward for PTP frames (PTP over IEEE 802.3 /Ethernet)
  regs_o.rx_ctr_ff_mac_ptp_o <= rtu_rx_ctr_ff_mac_ptp_int;
-- Port Mirror Enable
  regs_o.rx_ctr_mr_ena_o <= rtu_rx_ctr_mr_ena_int;
-- Drop/Forward on FullMatch Full
  regs_o.rx_ctr_at_fmatch_too_slow_o <= rtu_rx_ctr_at_fmatch_too_slow_int;
-- HP Priorities Mask
  regs_o.rx_ctr_prio_mask_o <= rtu_rx_ctr_prio_mask_int;
-- HP forward to CPU
  regs_o.rx_ctr_hp_fw_cpu_ena_o <= rtu_rx_ctr_hp_fw_cpu_ena_int;
-- Urecognized forward to CPU
  regs_o.rx_ctr_urec_fw_cpu_ena_o <= rtu_rx_ctr_urec_fw_cpu_ena_int;
-- Learn Destination MAC enable
  regs_o.rx_ctr_learn_dst_ena_o <= rtu_rx_ctr_learn_dst_ena_int;
-- DBG: Force Fast Match only
  regs_o.rx_ctr_force_fast_match_ena_o <= rtu_rx_ctr_force_fast_match_ena_int;
-- DBG: Force Full Match only
  regs_o.rx_ctr_force_full_match_ena_o <= rtu_rx_ctr_force_full_match_ena_int;
-- Fast Forward MAC
  regs_o.rx_ff_mac_r0_lo_o <= rtu_rx_ff_mac_r0_lo_int;
-- Fast Forward MAC
  regs_o.rx_ff_mac_r1_hi_id_o <= wrdata_reg(15 downto 0);
-- Fast Forward entry index (single/range)
  regs_o.rx_ff_mac_r1_id_o <= wrdata_reg(23 downto 16);
-- Fast Forward MAC single/range entry
  regs_o.rx_ff_mac_r1_type_o <= rtu_rx_ff_mac_r1_type_int;
-- Fast Forward MAC valid
  regs_o.rx_ff_mac_r1_valid_o <= rtu_rx_ff_mac_r1_valid_int;
--  CPU/LL Mask
-- DST/SRC Mirror port
  regs_o.rx_mp_r0_dst_src_o <= rtu_rx_mp_r0_dst_src_int;
-- RX/TX mirror port source
  regs_o.rx_mp_r0_rx_tx_o <= rtu_rx_mp_r0_rx_tx_int;
-- Mirrored Port MASK Index
  regs_o.rx_mp_r0_mask_id_o <= rtu_rx_mp_r0_mask_id_int;
-- Mirror Port MASK
  regs_o.rx_mp_r1_mask_o <= wrdata_reg(31 downto 0);
-- extra code for reg/fifo/mem: Aging bitmap for main hashtable
-- RAM block instantiation for memory: Aging bitmap for main hashtable
  rtu_aram_raminst : wbgen2_dpssram
    generic map (
      g_data_width         => 32,
      g_size               => 256,
      g_addr_width         => 8,
      g_dual_clock         => false,
      g_use_bwsel          => false
    )
    port map (
      clk_a_i              => clk_sys_i,
      clk_b_i              => clk_sys_i,
      addr_b_i             => rtu_aram_addr_i,
      addr_a_i             => rwaddr_reg(7 downto 0),
      data_b_o             => rtu_aram_data_o,
      rd_b_i               => rtu_aram_rd_i,
      data_b_i             => rtu_aram_data_i,
      wr_b_i               => rtu_aram_wr_i,
      bwsel_b_i            => allones(3 downto 0),
      data_a_o             => rtu_aram_rddata_int(31 downto 0),
      rd_a_i               => rtu_aram_rd_int,
      data_a_i             => wrdata_reg(31 downto 0),
      wr_a_i               => rtu_aram_wr_int,
      bwsel_a_i            => allones(3 downto 0)
    );
  
-- extra code for reg/fifo/mem: Interrupt disable register
  eic_idr_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt enable register
  eic_ier_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt status register
  eic_isr_clear_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
  eic_irq_controller_inst : wbgen2_eic
    generic map (
      g_num_interrupts     => 1,
      g_irq00_mode         => 2,
      g_irq01_mode         => 0,
      g_irq02_mode         => 0,
      g_irq03_mode         => 0,
      g_irq04_mode         => 0,
      g_irq05_mode         => 0,
      g_irq06_mode         => 0,
      g_irq07_mode         => 0,
      g_irq08_mode         => 0,
      g_irq09_mode         => 0,
      g_irq0a_mode         => 0,
      g_irq0b_mode         => 0,
      g_irq0c_mode         => 0,
      g_irq0d_mode         => 0,
      g_irq0e_mode         => 0,
      g_irq0f_mode         => 0,
      g_irq10_mode         => 0,
      g_irq11_mode         => 0,
      g_irq12_mode         => 0,
      g_irq13_mode         => 0,
      g_irq14_mode         => 0,
      g_irq15_mode         => 0,
      g_irq16_mode         => 0,
      g_irq17_mode         => 0,
      g_irq18_mode         => 0,
      g_irq19_mode         => 0,
      g_irq1a_mode         => 0,
      g_irq1b_mode         => 0,
      g_irq1c_mode         => 0,
      g_irq1d_mode         => 0,
      g_irq1e_mode         => 0,
      g_irq1f_mode         => 0
    )
    port map (
      clk_i                => clk_sys_i,
      rst_n_i              => rst_n_i,
      irq_i                => irq_inputs_vector_int,
      irq_ack_o            => eic_irq_ack_int,
      reg_imr_o            => eic_imr_int,
      reg_ier_i            => eic_ier_int,
      reg_ier_wr_stb_i     => eic_ier_write_int,
      reg_idr_i            => eic_idr_int,
      reg_idr_wr_stb_i     => eic_idr_write_int,
      reg_isr_o            => eic_isr_status_int,
      reg_isr_i            => eic_isr_clear_int,
      reg_isr_wr_stb_i     => eic_isr_write_int,
      wb_irq_o             => wb_int_o
    );
  
  irq_inputs_vector_int(0) <= irq_nempty_i;
-- extra code for reg/fifo/mem: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      rtu_ufifo_rdreq_int_d0 <= '0';
    elsif rising_edge(clk_sys_i) then
      rtu_ufifo_rdreq_int_d0 <= rtu_ufifo_rdreq_int;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3
-- extra code for reg/fifo/mem: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4
-- extra code for reg/fifo/mem: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0
-- extra code for reg/fifo/mem: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
