---------------------------------------------------------------------------------------
-- Title          : Wishbone slave core for WR Watchdog module
---------------------------------------------------------------------------------------
-- File           : wdog_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from wrsw_watchdog.wb
-- Created        : Tue Jun 30 11:52:29 2015
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_watchdog.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package wdog_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_wdog_in_registers is record
    rst_cnt_i                                : std_logic_vector(31 downto 0);
    cr_port_i                                : std_logic_vector(7 downto 0);
    act_i                                    : std_logic_vector(6 downto 0);
    fsm_ib_alloc_i                           : std_logic_vector(3 downto 0);
    fsm_ib_trans_i                           : std_logic_vector(3 downto 0);
    fsm_ib_rcv_i                             : std_logic_vector(3 downto 0);
    fsm_ib_ll_i                              : std_logic_vector(3 downto 0);
    fsm_ob_prep_i                            : std_logic_vector(3 downto 0);
    fsm_ob_send_i                            : std_logic_vector(3 downto 0);
    fsm_free_i                               : std_logic_vector(3 downto 0);
    end record;
  
  constant c_wdog_in_registers_init_value: t_wdog_in_registers := (
    rst_cnt_i => (others => '0'),
    cr_port_i => (others => '0'),
    act_i => (others => '0'),
    fsm_ib_alloc_i => (others => '0'),
    fsm_ib_trans_i => (others => '0'),
    fsm_ib_rcv_i => (others => '0'),
    fsm_ib_ll_i => (others => '0'),
    fsm_ob_prep_i => (others => '0'),
    fsm_ob_send_i => (others => '0'),
    fsm_free_i => (others => '0')
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_wdog_out_registers is record
      cr_port_o                                : std_logic_vector(7 downto 0);
      cr_port_load_o                           : std_logic;
      cr_rst_o                                 : std_logic;
      end record;
    
    constant c_wdog_out_registers_init_value: t_wdog_out_registers := (
      cr_port_o => (others => '0'),
      cr_port_load_o => '0',
      cr_rst_o => '0'
      );
    function "or" (left, right: t_wdog_in_registers) return t_wdog_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body wdog_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if; 
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_wdog_in_registers) return t_wdog_in_registers is
variable tmp: t_wdog_in_registers;
begin
tmp.rst_cnt_i := f_x_to_zero(left.rst_cnt_i) or f_x_to_zero(right.rst_cnt_i);
tmp.cr_port_i := f_x_to_zero(left.cr_port_i) or f_x_to_zero(right.cr_port_i);
tmp.act_i := f_x_to_zero(left.act_i) or f_x_to_zero(right.act_i);
tmp.fsm_ib_alloc_i := f_x_to_zero(left.fsm_ib_alloc_i) or f_x_to_zero(right.fsm_ib_alloc_i);
tmp.fsm_ib_trans_i := f_x_to_zero(left.fsm_ib_trans_i) or f_x_to_zero(right.fsm_ib_trans_i);
tmp.fsm_ib_rcv_i := f_x_to_zero(left.fsm_ib_rcv_i) or f_x_to_zero(right.fsm_ib_rcv_i);
tmp.fsm_ib_ll_i := f_x_to_zero(left.fsm_ib_ll_i) or f_x_to_zero(right.fsm_ib_ll_i);
tmp.fsm_ob_prep_i := f_x_to_zero(left.fsm_ob_prep_i) or f_x_to_zero(right.fsm_ob_prep_i);
tmp.fsm_ob_send_i := f_x_to_zero(left.fsm_ob_send_i) or f_x_to_zero(right.fsm_ob_send_i);
tmp.fsm_free_i := f_x_to_zero(left.fsm_free_i) or f_x_to_zero(right.fsm_free_i);
return tmp;
end function;
end package body;
