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-- Title          : Wishbone slave core for WR PTP Support Unit Controller
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-- File           : psu_wishbone_controller.vhd
-- Author         : auto-generated by wbgen2 from psu_wishbone_controller.wb
-- Created        : Wed Mar 25 20:00:25 2015
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE psu_wishbone_controller.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.psu_wbgen2_pkg.all;


entity psu_wishbone_controller is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(2 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    regs_i                                   : in     t_psu_in_registers;
    regs_o                                   : out    t_psu_out_registers
  );
end psu_wishbone_controller;

architecture syn of psu_wishbone_controller is

signal psu_pcr_psu_ena_int                      : std_logic      ;
signal psu_pcr_psu_clr_tx_msg_dly0              : std_logic      ;
signal psu_pcr_psu_clr_tx_msg_int               : std_logic      ;
signal psu_pcr_inj_prio_int                     : std_logic_vector(2 downto 0);
signal psu_pcr_holdover_clk_class_int           : std_logic_vector(7 downto 0);
signal psu_ptcr_seqid_dup_drop_int              : std_logic      ;
signal psu_ptcr_seqid_wrg_drop_int              : std_logic      ;
signal psu_ptcr_clkcl_wrg_drop_int              : std_logic      ;
signal psu_ptcr_prtid_wrg_drop_int              : std_logic      ;
signal psu_prcr_seqid_dup_det_int               : std_logic      ;
signal psu_prcr_seqid_wrg_det_int               : std_logic      ;
signal psu_prcr_prtid_wrg_det_int               : std_logic      ;
signal psu_rxpm_port_mask_int                   : std_logic_vector(31 downto 0);
signal psu_txpm_port_mask_int                   : std_logic_vector(31 downto 0);
signal psu_ptd_dbg_holdover_on_int              : std_logic      ;
signal psu_ptd_tx_ram_rd_adr_int                : std_logic_vector(9 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(2 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      psu_pcr_psu_ena_int <= '0';
      psu_pcr_psu_clr_tx_msg_int <= '0';
      psu_pcr_inj_prio_int <= "000";
      psu_pcr_holdover_clk_class_int <= "00000000";
      psu_ptcr_seqid_dup_drop_int <= '0';
      psu_ptcr_seqid_wrg_drop_int <= '0';
      psu_ptcr_clkcl_wrg_drop_int <= '0';
      psu_ptcr_prtid_wrg_drop_int <= '0';
      psu_prcr_seqid_dup_det_int <= '0';
      psu_prcr_seqid_wrg_det_int <= '0';
      psu_prcr_prtid_wrg_det_int <= '0';
      psu_rxpm_port_mask_int <= "00000000000000000000000000000000";
      psu_txpm_port_mask_int <= "00000000000000000000000000000000";
      psu_ptd_dbg_holdover_on_int <= '0';
      psu_ptd_tx_ram_rd_adr_int <= "0000000000";
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          psu_pcr_psu_clr_tx_msg_int <= '0';
          ack_in_progress <= '0';
        else
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(2 downto 0) is
          when "000" => 
            if (wb_we_i = '1') then
              psu_pcr_psu_ena_int <= wrdata_reg(0);
              psu_pcr_psu_clr_tx_msg_int <= wrdata_reg(1);
              psu_pcr_inj_prio_int <= wrdata_reg(10 downto 8);
              psu_pcr_holdover_clk_class_int <= wrdata_reg(23 downto 16);
            end if;
            rddata_reg(0) <= psu_pcr_psu_ena_int;
            rddata_reg(1) <= '0';
            rddata_reg(10 downto 8) <= psu_pcr_inj_prio_int;
            rddata_reg(23 downto 16) <= psu_pcr_holdover_clk_class_int;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= regs_i.psr_holdover_on_i;
            rddata_reg(1) <= regs_i.psr_hd_msg_rx_i;
            rddata_reg(2) <= regs_i.psr_hd_on_spll_i;
            rddata_reg(31 downto 8) <= regs_i.psr_active_ref_spll_i;
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010" => 
            if (wb_we_i = '1') then
              psu_ptcr_seqid_dup_drop_int <= wrdata_reg(0);
              psu_ptcr_seqid_wrg_drop_int <= wrdata_reg(1);
              psu_ptcr_clkcl_wrg_drop_int <= wrdata_reg(2);
              psu_ptcr_prtid_wrg_drop_int <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= psu_ptcr_seqid_dup_drop_int;
            rddata_reg(1) <= psu_ptcr_seqid_wrg_drop_int;
            rddata_reg(2) <= psu_ptcr_clkcl_wrg_drop_int;
            rddata_reg(3) <= psu_ptcr_prtid_wrg_drop_int;
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011" => 
            if (wb_we_i = '1') then
              psu_prcr_seqid_dup_det_int <= wrdata_reg(0);
              psu_prcr_seqid_wrg_det_int <= wrdata_reg(1);
              psu_prcr_prtid_wrg_det_int <= wrdata_reg(2);
            end if;
            rddata_reg(0) <= psu_prcr_seqid_dup_det_int;
            rddata_reg(1) <= psu_prcr_seqid_wrg_det_int;
            rddata_reg(2) <= psu_prcr_prtid_wrg_det_int;
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100" => 
            if (wb_we_i = '1') then
              psu_rxpm_port_mask_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= psu_rxpm_port_mask_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101" => 
            if (wb_we_i = '1') then
              psu_txpm_port_mask_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= psu_txpm_port_mask_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "110" => 
            if (wb_we_i = '1') then
              psu_ptd_dbg_holdover_on_int <= wrdata_reg(0);
              psu_ptd_tx_ram_rd_adr_int <= wrdata_reg(13 downto 4);
            end if;
            rddata_reg(0) <= psu_ptd_dbg_holdover_on_int;
            rddata_reg(1) <= regs_i.ptd_tx_ram_dat_valid_i;
            rddata_reg(13 downto 4) <= psu_ptd_tx_ram_rd_adr_int;
            rddata_reg(31 downto 14) <= regs_i.ptd_tx_ram_rd_dat_i;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- Enable PSU
  regs_o.pcr_psu_ena_o <= psu_pcr_psu_ena_int;
-- Clear Rx Msg
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      psu_pcr_psu_clr_tx_msg_dly0 <= '0';
      regs_o.pcr_psu_clr_tx_msg_o <= '0';
    elsif rising_edge(clk_sys_i) then
      psu_pcr_psu_clr_tx_msg_dly0 <= psu_pcr_psu_clr_tx_msg_int;
      regs_o.pcr_psu_clr_tx_msg_o <= psu_pcr_psu_clr_tx_msg_int and (not psu_pcr_psu_clr_tx_msg_dly0);
    end if;
  end process;
  
  
-- Inject Packet Priority
  regs_o.pcr_inj_prio_o <= psu_pcr_inj_prio_int;
-- Holdover clockClass
  regs_o.pcr_holdover_clk_class_o <= psu_pcr_holdover_clk_class_int;
-- Holdover ON
-- Announce Holdover Msg Received
-- Holdover info from SoftPLL
-- Active reference from SoftPLl
-- Drop Announce with duplicate sequence Number
  regs_o.ptcr_seqid_dup_drop_o <= psu_ptcr_seqid_dup_drop_int;
-- Drop Announce with wrong sequence Number
  regs_o.ptcr_seqid_wrg_drop_o <= psu_ptcr_seqid_wrg_drop_int;
-- Drop Announce with mismatched ClockClass
  regs_o.ptcr_clkcl_wrg_drop_o <= psu_ptcr_clkcl_wrg_drop_int;
-- Drop Announce with mismatched PortIdentity
  regs_o.ptcr_prtid_wrg_drop_o <= psu_ptcr_prtid_wrg_drop_int;
-- Detect duplicate sequence number in Announce 
  regs_o.prcr_seqid_dup_det_o <= psu_prcr_seqid_dup_det_int;
-- Detect wrong sequence number in Announce 
  regs_o.prcr_seqid_wrg_det_o <= psu_prcr_seqid_wrg_det_int;
-- Detect mismatched PortIdentity in Announce messages
  regs_o.prcr_prtid_wrg_det_o <= psu_prcr_prtid_wrg_det_int;
-- Port Mask
  regs_o.rxpm_port_mask_o <= psu_rxpm_port_mask_int;
-- Port Mask
  regs_o.txpm_port_mask_o <= psu_txpm_port_mask_int;
-- Holdover ON
  regs_o.ptd_dbg_holdover_on_o <= psu_ptd_dbg_holdover_on_int;
-- Tx inject/snoop RAM read valid
-- Tx inject/snoop RAM ADR
  regs_o.ptd_tx_ram_rd_adr_o <= psu_ptd_tx_ram_rd_adr_int;
-- Tx inject/snoop RAM DAT
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
