---------------------------------------------------------------------------------------
-- Title          : Wishbone slave core for WR Switching core
---------------------------------------------------------------------------------------
-- File           : swc_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from wrsw_swcore.wb
-- Created        : Tue Sep 13 14:08:37 2016
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_swcore.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package swc_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_swc_in_registers is record
    csr_mpm_afull_i                          : std_logic;
    csr_mpm_full_i                           : std_logic;
    stat_min_fpg_i                           : std_logic_vector(15 downto 0);
    stat_max_fpg_i                           : std_logic_vector(15 downto 0);
    cur_fpg_i                                : std_logic_vector(31 downto 0);
    afull_thr_i                              : std_logic_vector(31 downto 0);
    end record;
  
  constant c_swc_in_registers_init_value: t_swc_in_registers := (
    csr_mpm_afull_i => '0',
    csr_mpm_full_i => '0',
    stat_min_fpg_i => (others => '0'),
    stat_max_fpg_i => (others => '0'),
    cur_fpg_i => (others => '0'),
    afull_thr_i => (others => '0')
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_swc_out_registers is record
      csr_new_stat_o                           : std_logic;
      afull_thr_o                              : std_logic_vector(31 downto 0);
      afull_thr_load_o                         : std_logic;
      hp_ob_drop_mask_o                        : std_logic_vector(18 downto 0);
      end record;
    
    constant c_swc_out_registers_init_value: t_swc_out_registers := (
      csr_new_stat_o => '0',
      afull_thr_o => (others => '0'),
      afull_thr_load_o => '0',
      hp_ob_drop_mask_o => (others => '0')
      );
    function "or" (left, right: t_swc_in_registers) return t_swc_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body swc_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):= '0';
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_swc_in_registers) return t_swc_in_registers is
variable tmp: t_swc_in_registers;
begin
tmp.csr_mpm_afull_i := f_x_to_zero(left.csr_mpm_afull_i) or f_x_to_zero(right.csr_mpm_afull_i);
tmp.csr_mpm_full_i := f_x_to_zero(left.csr_mpm_full_i) or f_x_to_zero(right.csr_mpm_full_i);
tmp.stat_min_fpg_i := f_x_to_zero(left.stat_min_fpg_i) or f_x_to_zero(right.stat_min_fpg_i);
tmp.stat_max_fpg_i := f_x_to_zero(left.stat_max_fpg_i) or f_x_to_zero(right.stat_max_fpg_i);
tmp.cur_fpg_i := f_x_to_zero(left.cur_fpg_i) or f_x_to_zero(right.cur_fpg_i);
tmp.afull_thr_i := f_x_to_zero(left.afull_thr_i) or f_x_to_zero(right.afull_thr_i);
return tmp;
end function;
end package body;
