---------------------------------------------------------------------------------------
-- Title          : Wishbone slave core for WR switch Time Aware Traffic Shaper controller
---------------------------------------------------------------------------------------
-- File           : tatsu_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from tatsu_wishbone_controller.wb
-- Created        : Sun Mar  3 20:53:36 2013
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tatsu_wishbone_controller.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package tatsu_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_tatsu_in_registers is record
    tcr_min_rpt_i                            : std_logic_vector(7 downto 0);
    tcr_started_i                            : std_logic;
    tcr_delayed_i                            : std_logic;
    tcr_stg_ok_i                             : std_logic;
    tcr_stg_err_i                            : std_logic;
    tcr_stg_err_tai_i                        : std_logic;
    tcr_stg_err_cyc_i                        : std_logic;
    tcr_stg_err_rpt_i                        : std_logic;
    tcr_stg_err_snc_i                        : std_logic;
    end record;
  
  constant c_tatsu_in_registers_init_value: t_tatsu_in_registers := (
    tcr_min_rpt_i => (others => '0'),
    tcr_started_i => '0',
    tcr_delayed_i => '0',
    tcr_stg_ok_i => '0',
    tcr_stg_err_i => '0',
    tcr_stg_err_tai_i => '0',
    tcr_stg_err_cyc_i => '0',
    tcr_stg_err_rpt_i => '0',
    tcr_stg_err_snc_i => '0'
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_tatsu_out_registers is record
      tcr_validate_o                           : std_logic;
      tcr_disable_o                            : std_logic;
      tcr_drop_ena_o                           : std_logic;
      tsr0_qnt_o                               : std_logic_vector(15 downto 0);
      tsr0_prio_o                              : std_logic_vector(7 downto 0);
      tsr0_htai_o                              : std_logic_vector(7 downto 0);
      tsr1_ltai_o                              : std_logic_vector(31 downto 0);
      tsr2_cyc_o                               : std_logic_vector(27 downto 0);
      tsr3_cyc_o                               : std_logic_vector(27 downto 0);
      tsr4_ports_o                             : std_logic_vector(31 downto 0);
      end record;
    
    constant c_tatsu_out_registers_init_value: t_tatsu_out_registers := (
      tcr_validate_o => '0',
      tcr_disable_o => '0',
      tcr_drop_ena_o => '0',
      tsr0_qnt_o => (others => '0'),
      tsr0_prio_o => (others => '0'),
      tsr0_htai_o => (others => '0'),
      tsr1_ltai_o => (others => '0'),
      tsr2_cyc_o => (others => '0'),
      tsr3_cyc_o => (others => '0'),
      tsr4_ports_o => (others => '0')
      );
    function "or" (left, right: t_tatsu_in_registers) return t_tatsu_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body tatsu_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if; 
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_tatsu_in_registers) return t_tatsu_in_registers is
variable tmp: t_tatsu_in_registers;
begin
tmp.tcr_min_rpt_i := f_x_to_zero(left.tcr_min_rpt_i) or f_x_to_zero(right.tcr_min_rpt_i);
tmp.tcr_started_i := f_x_to_zero(left.tcr_started_i) or f_x_to_zero(right.tcr_started_i);
tmp.tcr_delayed_i := f_x_to_zero(left.tcr_delayed_i) or f_x_to_zero(right.tcr_delayed_i);
tmp.tcr_stg_ok_i := f_x_to_zero(left.tcr_stg_ok_i) or f_x_to_zero(right.tcr_stg_ok_i);
tmp.tcr_stg_err_i := f_x_to_zero(left.tcr_stg_err_i) or f_x_to_zero(right.tcr_stg_err_i);
tmp.tcr_stg_err_tai_i := f_x_to_zero(left.tcr_stg_err_tai_i) or f_x_to_zero(right.tcr_stg_err_tai_i);
tmp.tcr_stg_err_cyc_i := f_x_to_zero(left.tcr_stg_err_cyc_i) or f_x_to_zero(right.tcr_stg_err_cyc_i);
tmp.tcr_stg_err_rpt_i := f_x_to_zero(left.tcr_stg_err_rpt_i) or f_x_to_zero(right.tcr_stg_err_rpt_i);
tmp.tcr_stg_err_snc_i := f_x_to_zero(left.tcr_stg_err_snc_i) or f_x_to_zero(right.tcr_stg_err_snc_i);
return tmp;
end function;
end package body;
