# tru_wishbone_slave

### Topology Resolution Unit (TRU)

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. TRU Global Control Register
3.2. TRU Global Status Register 0
3.3. TRU Global Status Register 1
3.4. Pattern Control Register
3.5. Link Aggregation Control Register
3.6. Transition Control General Register
3.7. Transition Control PAUSE/Block Register
3.8. Transition Control Port Register
3.9. Transition Status Register
3.10. Real Time Reconfiguration Control Register
3.11. HW-frame gen/det config
3.12. TRU Table Register 0
3.13. TRU Table Register 1
3.14. TRU Table Register 2
3.15. TRU Table Register 3
3.16. TRU Table Register 4
3.17. TRU Table Register 5
3.18. Debug port select
3.19. Packet Injection Debug Register
3.20. Packet Filter Debug Register
3.21. RT Reconfig Debug Register

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | TRU Global Control Register | tru_gcr | GCR
0x1 | REG | TRU Global Status Register 0 | tru_gsr0 | GSR0
0x2 | REG | TRU Global Status Register 1 | tru_gsr1 | GSR1
0x3 | REG | Pattern Control Register | tru_mcr | MCR
0x4 | REG | Link Aggregation Control Register | tru_lacr | LACR
0x5 | REG | Transition Control General Register | tru_tcgr | TCGR
0x6 | REG | Transition Control PAUSE/Block Register | tru_tcpbr | TCPBR
0x7 | REG | Transition Control Port Register | tru_tcpr | TCPR
0x8 | REG | Transition Status Register | tru_tsr | TSR
0x9 | REG | Real Time Reconfiguration Control Register | tru_rtrcr | RTRCR
0xa | REG | HW-frame gen/det config | tru_hwfc | HWFC
0xb | REG | TRU Table Register 0 | tru_ttr0 | TTR0
0xc | REG | TRU Table Register 1 | tru_ttr1 | TTR1
0xd | REG | TRU Table Register 2 | tru_ttr2 | TTR2
0xe | REG | TRU Table Register 3 | tru_ttr3 | TTR3
0xf | REG | TRU Table Register 4 | tru_ttr4 | TTR4
0x10 | REG | TRU Table Register 5 | tru_ttr5 | TTR5
0x11 | REG | Debug port select | tru_dps | DPS
0x12 | REG | Packet Injection Debug Register | tru_pidr | PIDR
0x13 | REG | Packet Filter Debug Register | tru_pfdr | PFDR
0x14 | REG | RT Reconfig Debug Register | tru_ptrdr | PTRDR

### 2. HDL symbol

→ | rst_n_i |  | TRU Global Control Register: |
→ | wb_clk_i |  | tru_gcr_g_ena_o | →
⇒ | wb_addr_i[4:0] |  | tru_gcr_tru_bank_o | →
⇒ | wb_data_i[31:0] |  | tru_gcr_rx_frame_reset_o[23:0] | ⇒
⇐ | wb_data_o[31:0] |  |  |
→ | wb_cyc_i |  | TRU Global Status Register 0: |
⇒ | wb_sel_i[3:0] |  | tru_gsr0_stat_bank_i | ←
→ | wb_stb_i |  | tru_gsr0_stat_stb_up_i[23:0] | ⇐
→ | wb_we_i |  |  |
← | wb_ack_o |  | TRU Global Status Register 1: |
|  |  | tru_gsr1_stat_up_i[31:0] | ⇐
|  |  | Pattern Control Register: |
|  |  | tru_mcr_pattern_mode_rep_o[3:0] | ⇒
|  |  | tru_mcr_pattern_mode_add_o[3:0] | ⇒
|  |  | tru_mcr_pattern_mode_sub_o[3:0] | ⇒
|  |  | Link Aggregation Control Register: |
|  |  | tru_lacr_agg_df_hp_id_o[3:0] | ⇒
|  |  | tru_lacr_agg_df_br_id_o[3:0] | ⇒
|  |  | tru_lacr_agg_df_un_id_o[3:0] | ⇒
|  |  | Transition Control General Register: |
|  |  | tru_tcgr_trans_ena_o | →
|  |  | tru_tcgr_trans_clear_o | →
|  |  | tru_tcgr_trans_mode_o[2:0] | ⇒
|  |  | tru_tcgr_trans_rx_id_o[2:0] | ⇒
|  |  | tru_tcgr_trans_prio_o[2:0] | ⇒
|  |  | tru_tcgr_trans_prio_mode_o | →
|  |  | Transition Control PAUSE/Block Register: |
|  |  | tru_tcpbr_trans_pause_time_o[15:0] | ⇒
|  |  | tru_tcpbr_trans_block_time_o[15:0] | ⇒
|  |  | Transition Control Port Register: |
|  |  | tru_tcpr_trans_port_a_id_o[5:0] | ⇒
|  |  | tru_tcpr_trans_port_a_valid_o | →
|  |  | tru_tcpr_trans_port_b_id_o[5:0] | ⇒
|  |  | tru_tcpr_trans_port_b_valid_o | →
|  |  | Transition Status Register: |
|  |  | tru_tsr_trans_stat_active_i | ←
|  |  | tru_tsr_trans_stat_finished_i | ←
|  |  | Real Time Reconfiguration Control Register: |
|  |  | tru_rtrcr_rtr_ena_o | →
|  |  | tru_rtrcr_rtr_reset_o | →
|  |  | tru_rtrcr_rtr_mode_o[3:0] | ⇒
|  |  | tru_rtrcr_rtr_rx_o[3:0] | ⇒
|  |  | tru_rtrcr_rtr_tx_o[3:0] | ⇒
|  |  | HW-frame gen/det config: |
|  |  | tru_hwfc_rx_fwd_id_o[3:0] | ⇒
|  |  | tru_hwfc_rx_blk_id_o[3:0] | ⇒
|  |  | tru_hwfc_tx_fwd_id_o[3:0] | ⇒
|  |  | tru_hwfc_tx_blk_id_o[3:0] | ⇒
|  |  | tru_hwfc_tx_fwd_ub_o[7:0] | ⇒
|  |  | tru_hwfc_tx_blk_ub_o[7:0] | ⇒
|  |  | TRU Table Register 0: |
|  |  | tru_ttr0_fid_o[7:0] | ⇒
|  |  | tru_ttr0_sub_fid_o[7:0] | ⇒
|  |  | tru_ttr0_update_o | →
|  |  | tru_ttr0_mask_valid_o | →
|  |  | tru_ttr0_patrn_mode_o[3:0] | ⇒
|  |  | TRU Table Register 1: |
|  |  | tru_ttr1_ports_ingress_o[31:0] | ⇒
|  |  | TRU Table Register 2: |
|  |  | tru_ttr2_ports_egress_o[31:0] | ⇒
|  |  | TRU Table Register 3: |
|  |  | tru_ttr3_ports_mask_o[31:0] | ⇒
|  |  | TRU Table Register 4: |
|  |  | tru_ttr4_patrn_match_o[31:0] | ⇒
|  |  | TRU Table Register 5: |
|  |  | tru_ttr5_patrn_mask_o[31:0] | ⇒
|  |  | Debug port select: |
|  |  | tru_dps_pid_o[7:0] | ⇒
|  |  | Packet Injection Debug Register: |
|  |  | tru_pidr_inject_o | →
|  |  | tru_pidr_psel_o[2:0] | ⇒
|  |  | tru_pidr_uval_o[15:0] | ⇒
|  |  | tru_pidr_iready_i | ←
|  |  | Packet Filter Debug Register: |
|  |  | tru_pfdr_clr_o | →
|  |  | tru_pfdr_class_i[7:0] | ⇐
|  |  | tru_pfdr_cnt_i[15:0] | ⇐
|  |  | RT Reconfig Debug Register: |
|  |  | tru_ptrdr_ging_mask_i[31:0] | ⇐

### 3. Register description

### 3.1. TRU Global Control Register

HW prefix: | tru_gcr
HW address: | 0x0
C prefix: | GCR
C offset: | 0x0

Control register containing global (port-independent) settings of the TRU.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RX_FRAME_RESET[23:16] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RX_FRAME_RESET[15:8] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RX_FRAME_RESET[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | TRU_BANK | G_ENA

- G_ENA [read/write]: TRU Global Enable
  Global TRU enable bit. Overrides all port settings.
  0: RTU is disabled. All packets are dropped.
  1: RTU is enabled.
- TRU_BANK [write-only]: Swap TRU TAB bank
  write 1: swaps the active bank of the VLAN TAB (writing to TRU TAB affects
  inactive bank, only swapping the banks causes the written data to be activated
  write 0: no effect
- RX_FRAME_RESET [read/write]: Rx Frame Reset
  Resets information about filtered frames received on
  a port

### 3.2. TRU Global Status Register 0

HW prefix: | tru_gsr0
HW address: | 0x1
C prefix: | GSR0
C offset: | 0x4

Provides status of TRU actions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
STAT_STB_UP[23:16] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
STAT_STB_UP[15:8] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
STAT_STB_UP[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | STAT_BANK

- STAT_BANK [read-only]: Active Bank
  Indicates active bank in the TRU TAB
- STAT_STB_UP [read-only]: Stable Ports UP
  Indicates stable ports which are up (0=down, 1=up)

### 3.3. TRU Global Status Register 1

HW prefix: | tru_gsr1
HW address: | 0x2
C prefix: | GSR1
C offset: | 0x8

Provides status of TRU actions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
STAT_UP[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
STAT_UP[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
STAT_UP[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
STAT_UP[7:0] |  |  |  |  |  |  |

- STAT_UP [read-only]: Ports UP
  Indicates ports which are up (0=down, 1=up)

### 3.4. Pattern Control Register

HW prefix: | tru_mcr
HW address: | 0x3
C prefix: | MCR
C offset: | 0xc

Defines matching pattern mode/configuration for quick port reconfiguration

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | PATTERN_MODE_SUB[3:0] |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | PATTERN_MODE_ADD[3:0] |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | PATTERN_MODE_REP[3:0] |  |  |

- PATTERN_MODE_REP [read/write]: Replace Pattern Mode
  Selected Pattern Mode for port config replacement
- PATTERN_MODE_ADD [read/write]: Addition Pattern Mode
  Selected Pattern Mode for port config addition
- PATTERN_MODE_SUB [read/write]: Substraction Pattern Mode
  Selected Pattern Mode for port config substraction

### 3.5. Link Aggregation Control Register

HW prefix: | tru_lacr
HW address: | 0x4
C prefix: | LACR
C offset: | 0x10

Enables configuration of Link Aggregation distribution functions for each kind of traffic.
Available functions:
0: based on pclass detected by Packet Filter (need proper pFilter config)
1: based on destination MAC address (bits 6 and 7)
2: based on source MAC address (bits 6 and 7)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | AGG_DF_UN_ID[3:0] |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | AGG_DF_BR_ID[3:0] |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | AGG_DF_HP_ID[3:0] |  |  |

- AGG_DF_HP_ID [read/write]: HP traffic Distribution Function ID
  ID of Aggregation Distribution Function for HP traffic (value of 0 recommended, requires proper pFilter config)
- AGG_DF_BR_ID [read/write]: Broadcast Distribution Function ID
  ID of Aggregation Distribution Function for broadcast traffic (value of 2 recommended)
- AGG_DF_UN_ID [read/write]: Unicast Distribution Function ID
  ID of Aggregation Distribution Function for unicast traffic

### 3.6. Transition Control General Register

HW prefix: | tru_tcgr
HW address: | 0x5
C prefix: | TCGR
C offset: | 0x14

Defines transition mode/configuration for slow port reconfiguration - decides
when two swap banks such that HP packets are not lost.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TRANS_PRIO_MODE | TRANS_PRIO[2:0] | - | TRANS_RX_ID[2:0] |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | TRANS_MODE[2:0] | - | - | TRANS_CLEAR | TRANS_ENA |  |

- TRANS_ENA [read/write]: Transition Enabled
  Enables/disables transition
- TRANS_CLEAR [read/write]: Transition Clear
  Writing 1 clears >Transition Finished< bit so that new transition can be
  performed. No new transition will be started until >Transition Finished< is cleared
- TRANS_MODE [read/write]: Transition Mode
  Selected Transitin Mode for port re-config
- TRANS_RX_ID [read/write]: Rx Detected Frame ID
  Base transition on detection of the frame which is parsed into provided CLASS ID
- TRANS_PRIO [read/write]: Priority
  Indicates at which traffic priority the transition attempts not to loose
  frames
- TRANS_PRIO_MODE [read/write]: Priority Mode
  Specifies whether
  - 0: use indication of HP packet from RTU (fast match)
  - 1: use the priority specified in TRANS_PRIO register
  to count packets during transition

### 3.7. Transition Control PAUSE/Block Register

HW prefix: | tru_tcpbr
HW address: | 0x6
C prefix: | TCPBR
C offset: | 0x18

Defines transition mode/configuration for slow port reconfiguration - decides
when two swap banks such that HP packets are not lost.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANS_BLOCK_TIME[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TRANS_BLOCK_TIME[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TRANS_PAUSE_TIME[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRANS_PAUSE_TIME[7:0] |  |  |  |  |  |  |

- TRANS_PAUSE_TIME [read/write]: PAUSE Time
  Time (quanta) send in hw-generated PAUSE message to the link partner (port B) to block the traffic on configured priority
- TRANS_BLOCK_TIME [read/write]: Output Block Time
  Time (quanta) for which output queues of both ports (A and B) are blocked for configured priority

### 3.8. Transition Control Port Register

HW prefix: | tru_tcpr
HW address: | 0x7
C prefix: | TCPR
C offset: | 0x1c

Defines transition mode/configuration for slow port reconfiguration - decides
when two swap banks such that HP packets are not lost.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | TRANS_PORT_B_VALID

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | TRANS_PORT_B_ID[5:0] |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | TRANS_PORT_A_VALID

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | TRANS_PORT_A_ID[5:0] |  |  |  |  |

- TRANS_PORT_A_ID [read/write]: Port A ID
  Configuration of port A (PORT ID)
- TRANS_PORT_A_VALID [read/write]: Port A Valid
  Configuration of port A (valid bit)
- TRANS_PORT_B_ID [read/write]: Port B ID
  Configuration of port B (PORT ID)
- TRANS_PORT_B_VALID [read/write]: Port B Valid
  Configuration of port B (valid bit)

### 3.9. Transition Status Register

HW prefix: | tru_tsr
HW address: | 0x8
C prefix: | TSR
C offset: | 0x20

Provides information about the state of transition (if any).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | TRANS_STAT_FINISHED | TRANS_STAT_ACTIVE

- TRANS_STAT_ACTIVE [read-only]: Transition Active
  Indicates that transition is active
- TRANS_STAT_FINISHED [read-only]: Transition Finished
  Indicates that transition has been finished

### 3.10. Real Time Reconfiguration Control Register

HW prefix: | tru_rtrcr
HW address: | 0x9
C prefix: | RTRCR
C offset: | 0x24

Controls Real Time Handler.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | RTR_TX[3:0] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | RTR_RX[3:0] |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | RTR_MODE[3:0] |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | RTR_RESET | RTR_ENA

- RTR_ENA [read/write]: RTR Enabled
  Enables Real Time Reconfiguration Handler
- RTR_RESET [read/write]: RTR Reset
  Resets Real Time Reconfiguration Handler
- RTR_MODE [read/write]: RTR Handler Mode
  Selected Real Time Reconfig Handler Mode
- RTR_RX [read/write]: RTR Rx Frame ID
  ID (bit number of the rxFrameMask) of the signal from the endpoint which
  is programmed to indicate reception of Quick Forward Request BPDUe
- RTR_TX [read/write]: RTR Tx Frame ID
  ID (bit number of the txFrameMask) of the HW-sent frame by endpoint
  (Quick Forward Request BPDUe)

### 3.11. HW-frame gen/det config

HW prefix: | tru_hwfc
HW address: | 0xa
C prefix: | HWFC
C offset: | 0x28

Controls HW generation/detection of frames

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TX_BLK_UB[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TX_FWD_UB[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TX_BLK_ID[3:0] | TX_FWD_ID[3:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RX_BLK_ID[3:0] | RX_FWD_ID[3:0] |  |  |  |  |  |

- RX_FWD_ID [read/write]: HW Frame Rx Forward ID
  ID (bit number of the rxFrameMask) of the signal from the endpoint which
  is programmed to indicate reception of Quick Forward Request BPDUe
- RX_BLK_ID [read/write]: HW Frame Rx Block ID
  ID (bit number of the rxFrameMask) of the signal from the endpoint which
  is programmed to indicate reception of Quick Block Request BPDUe
- TX_FWD_ID [read/write]: HW Frame Tx Forward ID
  ID (bit number of the txFrameMask) of the HW-sent frame by endpoint
  (Quick Forward Request BPDUe)
- TX_BLK_ID [read/write]: HW Frame Tx Block ID
  ID (bit number of the txFrameMask) of the HW-sent frame by endpoint
  (Quick Block Request BPDUe)
- TX_FWD_UB [read/write]: HW Frame Tx Forward User Byte
  LOW byte of the 16-bit User Defined Value inserted into tnjected Template
- TX_BLK_UB [read/write]: HW Frame Tx Block User Byte
  LOW byte of the 16-bit User Defined Value inserted into tnjected Template

### 3.12. TRU Table Register 0

HW prefix: | tru_ttr0
HW address: | 0xb
C prefix: | TTR0
C offset: | 0x2c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | PATRN_MODE[3:0] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | MASK_VALID | UPDATE

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SUB_FID[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FID[7:0] |  |  |  |  |  |  |

- FID [read/write]: Filtering Database ID
  Assigns the VID to a particular filtering database
- SUB_FID [read/write]: ID withing Filtering Database Entry
  Identifies entry within FID entry
- UPDATE [write-only]: Force TRU table sub-entry update
  write 1: flush TTR register to inactive bank of TRU table entry at address
  in FID+SUB_FID
- MASK_VALID [read/write]: Entry Valid
- PATRN_MODE [read/write]: Pattern Mode

### 3.13. TRU Table Register 1

HW prefix: | tru_ttr1
HW address: | 0xc
C prefix: | TTR1
C offset: | 0x30

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
PORTS_INGRESS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
PORTS_INGRESS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PORTS_INGRESS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PORTS_INGRESS[7:0] |  |  |  |  |  |  |

- PORTS_INGRESS [read/write]: Ingress Mask

### 3.14. TRU Table Register 2

HW prefix: | tru_ttr2
HW address: | 0xd
C prefix: | TTR2
C offset: | 0x34

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
PORTS_EGRESS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
PORTS_EGRESS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PORTS_EGRESS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PORTS_EGRESS[7:0] |  |  |  |  |  |  |

- PORTS_EGRESS [read/write]: Egress Mask

### 3.15. TRU Table Register 3

HW prefix: | tru_ttr3
HW address: | 0xe
C prefix: | TTR3
C offset: | 0x38

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
PORTS_MASK[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
PORTS_MASK[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PORTS_MASK[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PORTS_MASK[7:0] |  |  |  |  |  |  |

- PORTS_MASK [read/write]: Egress Mask

### 3.16. TRU Table Register 4

HW prefix: | tru_ttr4
HW address: | 0xf
C prefix: | TTR4
C offset: | 0x3c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
PATRN_MATCH[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
PATRN_MATCH[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PATRN_MATCH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PATRN_MATCH[7:0] |  |  |  |  |  |  |

- PATRN_MATCH [read/write]: Pattern Match

### 3.17. TRU Table Register 5

HW prefix: | tru_ttr5
HW address: | 0x10
C prefix: | TTR5
C offset: | 0x40

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
PATRN_MASK[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
PATRN_MASK[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PATRN_MASK[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PATRN_MASK[7:0] |  |  |  |  |  |  |

- PATRN_MASK [read/write]: Patern Mask

### 3.18. Debug port select

HW prefix: | tru_dps
HW address: | 0x11
C prefix: | DPS
C offset: | 0x44

Select port number for applying debugging measures in boht:
Packet Injection Debug Register
Packet Filter Debug Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PID[7:0] |  |  |  |  |  |  |

- PID [read/write]: Port ID
  ID of the port to be debugged

### 3.19. Packet Injection Debug Register

HW prefix: | tru_pidr
HW address: | 0x12
C prefix: | PIDR
C offset: | 0x48

Used for debugging (ctrl/status) HW packet injection of a selected port

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | IREADY

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
UVAL[15:8] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
UVAL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | PSEL[2:0] | INJECT |  |

- INJECT [write-only]: Injection Request
- PSEL [read/write]: Packet Select
  ID of the packet-template to be sent
- UVAL [read/write]: USER VALUE
  Value to be inserted at predefined place in the injected packet
- IREADY [read-only]: Injection Ready

### 3.20. Packet Filter Debug Register

HW prefix: | tru_pfdr
HW address: | 0x13
C prefix: | PFDR
C offset: | 0x4c

This register stores information about detected packages (class, number)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CNT[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CNT[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CLASS[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | CLR

- CLR [write-only]: Clear register
  Clears the status regs (count and class)
- CLASS [read-only]: Filtered class
  Shows which class messages has been detected
- CNT [read-only]: CNT
  Counts all detections (regardless of the class)

### 3.21. RT Reconfig Debug Register

HW prefix: | tru_ptrdr
HW address: | 0x14
C prefix: | PTRDR
C offset: | 0x50

This register stores information about detected packages (class, number)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
GING_MASK[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
GING_MASK[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
GING_MASK[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
GING_MASK[7:0] |  |  |  |  |  |  |

- GING_MASK [read-only]: globalIngMask
  Global Ingress Mask