`define ADDR_PSU_PCR                   5'h0
`define PSU_PCR_PSU_ENA_OFFSET 0
`define PSU_PCR_PSU_ENA 32'h00000001
`define PSU_PCR_PSU_CLR_TX_MSG_OFFSET 1
`define PSU_PCR_PSU_CLR_TX_MSG 32'h00000002
`define PSU_PCR_INJ_PRIO_OFFSET 8
`define PSU_PCR_INJ_PRIO 32'h00000700
`define PSU_PCR_HOLDOVER_CLK_CLASS_OFFSET 16
`define PSU_PCR_HOLDOVER_CLK_CLASS 32'h00ff0000
`define ADDR_PSU_PSR                   5'h4
`define PSU_PSR_HOLDOVER_ON_OFFSET 0
`define PSU_PSR_HOLDOVER_ON 32'h00000001
`define PSU_PSR_HD_MSG_RX_OFFSET 1
`define PSU_PSR_HD_MSG_RX 32'h00000002
`define PSU_PSR_HD_ON_SPLL_OFFSET 2
`define PSU_PSR_HD_ON_SPLL 32'h00000004
`define PSU_PSR_ACTIVE_REF_SPLL_OFFSET 8
`define PSU_PSR_ACTIVE_REF_SPLL 32'hffffff00
`define ADDR_PSU_PTCR                  5'h8
`define PSU_PTCR_SEQID_DUP_DROP_OFFSET 0
`define PSU_PTCR_SEQID_DUP_DROP 32'h00000001
`define PSU_PTCR_SEQID_WRG_DROP_OFFSET 1
`define PSU_PTCR_SEQID_WRG_DROP 32'h00000002
`define PSU_PTCR_CLKCL_WRG_DROP_OFFSET 2
`define PSU_PTCR_CLKCL_WRG_DROP 32'h00000004
`define PSU_PTCR_PRTID_WRG_DROP_OFFSET 3
`define PSU_PTCR_PRTID_WRG_DROP 32'h00000008
`define ADDR_PSU_PRCR                  5'hc
`define PSU_PRCR_SEQID_DUP_DET_OFFSET 0
`define PSU_PRCR_SEQID_DUP_DET 32'h00000001
`define PSU_PRCR_SEQID_WRG_DET_OFFSET 1
`define PSU_PRCR_SEQID_WRG_DET 32'h00000002
`define PSU_PRCR_PRTID_WRG_DET_OFFSET 2
`define PSU_PRCR_PRTID_WRG_DET 32'h00000004
`define ADDR_PSU_RXPM                  5'h10
`define PSU_RXPM_PORT_MASK_OFFSET 0
`define PSU_RXPM_PORT_MASK 32'hffffffff
`define ADDR_PSU_TXPM                  5'h14
`define PSU_TXPM_PORT_MASK_OFFSET 0
`define PSU_TXPM_PORT_MASK 32'hffffffff
`define ADDR_PSU_PTD                   5'h18
`define PSU_PTD_DBG_HOLDOVER_ON_OFFSET 0
`define PSU_PTD_DBG_HOLDOVER_ON 32'h00000001
`define PSU_PTD_TX_RAM_DAT_VALID_OFFSET 1
`define PSU_PTD_TX_RAM_DAT_VALID 32'h00000002
`define PSU_PTD_TX_RAM_RD_ADR_OFFSET 4
`define PSU_PTD_TX_RAM_RD_ADR 32'h00003ff0
`define PSU_PTD_TX_RAM_RD_DAT_OFFSET 14
`define PSU_PTD_TX_RAM_RD_DAT 32'hffffc000
