/*
  Register definitions for slave core: WR Switch dummy Statistic Counters

  * File           : dummy_regs.h
  * Author         : auto-generated by wbgen2 from wrsw_dummy.wb
  * Created        : Thu Feb 14 15:43:14 2013
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dummy.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_WRSW_DUMMY_WB
#define __WBGEN2_REGDEFS_WRSW_DUMMY_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: control reg */

/* definitions for field: reset counters in reg: control reg */
#define DUMMY_CR_RST                          WBGEN2_GEN_MASK(0, 1)

/* definitions for register: port 0 cnt */

/* definitions for register: port 0 cnt */

/* definitions for register: port 1 cnt */

/* definitions for register: port 1 cnt */

/* definitions for register: port 1 cnt */

/* definitions for register: port 1 cnt */

/* definitions for register: port 3 cnt */

/* definitions for register: port 3 cnt */

/* definitions for register: port 4 cnt */

/* definitions for register: port 4 cnt */

/* definitions for register: port 5 cnt */

/* definitions for register: port 5 cnt */

/* definitions for register: port 6 cnt */

/* definitions for register: port 6 cnt */

/* definitions for register: port 7 cnt */

/* definitions for register: port 7 cnt */

PACKED struct DUMMY_WB {
  /* [0x0]: REG control reg */
  uint32_t CR;
  /* [0x4]: REG port 0 cnt */
  uint32_t P0_TX;
  /* [0x8]: REG port 0 cnt */
  uint32_t P0_RX;
  /* [0xc]: REG port 1 cnt */
  uint32_t P1_TX;
  /* [0x10]: REG port 1 cnt */
  uint32_t P1_RX;
  /* [0x14]: REG port 1 cnt */
  uint32_t P2_TX;
  /* [0x18]: REG port 1 cnt */
  uint32_t P2_RX;
  /* [0x1c]: REG port 3 cnt */
  uint32_t P3_TX;
  /* [0x20]: REG port 3 cnt */
  uint32_t P3_RX;
  /* [0x24]: REG port 4 cnt */
  uint32_t P4_TX;
  /* [0x28]: REG port 4 cnt */
  uint32_t P4_RX;
  /* [0x2c]: REG port 5 cnt */
  uint32_t P5_TX;
  /* [0x30]: REG port 5 cnt */
  uint32_t P5_RX;
  /* [0x34]: REG port 6 cnt */
  uint32_t P6_TX;
  /* [0x38]: REG port 6 cnt */
  uint32_t P6_RX;
  /* [0x3c]: REG port 7 cnt */
  uint32_t P7_TX;
  /* [0x40]: REG port 7 cnt */
  uint32_t P7_RX;
};

#endif
