`define ADDR_TRU_GCR                   7'h0
`define TRU_GCR_G_ENA_OFFSET 0
`define TRU_GCR_G_ENA 32'h00000001
`define TRU_GCR_TRU_BANK_OFFSET 1
`define TRU_GCR_TRU_BANK 32'h00000002
`define TRU_GCR_RX_FRAME_RESET_OFFSET 8
`define TRU_GCR_RX_FRAME_RESET 32'hffffff00
`define ADDR_TRU_GSR0                  7'h4
`define TRU_GSR0_STAT_BANK_OFFSET 0
`define TRU_GSR0_STAT_BANK 32'h00000001
`define TRU_GSR0_STAT_STB_UP_OFFSET 8
`define TRU_GSR0_STAT_STB_UP 32'hffffff00
`define ADDR_TRU_GSR1                  7'h8
`define TRU_GSR1_STAT_UP_OFFSET 0
`define TRU_GSR1_STAT_UP 32'hffffffff
`define ADDR_TRU_MCR                   7'hc
`define TRU_MCR_PATTERN_MODE_REP_OFFSET 0
`define TRU_MCR_PATTERN_MODE_REP 32'h0000000f
`define TRU_MCR_PATTERN_MODE_ADD_OFFSET 8
`define TRU_MCR_PATTERN_MODE_ADD 32'h00000f00
`define TRU_MCR_PATTERN_MODE_SUB_OFFSET 16
`define TRU_MCR_PATTERN_MODE_SUB 32'h000f0000
`define ADDR_TRU_LACR                  7'h10
`define TRU_LACR_AGG_DF_HP_ID_OFFSET 0
`define TRU_LACR_AGG_DF_HP_ID 32'h0000000f
`define TRU_LACR_AGG_DF_BR_ID_OFFSET 8
`define TRU_LACR_AGG_DF_BR_ID 32'h00000f00
`define TRU_LACR_AGG_DF_UN_ID_OFFSET 16
`define TRU_LACR_AGG_DF_UN_ID 32'h000f0000
`define ADDR_TRU_TCGR                  7'h14
`define TRU_TCGR_TRANS_ENA_OFFSET 0
`define TRU_TCGR_TRANS_ENA 32'h00000001
`define TRU_TCGR_TRANS_CLEAR_OFFSET 1
`define TRU_TCGR_TRANS_CLEAR 32'h00000002
`define TRU_TCGR_TRANS_MODE_OFFSET 4
`define TRU_TCGR_TRANS_MODE 32'h00000070
`define TRU_TCGR_TRANS_RX_ID_OFFSET 8
`define TRU_TCGR_TRANS_RX_ID 32'h00000700
`define TRU_TCGR_TRANS_PRIO_OFFSET 12
`define TRU_TCGR_TRANS_PRIO 32'h00007000
`define TRU_TCGR_TRANS_PRIO_MODE_OFFSET 15
`define TRU_TCGR_TRANS_PRIO_MODE 32'h00008000
`define ADDR_TRU_TCPBR                 7'h18
`define TRU_TCPBR_TRANS_PAUSE_TIME_OFFSET 0
`define TRU_TCPBR_TRANS_PAUSE_TIME 32'h0000ffff
`define TRU_TCPBR_TRANS_BLOCK_TIME_OFFSET 16
`define TRU_TCPBR_TRANS_BLOCK_TIME 32'hffff0000
`define ADDR_TRU_TCPR                  7'h1c
`define TRU_TCPR_TRANS_PORT_A_ID_OFFSET 0
`define TRU_TCPR_TRANS_PORT_A_ID 32'h0000003f
`define TRU_TCPR_TRANS_PORT_A_VALID_OFFSET 8
`define TRU_TCPR_TRANS_PORT_A_VALID 32'h00000100
`define TRU_TCPR_TRANS_PORT_B_ID_OFFSET 16
`define TRU_TCPR_TRANS_PORT_B_ID 32'h003f0000
`define TRU_TCPR_TRANS_PORT_B_VALID_OFFSET 24
`define TRU_TCPR_TRANS_PORT_B_VALID 32'h01000000
`define ADDR_TRU_TSR                   7'h20
`define TRU_TSR_TRANS_STAT_ACTIVE_OFFSET 0
`define TRU_TSR_TRANS_STAT_ACTIVE 32'h00000001
`define TRU_TSR_TRANS_STAT_FINISHED_OFFSET 1
`define TRU_TSR_TRANS_STAT_FINISHED 32'h00000002
`define ADDR_TRU_RTRCR                 7'h24
`define TRU_RTRCR_RTR_ENA_OFFSET 0
`define TRU_RTRCR_RTR_ENA 32'h00000001
`define TRU_RTRCR_RTR_RESET_OFFSET 1
`define TRU_RTRCR_RTR_RESET 32'h00000002
`define TRU_RTRCR_RTR_MODE_OFFSET 8
`define TRU_RTRCR_RTR_MODE 32'h00000f00
`define TRU_RTRCR_RTR_RX_OFFSET 16
`define TRU_RTRCR_RTR_RX 32'h000f0000
`define TRU_RTRCR_RTR_TX_OFFSET 24
`define TRU_RTRCR_RTR_TX 32'h0f000000
`define ADDR_TRU_HWFC                  7'h28
`define TRU_HWFC_RX_FWD_ID_OFFSET 0
`define TRU_HWFC_RX_FWD_ID 32'h0000000f
`define TRU_HWFC_RX_BLK_ID_OFFSET 4
`define TRU_HWFC_RX_BLK_ID 32'h000000f0
`define TRU_HWFC_TX_FWD_ID_OFFSET 8
`define TRU_HWFC_TX_FWD_ID 32'h00000f00
`define TRU_HWFC_TX_BLK_ID_OFFSET 12
`define TRU_HWFC_TX_BLK_ID 32'h0000f000
`define TRU_HWFC_TX_FWD_UB_OFFSET 16
`define TRU_HWFC_TX_FWD_UB 32'h00ff0000
`define TRU_HWFC_TX_BLK_UB_OFFSET 24
`define TRU_HWFC_TX_BLK_UB 32'hff000000
`define ADDR_TRU_TTR0                  7'h2c
`define TRU_TTR0_FID_OFFSET 0
`define TRU_TTR0_FID 32'h000000ff
`define TRU_TTR0_SUB_FID_OFFSET 8
`define TRU_TTR0_SUB_FID 32'h0000ff00
`define TRU_TTR0_UPDATE_OFFSET 16
`define TRU_TTR0_UPDATE 32'h00010000
`define TRU_TTR0_MASK_VALID_OFFSET 17
`define TRU_TTR0_MASK_VALID 32'h00020000
`define TRU_TTR0_PATRN_MODE_OFFSET 24
`define TRU_TTR0_PATRN_MODE 32'h0f000000
`define ADDR_TRU_TTR1                  7'h30
`define TRU_TTR1_PORTS_INGRESS_OFFSET 0
`define TRU_TTR1_PORTS_INGRESS 32'hffffffff
`define ADDR_TRU_TTR2                  7'h34
`define TRU_TTR2_PORTS_EGRESS_OFFSET 0
`define TRU_TTR2_PORTS_EGRESS 32'hffffffff
`define ADDR_TRU_TTR3                  7'h38
`define TRU_TTR3_PORTS_MASK_OFFSET 0
`define TRU_TTR3_PORTS_MASK 32'hffffffff
`define ADDR_TRU_TTR4                  7'h3c
`define TRU_TTR4_PATRN_MATCH_OFFSET 0
`define TRU_TTR4_PATRN_MATCH 32'hffffffff
`define ADDR_TRU_TTR5                  7'h40
`define TRU_TTR5_PATRN_MASK_OFFSET 0
`define TRU_TTR5_PATRN_MASK 32'hffffffff
`define ADDR_TRU_DPS                   7'h44
`define TRU_DPS_PID_OFFSET 0
`define TRU_DPS_PID 32'h000000ff
`define ADDR_TRU_PIDR                  7'h48
`define TRU_PIDR_INJECT_OFFSET 0
`define TRU_PIDR_INJECT 32'h00000001
`define TRU_PIDR_PSEL_OFFSET 1
`define TRU_PIDR_PSEL 32'h0000000e
`define TRU_PIDR_UVAL_OFFSET 8
`define TRU_PIDR_UVAL 32'h00ffff00
`define TRU_PIDR_IREADY_OFFSET 24
`define TRU_PIDR_IREADY 32'h01000000
`define ADDR_TRU_PFDR                  7'h4c
`define TRU_PFDR_CLR_OFFSET 0
`define TRU_PFDR_CLR 32'h00000001
`define TRU_PFDR_CLASS_OFFSET 8
`define TRU_PFDR_CLASS 32'h0000ff00
`define TRU_PFDR_CNT_OFFSET 16
`define TRU_PFDR_CNT 32'hffff0000
`define ADDR_TRU_PTRDR                 7'h50
`define TRU_PTRDR_GING_MASK_OFFSET 0
`define TRU_PTRDR_GING_MASK 32'hffffffff
