-- file: syst_mon.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity syst_mon is
    port (
          DADDR_IN            : in  STD_LOGIC_VECTOR (6 downto 0);     -- Address bus for the dynamic reconfiguration port
          DCLK_IN             : in  STD_LOGIC;                         -- Clock input for the dynamic reconfiguration port
          DEN_IN              : in  STD_LOGIC;                         -- Enable Signal for the dynamic reconfiguration port
          DI_IN               : in  STD_LOGIC_VECTOR (15 downto 0);    -- Input data bus for the dynamic reconfiguration port
          DWE_IN              : in  STD_LOGIC;                         -- Write Enable for the dynamic reconfiguration port
          RESET_IN            : in  STD_LOGIC;                         -- Reset signal for the System Monitor control logic
          VAUXP0              : in  STD_LOGIC;                         -- Auxiliary Channel 0
          VAUXN0              : in  STD_LOGIC;
          VAUXP1              : in  STD_LOGIC;                         -- Auxiliary Channel 1
          VAUXN1              : in  STD_LOGIC;
          VAUXP2              : in  STD_LOGIC;                         -- Auxiliary Channel 2
          VAUXN2              : in  STD_LOGIC;
          VAUXP3              : in  STD_LOGIC;                         -- Auxiliary Channel 3
          VAUXN3              : in  STD_LOGIC;
          VAUXP4              : in  STD_LOGIC;                         -- Auxiliary Channel 4
          VAUXN4              : in  STD_LOGIC;
          VAUXP5              : in  STD_LOGIC;                         -- Auxiliary Channel 5
          VAUXN5              : in  STD_LOGIC;
          VAUXP6              : in  STD_LOGIC;                         -- Auxiliary Channel 6
          VAUXN6              : in  STD_LOGIC;
          VAUXP7              : in  STD_LOGIC;                         -- Auxiliary Channel 7
          VAUXN7              : in  STD_LOGIC;
          BUSY_OUT            : out  STD_LOGIC;                        -- ADC Busy signal
          CHANNEL_OUT         : out  STD_LOGIC_VECTOR (4 downto 0);    -- Channel Selection Outputs
          DO_OUT              : out  STD_LOGIC_VECTOR (15 downto 0);   -- Output data bus for dynamic reconfiguration port
          DRDY_OUT            : out  STD_LOGIC;                        -- Data ready signal for the dynamic reconfiguration port
          EOC_OUT             : out  STD_LOGIC;                        -- End of Conversion Signal
          EOS_OUT             : out  STD_LOGIC;                        -- End of Sequence Signal
          VP_IN               : in  STD_LOGIC;                         -- Dedicated Analog Input Pair
          VN_IN               : in  STD_LOGIC
);
end syst_mon;

architecture xilinx of syst_mon is

  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of xilinx : architecture is "sysmon_wiz_v2_1, Coregen 12.4";

  signal aux_channel_p : std_logic_vector (15 downto 0);
  signal aux_channel_n : std_logic_vector (15 downto 0);

begin

        aux_channel_p(0) <= VAUXP0;
        aux_channel_n(0) <= VAUXN0;

        aux_channel_p(1) <= VAUXP1;
        aux_channel_n(1) <= VAUXN1;

        aux_channel_p(2) <= VAUXP2;
        aux_channel_n(2) <= VAUXN2;

        aux_channel_p(3) <= VAUXP3;
        aux_channel_n(3) <= VAUXN3;

        aux_channel_p(4) <= VAUXP4;
        aux_channel_n(4) <= VAUXN4;

        aux_channel_p(5) <= VAUXP5;
        aux_channel_n(5) <= VAUXN5;

        aux_channel_p(6) <= VAUXP6;
        aux_channel_n(6) <= VAUXN6;

        aux_channel_p(7) <= VAUXP7;
        aux_channel_n(7) <= VAUXN7;

        aux_channel_p(8) <= '0';
        aux_channel_n(8) <= '0';

        aux_channel_p(9) <= '0';
        aux_channel_n(9) <= '0';

        aux_channel_p(10) <= '0';
        aux_channel_n(10) <= '0';

        aux_channel_p(11) <= '0';
        aux_channel_n(11) <= '0';

        aux_channel_p(12) <= '0';
        aux_channel_n(12) <= '0';

        aux_channel_p(13) <= '0';
        aux_channel_n(13) <= '0';

        aux_channel_p(14) <= '0';
        aux_channel_n(14) <= '0';

        aux_channel_p(15) <= '0';
        aux_channel_n(15) <= '0';


 SYSMON_INST : SYSMON
     generic map(
        INIT_40 => X"1000", -- config reg 0
        INIT_41 => X"20ff", -- config reg 1
        INIT_42 => X"0d00", -- config reg 2
        INIT_48 => X"0701", -- Sequencer channel selection
        INIT_49 => X"00ff", -- Sequencer channel selection
        INIT_4A => X"0700", -- Sequencer Average selection
        INIT_4B => X"00ff", -- Sequencer Average selection
        INIT_4C => X"0000", -- Sequencer Bipolar selection
        INIT_4D => X"0000", -- Sequencer Bipolar selection
        INIT_4E => X"0000", -- Sequencer Acq time selection
        INIT_4F => X"0000", -- Sequencer Acq time selection
        INIT_50 => X"b5ed", -- Temp alarm trigger
        INIT_51 => X"5999", -- Vccint upper alarm limit
        INIT_52 => X"e000", -- Vccaux upper alarm limit
        INIT_53 => X"ca33",  -- Temp alarm OT upper
        INIT_54 => X"a93a", -- Temp alarm reset
        INIT_55 => X"5111", -- Vccint lower alarm limit
        INIT_56 => X"caaa", -- Vccaux lower alarm limit
        INIT_57 => X"ae4e",  -- Temp alarm OT reset
        SIM_DEVICE => "VIRTEX6",
        SIM_MONITOR_FILE => "design.txt"
        )

port map (
        CONVST              => '0',
        CONVSTCLK           => '0',
        DADDR(6 downto 0)   => DADDR_IN(6 downto 0),
        DCLK                => DCLK_IN,
        DEN                 => DEN_IN,
        DI(15 downto 0)     => DI_IN(15 downto 0),
        DWE                 => DWE_IN,
        RESET               => RESET_IN,
        VAUXN(15 downto 0)  => aux_channel_n(15 downto 0),
        VAUXP(15 downto 0)  => aux_channel_p(15 downto 0),
        ALM(2)              => open,
        ALM(1)              => open,
        ALM(0)              => open,
        BUSY                => BUSY_OUT,
        CHANNEL(4 downto 0) => CHANNEL_OUT(4 downto 0),
        DO(15 downto 0)     => DO_OUT(15 downto 0),
        DRDY                => DRDY_OUT,
        EOC                 => EOC_OUT,
        EOS                 => EOS_OUT,
        JTAGBUSY            => open,
        JTAGLOCKED          => open,
        JTAGMODIFIED        => open,
        OT                  => open,
        VN                  => VP_IN,
        VP                  => VN_IN
        );
end xilinx;

