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-- Title          : Wishbone slave core for WR Switch aux clock generation module
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-- File           : gen10_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from wrsw_gen_10mhz.wb
-- Created        : Tue Dec  9 10:20:16 2014
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_gen_10mhz.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package gen10_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_gen10_in_registers is record
    ior_tap_cur_i                            : std_logic_vector(4 downto 0);
    ior_lck_i                                : std_logic;
    pps_ior_tap_cur_i                        : std_logic_vector(4 downto 0);
    end record;
  
  constant c_gen10_in_registers_init_value: t_gen10_in_registers := (
    ior_tap_cur_i => (others => '0'),
    ior_lck_i => '0',
    pps_ior_tap_cur_i => (others => '0')
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_gen10_out_registers is record
      pr_hp_width_o                            : std_logic_vector(15 downto 0);
      pr_hp_width_wr_o                         : std_logic;
      dcr_low_width_o                          : std_logic_vector(15 downto 0);
      dcr_low_width_wr_o                       : std_logic;
      csr_o                                    : std_logic_vector(15 downto 0);
      csr_wr_o                                 : std_logic;
      ior_tap_set_o                            : std_logic_vector(4 downto 0);
      ior_tap_set_wr_o                         : std_logic;
      pps_ior_tap_set_o                        : std_logic_vector(4 downto 0);
      pps_ior_tap_set_wr_o                     : std_logic;
      end record;
    
    constant c_gen10_out_registers_init_value: t_gen10_out_registers := (
      pr_hp_width_o => (others => '0'),
      pr_hp_width_wr_o => '0',
      dcr_low_width_o => (others => '0'),
      dcr_low_width_wr_o => '0',
      csr_o => (others => '0'),
      csr_wr_o => '0',
      ior_tap_set_o => (others => '0'),
      ior_tap_set_wr_o => '0',
      pps_ior_tap_set_o => (others => '0'),
      pps_ior_tap_set_wr_o => '0'
      );
    function "or" (left, right: t_gen10_in_registers) return t_gen10_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body gen10_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if; 
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_gen10_in_registers) return t_gen10_in_registers is
variable tmp: t_gen10_in_registers;
begin
tmp.ior_tap_cur_i := f_x_to_zero(left.ior_tap_cur_i) or f_x_to_zero(right.ior_tap_cur_i);
tmp.ior_lck_i := f_x_to_zero(left.ior_lck_i) or f_x_to_zero(right.ior_lck_i);
tmp.pps_ior_tap_cur_i := f_x_to_zero(left.pps_ior_tap_cur_i) or f_x_to_zero(right.pps_ior_tap_cur_i);
return tmp;
end function;
end package body;
