`define ADDR_TXTSU_EIC_IDR             5'h0
`define TXTSU_EIC_IDR_NEMPTY_OFFSET 0
`define TXTSU_EIC_IDR_NEMPTY 32'h00000001
`define ADDR_TXTSU_EIC_IER             5'h4
`define TXTSU_EIC_IER_NEMPTY_OFFSET 0
`define TXTSU_EIC_IER_NEMPTY 32'h00000001
`define ADDR_TXTSU_EIC_IMR             5'h8
`define TXTSU_EIC_IMR_NEMPTY_OFFSET 0
`define TXTSU_EIC_IMR_NEMPTY 32'h00000001
`define ADDR_TXTSU_EIC_ISR             5'hc
`define TXTSU_EIC_ISR_NEMPTY_OFFSET 0
`define TXTSU_EIC_ISR_NEMPTY 32'h00000001
`define ADDR_TXTSU_TSF_R0              5'h10
`define TXTSU_TSF_R0_VAL_R_OFFSET 0
`define TXTSU_TSF_R0_VAL_R 32'h0fffffff
`define TXTSU_TSF_R0_VAL_F_OFFSET 28
`define TXTSU_TSF_R0_VAL_F 32'hf0000000
`define ADDR_TXTSU_TSF_R1              5'h14
`define TXTSU_TSF_R1_PID_OFFSET 0
`define TXTSU_TSF_R1_PID 32'h0000001f
`define TXTSU_TSF_R1_FID_OFFSET 16
`define TXTSU_TSF_R1_FID 32'hffff0000
`define ADDR_TXTSU_TSF_R2              5'h18
`define TXTSU_TSF_R2_INCORRECT_OFFSET 0
`define TXTSU_TSF_R2_INCORRECT 32'h00000001
`define ADDR_TXTSU_TSF_CSR             5'h1c
`define TXTSU_TSF_CSR_FULL_OFFSET 16
`define TXTSU_TSF_CSR_FULL 32'h00010000
`define TXTSU_TSF_CSR_EMPTY_OFFSET 17
`define TXTSU_TSF_CSR_EMPTY 32'h00020000
`define TXTSU_TSF_CSR_USEDW_OFFSET 0
`define TXTSU_TSF_CSR_USEDW 32'h000000ff
