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-- Title          : Wishbone slave core for PTS Frequency Measurement Result Registers
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-- File           : freq_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from wb_freq_regs.wb
-- Created        : Wed Feb 15 11:13:39 2017
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_freq_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package freq_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_freq_in_registers is record
    f_dmtd_clk_freq_i                        : std_logic_vector(27 downto 0);
    f_clk10mhz_ext_freq_i                    : std_logic_vector(27 downto 0);
    f_fpga_main_clk_freq_i                   : std_logic_vector(27 downto 0);
    f_aux_clk_freq_i                         : std_logic_vector(27 downto 0);
    f_serdes_clk_freq_i                      : std_logic_vector(27 downto 0);
    f_ref_clk_freq_i                         : std_logic_vector(27 downto 0);
    end record;
  
  constant c_freq_in_registers_init_value: t_freq_in_registers := (
    f_dmtd_clk_freq_i => (others => '0'),
    f_clk10mhz_ext_freq_i => (others => '0'),
    f_fpga_main_clk_freq_i => (others => '0'),
    f_aux_clk_freq_i => (others => '0'),
    f_serdes_clk_freq_i => (others => '0'),
    f_ref_clk_freq_i => (others => '0')
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_freq_out_registers is record
      dummy : std_logic;
      end record;
    
    constant c_freq_out_registers_init_value: t_freq_out_registers := (
      dummy => '0'
      );
    function "or" (left, right: t_freq_in_registers) return t_freq_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body freq_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_freq_in_registers) return t_freq_in_registers is
variable tmp: t_freq_in_registers;
begin
tmp.f_dmtd_clk_freq_i := f_x_to_zero(left.f_dmtd_clk_freq_i) or f_x_to_zero(right.f_dmtd_clk_freq_i);
tmp.f_clk10mhz_ext_freq_i := f_x_to_zero(left.f_clk10mhz_ext_freq_i) or f_x_to_zero(right.f_clk10mhz_ext_freq_i);
tmp.f_fpga_main_clk_freq_i := f_x_to_zero(left.f_fpga_main_clk_freq_i) or f_x_to_zero(right.f_fpga_main_clk_freq_i);
tmp.f_aux_clk_freq_i := f_x_to_zero(left.f_aux_clk_freq_i) or f_x_to_zero(right.f_aux_clk_freq_i);
tmp.f_serdes_clk_freq_i := f_x_to_zero(left.f_serdes_clk_freq_i) or f_x_to_zero(right.f_serdes_clk_freq_i);
tmp.f_ref_clk_freq_i := f_x_to_zero(left.f_ref_clk_freq_i) or f_x_to_zero(right.f_ref_clk_freq_i);
return tmp;
end function;
end package body;
