---------------------------------------------------------------------------------------
-- Title          : Wishbone slave core for WR Switch dummy Statistic Counters
---------------------------------------------------------------------------------------
-- File           : dummy_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from wrsw_dummy.wb
-- Created        : Thu Feb 14 15:43:14 2013
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_dummy.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package dummy_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_dummy_in_registers is record
    p0_tx_i                                  : std_logic_vector(31 downto 0);
    p0_rx_i                                  : std_logic_vector(31 downto 0);
    p1_tx_i                                  : std_logic_vector(31 downto 0);
    p1_rx_i                                  : std_logic_vector(31 downto 0);
    p2_tx_i                                  : std_logic_vector(31 downto 0);
    p2_rx_i                                  : std_logic_vector(31 downto 0);
    p3_tx_i                                  : std_logic_vector(31 downto 0);
    p3_rx_i                                  : std_logic_vector(31 downto 0);
    p4_tx_i                                  : std_logic_vector(31 downto 0);
    p4_rx_i                                  : std_logic_vector(31 downto 0);
    p5_tx_i                                  : std_logic_vector(31 downto 0);
    p5_rx_i                                  : std_logic_vector(31 downto 0);
    p6_tx_i                                  : std_logic_vector(31 downto 0);
    p6_rx_i                                  : std_logic_vector(31 downto 0);
    p7_tx_i                                  : std_logic_vector(31 downto 0);
    p7_rx_i                                  : std_logic_vector(31 downto 0);
    end record;
  
  constant c_dummy_in_registers_init_value: t_dummy_in_registers := (
    p0_tx_i => (others => '0'),
    p0_rx_i => (others => '0'),
    p1_tx_i => (others => '0'),
    p1_rx_i => (others => '0'),
    p2_tx_i => (others => '0'),
    p2_rx_i => (others => '0'),
    p3_tx_i => (others => '0'),
    p3_rx_i => (others => '0'),
    p4_tx_i => (others => '0'),
    p4_rx_i => (others => '0'),
    p5_tx_i => (others => '0'),
    p5_rx_i => (others => '0'),
    p6_tx_i => (others => '0'),
    p6_rx_i => (others => '0'),
    p7_tx_i => (others => '0'),
    p7_rx_i => (others => '0')
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_dummy_out_registers is record
      cr_rst_o                                 : std_logic;
      end record;
    
    constant c_dummy_out_registers_init_value: t_dummy_out_registers := (
      cr_rst_o => '0'
      );
    function "or" (left, right: t_dummy_in_registers) return t_dummy_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body dummy_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if; 
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_dummy_in_registers) return t_dummy_in_registers is
variable tmp: t_dummy_in_registers;
begin
tmp.p0_tx_i := f_x_to_zero(left.p0_tx_i) or f_x_to_zero(right.p0_tx_i);
tmp.p0_rx_i := f_x_to_zero(left.p0_rx_i) or f_x_to_zero(right.p0_rx_i);
tmp.p1_tx_i := f_x_to_zero(left.p1_tx_i) or f_x_to_zero(right.p1_tx_i);
tmp.p1_rx_i := f_x_to_zero(left.p1_rx_i) or f_x_to_zero(right.p1_rx_i);
tmp.p2_tx_i := f_x_to_zero(left.p2_tx_i) or f_x_to_zero(right.p2_tx_i);
tmp.p2_rx_i := f_x_to_zero(left.p2_rx_i) or f_x_to_zero(right.p2_rx_i);
tmp.p3_tx_i := f_x_to_zero(left.p3_tx_i) or f_x_to_zero(right.p3_tx_i);
tmp.p3_rx_i := f_x_to_zero(left.p3_rx_i) or f_x_to_zero(right.p3_rx_i);
tmp.p4_tx_i := f_x_to_zero(left.p4_tx_i) or f_x_to_zero(right.p4_tx_i);
tmp.p4_rx_i := f_x_to_zero(left.p4_rx_i) or f_x_to_zero(right.p4_rx_i);
tmp.p5_tx_i := f_x_to_zero(left.p5_tx_i) or f_x_to_zero(right.p5_tx_i);
tmp.p5_rx_i := f_x_to_zero(left.p5_rx_i) or f_x_to_zero(right.p5_rx_i);
tmp.p6_tx_i := f_x_to_zero(left.p6_tx_i) or f_x_to_zero(right.p6_tx_i);
tmp.p6_rx_i := f_x_to_zero(left.p6_rx_i) or f_x_to_zero(right.p6_rx_i);
tmp.p7_tx_i := f_x_to_zero(left.p7_tx_i) or f_x_to_zero(right.p7_tx_i);
tmp.p7_rx_i := f_x_to_zero(left.p7_rx_i) or f_x_to_zero(right.p7_rx_i);
return tmp;
end function;
end package body;
