-- file: oserdes_8_to_1.vhd
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
-- 
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
-- 
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
-- 
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
-- 
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

entity oserdes_8_to_1 is
generic
 (-- width of the data for the system
  sys_w       : integer := 1;
  -- width of the data for the device
  dev_w       : integer := 8);
port
 (
  -- From the device out to the system
  DATA_OUT_FROM_DEVICE    : in    std_logic_vector(dev_w-1 downto 0);
  DATA_OUT_TO_PINS_P      : out   std_logic_vector(sys_w-1 downto 0);
  DATA_OUT_TO_PINS_N      : out   std_logic_vector(sys_w-1 downto 0);

-- Input, Output delay control signals
  DELAY_RESET          : in    std_logic;                    -- Active high synchronous reset for input delay
  DELAY_DATA_CE        : in    std_logic_vector(sys_w -1 downto 0);            -- Enable signal for delay for bit 
  DELAY_DATA_INC       : in    std_logic_vector(sys_w -1 downto 0);            -- Delay increment, decrement signal for bit 
  DELAY_TAP_IN         : in    std_logic_vector(5*sys_w -1 downto 0); -- Dynamically loadable delay tap value for bit 
  DELAY_TAP_OUT        : out   std_logic_vector(5*sys_w -1 downto 0); -- Bit  Delay tap value for monitoring
  DELAY_LOCKED            : out   std_logic;                    -- Locked signal from IDELAYCTRL
  REF_CLOCK               : in    std_logic;                    -- Reference Clock for IDELAYCTRL. Has to come from BUFG.
 
-- Clock and reset signals
  CLK_IN                  : in    std_logic;                    -- Fast clock from PLL/MMCM 
  CLK_DIV_IN              : in    std_logic;                    -- Slow clock from PLL/MMCM
  IO_RESET                : in    std_logic);                   -- Reset signal for IO circuit
end oserdes_8_to_1;

architecture xilinx of oserdes_8_to_1 is
  attribute CORE_GENERATION_INFO            : string;
  attribute CORE_GENERATION_INFO of xilinx  : architecture is "oserdes_8_to_1,selectio_wiz_v4_1,{component_name=oserdes_8_to_1,bus_dir=OUTPUTS,bus_sig_type=DIFF,bus_io_std=LVDS_25,use_serialization=true,use_phase_detector=false,serialization_factor=8,enable_bitslip=false,enable_train=false,system_data_width=1,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=DIFF,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,v6_bus_in_delay=NONE,v6_bus_out_delay=VAR_LOADABLE,v6_clk_buf=MMCM,v6_active_edge=SDR,v6_ddr_alignment=SAME_EDGE_PIPELINED,v6_oddr_alignment=SAME_EDGE,ddr_alignment=C0,v6_interface_type=NETWORKING,interface_type=NETWORKING,v6_bus_in_tap=0,v6_bus_out_tap=0,v6_clk_io_std=LVCMOS25,v6_clk_sig_type=SINGLE}";
  constant clock_enable            : std_logic := '1';
  signal unused : std_logic;
  signal clk_in_int_buf            : std_logic;
  signal clk_div_in_int            : std_logic;


  -- Before the buffer
  signal data_out_to_pins_int      : std_logic_vector(sys_w-1 downto 0);
  -- Between the delay and serdes
  signal data_out_to_pins_predelay : std_logic_vector(sys_w-1 downto 0);
  signal data_delay                : std_logic_vector(sys_w-1 downto 0); 
  signal delay_ce              : std_logic_vector(sys_w-1 downto 0);
  signal delay_inc_dec         : std_logic_vector(sys_w-1 downto 0);
  type loadarr is array (0 to 15) of std_logic_vector(8 downto 0);
  signal intap                 : loadarr := (( others => (others => '0')));
  signal outtap                : loadarr := (( others => (others => '0')));
  constant num_serial_bits         : integer := dev_w/sys_w;
  --type serdarr is array (0 to 7) of std_logic_vector(sys_w-1 downto 0);
  -- Array to use intermediately from the serdes to the internal
  --  devices. bus "0" is the leftmost bus
   --  * fills in from higher order
  signal oserdes_d                : std_logic_vector(7 downto 0);
  signal serdesstrobe             : std_logic;
  signal ocascade_ms_d            : std_logic_vector(sys_w-1 downto 0);
  signal ocascade_ms_t            : std_logic_vector(sys_w-1 downto 0);
  signal ocascade_sm_d            : std_logic_vector(sys_w-1 downto 0);
  signal ocascade_sm_t            : std_logic_vector(sys_w-1 downto 0);

begin

  delay_ce(0) <= DELAY_DATA_CE(0);
  delay_inc_dec(0) <= DELAY_DATA_INC(0);
   intap(0) <= "0000"&DELAY_TAP_IN(5*(0 + 1) -1 downto 5*(0)); 
   DELAY_TAP_OUT(5*(0 + 1) -1 downto 5*(0)) <= outtap(0)(5*(0 + 1) -1 downto 5*(0)); 


  -- Create the clock logic

  
  -- We have multiple bits- step over every bit, instantiating the required elements
  pins: for pin_count in 0 to sys_w-1 generate 
  begin
    -- Instantiate the buffers
    ----------------------------------
    -- Instantiate a buffer for every bit of the data bus
     obufds_inst : OBUFDS
       port map (
         O          => DATA_OUT_TO_PINS_P  (pin_count),
         OB         => DATA_OUT_TO_PINS_N  (pin_count),
         I          => data_out_to_pins_int(pin_count));

    -- Instantiate the delay primitive
    -----------------------------------

   data_out_to_pins_int(pin_count) <= data_delay(pin_count);

   ODELAYE3_inst : ODELAYE3
   generic map (
      CASCADE => "NONE",          -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
      DELAY_FORMAT => "COUNT",     -- (COUNT, TIME)
      DELAY_TYPE => "VAR_LOAD",      -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
      DELAY_VALUE => 0,           -- Output delay tap setting
      IS_CLK_INVERTED => '0',     -- Optional inversion for CLK
      IS_RST_INVERTED => '0',     -- Optional inversion for RST
      REFCLK_FREQUENCY => 200.0,  -- IDELAYCTRL clock input frequency in MHz (200.0-2667.0).
      SIM_DEVICE => "ULTRASCALE_PLUS", -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
                                  -- ULTRASCALE_PLUS_ES2)
      UPDATE_MODE => "ASYNC"      -- Determines when updates to the delay will take effect (ASYNC, MANUAL,
                                  -- SYNC)
   )
   port map (
      CASC_OUT    => open,           -- 1-bit output: Cascade delay output to IDELAY input cascade
      CNTVALUEOUT => outtap(pin_count), -- 9-bit output: Counter value output
      DATAOUT     => data_delay(pin_count),  -- 1-bit output: Delayed data from ODATAIN input port
      CASC_IN     => '0',             -- 1-bit input: Cascade delay input from slave IDELAY CASCADE_OUT
      CASC_RETURN => '0',         -- 1-bit input: Cascade delay returning from slave IDELAY DATAOUT
      CE          => delay_ce(pin_count),                   -- 1-bit input: Active high enable increment/decrement input
      CLK         => CLK_DIV_IN,                 -- 1-bit input: Clock input
      CNTVALUEIN  => intap(pin_count),   -- 9-bit input: Counter value input
      EN_VTC      => '0',           -- 1-bit input: Keep delay constant over VT
      INC         => delay_inc_dec(pin_count),                 -- 1-bit input: Increment/Decrement tap delay input
      LOAD        => '0',               -- 1-bit input: Load DELAY_VALUE input
      ODATAIN     => data_out_to_pins_predelay(pin_count),             -- 1-bit input: Data input
      RST         => DELAY_RESET                  -- 1-bit input: Asynchronous Reset to the DELAY_VALUE
   );


     -- Instantiate the serdes primitive
     ----------------------------------

     -- it has changed a bit from Virtex version

    OSERDESE3_inst : OSERDESE3
    generic map (
      DATA_WIDTH => 8,            -- Parallel Data Width (4-8)
      INIT => '0',                -- Initialization value of the OSERDES flip-flops
      IS_CLKDIV_INVERTED => '0',  -- Optional inversion for CLKDIV
      IS_CLK_INVERTED => '0',     -- Optional inversion for CLK
      IS_RST_INVERTED => '0',     -- Optional inversion for RST
      SIM_DEVICE => "ULTRASCALE_PLUS"  -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
                                  -- ULTRASCALE_PLUS_ES2)
   )
   port map (
      OQ      => data_out_to_pins_predelay(pin_count),         -- 1-bit output: Serial Output Data
      T_OUT   => open,   -- 1-bit output: 3-state control output to IOB
      CLK     => CLK_IN,       -- 1-bit input: High-speed clock
      CLKDIV  => CLK_DIV_IN, -- 1-bit input: Divided Clock
      D       => oserdes_d,           -- 8-bit input: Parallel Data Input
      RST     => IO_RESET,       -- 1-bit input: Asynchronous Reset
      T       => '0'            -- 1-bit input: Tristate input from fabric
   );

     -------------------------------------------------------------


    out_slices: for slice_count in 0 to num_serial_bits-1 generate begin
        -- This places the first data in time on the right
        oserdes_d(8-slice_count-1) <=
           DATA_OUT_FROM_DEVICE(slice_count);
        -- To place the first data in time on the left, use the
        --   following code, instead
        -- oserdes_d(slice_count) <=
        --    DATA_OUT_FROM_DEVICE(slice_count);

     end generate out_slices;

  end generate pins;

-- IDELAYCTRL is needed for calibration
delayctrl : IDELAYCTRL
    generic map(
      SIM_DEVICE => "ULTRASCALE"
    )
    port map (
     RDY    => DELAY_LOCKED,
     REFCLK => REF_CLOCK,
     RST    => IO_RESET
     );




end xilinx;



