target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX130T"
fetchto = "../../ip_cores"
#vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"

files = [ "main.sv" ]

include_dirs = [ "../../sim", "../../sim/wr-hdl" ]

modules = { "local" : ["../../", "../../top/bare_top"] }
					

					
