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-- Title          : Wishbone slave core for WR switch Time Aware Traffic Shaper controller
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-- File           : tatsu_wishbone_controller.vhd
-- Author         : auto-generated by wbgen2 from tatsu_wishbone_controller.wb
-- Created        : Sun Mar  3 20:53:36 2013
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tatsu_wishbone_controller.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.tatsu_wbgen2_pkg.all;


entity tatsu_wishbone_controller is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(2 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    regs_i                                   : in     t_tatsu_in_registers;
    regs_o                                   : out    t_tatsu_out_registers
  );
end tatsu_wishbone_controller;

architecture syn of tatsu_wishbone_controller is

signal tatsu_tcr_validate_dly0                  : std_logic      ;
signal tatsu_tcr_validate_int                   : std_logic      ;
signal tatsu_tcr_disable_dly0                   : std_logic      ;
signal tatsu_tcr_disable_int                    : std_logic      ;
signal tatsu_tcr_drop_ena_int                   : std_logic      ;
signal tatsu_tsr0_qnt_int                       : std_logic_vector(15 downto 0);
signal tatsu_tsr0_prio_int                      : std_logic_vector(7 downto 0);
signal tatsu_tsr0_htai_int                      : std_logic_vector(7 downto 0);
signal tatsu_tsr1_ltai_int                      : std_logic_vector(31 downto 0);
signal tatsu_tsr2_cyc_int                       : std_logic_vector(27 downto 0);
signal tatsu_tsr3_cyc_int                       : std_logic_vector(27 downto 0);
signal tatsu_tsr4_ports_int                     : std_logic_vector(31 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(2 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      tatsu_tcr_validate_int <= '0';
      tatsu_tcr_disable_int <= '0';
      tatsu_tcr_drop_ena_int <= '0';
      tatsu_tsr0_qnt_int <= "0000000000000000";
      tatsu_tsr0_prio_int <= "00000000";
      tatsu_tsr0_htai_int <= "00000000";
      tatsu_tsr1_ltai_int <= "00000000000000000000000000000000";
      tatsu_tsr2_cyc_int <= "0000000000000000000000000000";
      tatsu_tsr3_cyc_int <= "0000000000000000000000000000";
      tatsu_tsr4_ports_int <= "00000000000000000000000000000000";
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          tatsu_tcr_validate_int <= '0';
          tatsu_tcr_disable_int <= '0';
          ack_in_progress <= '0';
        else
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(2 downto 0) is
          when "000" => 
            if (wb_we_i = '1') then
              tatsu_tcr_validate_int <= wrdata_reg(0);
              tatsu_tcr_disable_int <= wrdata_reg(1);
              tatsu_tcr_drop_ena_int <= wrdata_reg(8);
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(8) <= tatsu_tcr_drop_ena_int;
            rddata_reg(23 downto 16) <= regs_i.tcr_min_rpt_i;
            rddata_reg(24) <= regs_i.tcr_started_i;
            rddata_reg(25) <= regs_i.tcr_delayed_i;
            rddata_reg(26) <= regs_i.tcr_stg_ok_i;
            rddata_reg(27) <= regs_i.tcr_stg_err_i;
            rddata_reg(28) <= regs_i.tcr_stg_err_tai_i;
            rddata_reg(29) <= regs_i.tcr_stg_err_cyc_i;
            rddata_reg(30) <= regs_i.tcr_stg_err_rpt_i;
            rddata_reg(31) <= regs_i.tcr_stg_err_snc_i;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "001" => 
            if (wb_we_i = '1') then
              tatsu_tsr0_qnt_int <= wrdata_reg(15 downto 0);
              tatsu_tsr0_prio_int <= wrdata_reg(23 downto 16);
              tatsu_tsr0_htai_int <= wrdata_reg(31 downto 24);
            end if;
            rddata_reg(15 downto 0) <= tatsu_tsr0_qnt_int;
            rddata_reg(23 downto 16) <= tatsu_tsr0_prio_int;
            rddata_reg(31 downto 24) <= tatsu_tsr0_htai_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010" => 
            if (wb_we_i = '1') then
              tatsu_tsr1_ltai_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= tatsu_tsr1_ltai_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011" => 
            if (wb_we_i = '1') then
              tatsu_tsr2_cyc_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= tatsu_tsr2_cyc_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100" => 
            if (wb_we_i = '1') then
              tatsu_tsr3_cyc_int <= wrdata_reg(27 downto 0);
            end if;
            rddata_reg(27 downto 0) <= tatsu_tsr3_cyc_int;
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101" => 
            if (wb_we_i = '1') then
              tatsu_tsr4_ports_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= tatsu_tsr4_ports_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- Validate new settings, enable TATSU (if disabled)
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      tatsu_tcr_validate_dly0 <= '0';
      regs_o.tcr_validate_o <= '0';
    elsif rising_edge(clk_sys_i) then
      tatsu_tcr_validate_dly0 <= tatsu_tcr_validate_int;
      regs_o.tcr_validate_o <= tatsu_tcr_validate_int and (not tatsu_tcr_validate_dly0);
    end if;
  end process;
  
  
-- Stop TATSU
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      tatsu_tcr_disable_dly0 <= '0';
      regs_o.tcr_disable_o <= '0';
    elsif rising_edge(clk_sys_i) then
      tatsu_tcr_disable_dly0 <= tatsu_tcr_disable_int;
      regs_o.tcr_disable_o <= tatsu_tcr_disable_int and (not tatsu_tcr_disable_dly0);
    end if;
  end process;
  
  
-- Drop no-HP at HP
  regs_o.tcr_drop_ena_o <= tatsu_tcr_drop_ena_int;
-- Min repeat value
-- TATSU started
-- Delayed start
-- Settings OK
-- Settings Error
-- Settings Error: TAI value
-- Settings Error: cycle value
-- Settings Error: repeat value
-- Internal Time Sync Error
-- Quanta
  regs_o.tsr0_qnt_o <= tatsu_tsr0_qnt_int;
-- Window Priorit Mask
  regs_o.tsr0_prio_o <= tatsu_tsr0_prio_int;
-- Start time (hi_TAI)
  regs_o.tsr0_htai_o <= tatsu_tsr0_htai_int;
-- Start time (lo_TAI)
  regs_o.tsr1_ltai_o <= tatsu_tsr1_ltai_int;
-- Start time (cycles)
  regs_o.tsr2_cyc_o <= tatsu_tsr2_cyc_int;
-- Repeat time (cycle)
  regs_o.tsr3_cyc_o <= tatsu_tsr3_cyc_int;
-- Ports mask
  regs_o.tsr4_ports_o <= tatsu_tsr4_ports_int;
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
