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-- Title          : Wishbone slave core for silabs interface
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-- File           : si570_if_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from si570_if_wb.wb
-- Created        : Thu Aug  6 16:04:41 2015
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE si570_if_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package si570_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_si570_in_registers is record
    gpsr_scl_i                               : std_logic;
    gpsr_sda_i                               : std_logic;
    end record;
  
  constant c_si570_in_registers_init_value: t_si570_in_registers := (
    gpsr_scl_i => '0',
    gpsr_sda_i => '0'
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_si570_out_registers is record
      rfreql_o                                 : std_logic_vector(31 downto 0);
      rfreqh_o                                 : std_logic_vector(7 downto 0);
      gpsr_scl_o                               : std_logic;
      gpsr_scl_load_o                          : std_logic;
      gpsr_sda_o                               : std_logic;
      gpsr_sda_load_o                          : std_logic;
      gpcr_scl_o                               : std_logic;
      gpcr_sda_o                               : std_logic;
      end record;
    
    constant c_si570_out_registers_init_value: t_si570_out_registers := (
      rfreql_o => (others => '0'),
      rfreqh_o => (others => '0'),
      gpsr_scl_o => '0',
      gpsr_scl_load_o => '0',
      gpsr_sda_o => '0',
      gpsr_sda_load_o => '0',
      gpcr_scl_o => '0',
      gpcr_sda_o => '0'
      );
    function "or" (left, right: t_si570_in_registers) return t_si570_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body si570_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):= '0';
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_si570_in_registers) return t_si570_in_registers is
variable tmp: t_si570_in_registers;
begin
tmp.gpsr_scl_i := f_x_to_zero(left.gpsr_scl_i) or f_x_to_zero(right.gpsr_scl_i);
tmp.gpsr_sda_i := f_x_to_zero(left.gpsr_sda_i) or f_x_to_zero(right.gpsr_sda_i);
return tmp;
end function;
end package body;
