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-- Title          : Wishbone slave core for WR Switch Per-Port Statistic Counters
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-- File           : pstats_wishbone_slave.vhd
-- Author         : auto-generated by wbgen2 from wrsw_pstats.wb
-- Created        : Tue Jun 24 15:56:25 2014
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pstats.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;

use work.pstats_wbgen2_pkg.all;


entity pstats_wishbone_slave is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(3 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    wb_int_o                                 : out    std_logic;
    irq_port0_i                              : in     std_logic;
    irq_port0_ack_o                          : out    std_logic;
    irq_port1_i                              : in     std_logic;
    irq_port1_ack_o                          : out    std_logic;
    irq_port2_i                              : in     std_logic;
    irq_port2_ack_o                          : out    std_logic;
    irq_port3_i                              : in     std_logic;
    irq_port3_ack_o                          : out    std_logic;
    irq_port4_i                              : in     std_logic;
    irq_port4_ack_o                          : out    std_logic;
    irq_port5_i                              : in     std_logic;
    irq_port5_ack_o                          : out    std_logic;
    irq_port6_i                              : in     std_logic;
    irq_port6_ack_o                          : out    std_logic;
    irq_port7_i                              : in     std_logic;
    irq_port7_ack_o                          : out    std_logic;
    irq_port8_i                              : in     std_logic;
    irq_port8_ack_o                          : out    std_logic;
    irq_port9_i                              : in     std_logic;
    irq_port9_ack_o                          : out    std_logic;
    irq_port10_i                             : in     std_logic;
    irq_port10_ack_o                         : out    std_logic;
    irq_port11_i                             : in     std_logic;
    irq_port11_ack_o                         : out    std_logic;
    irq_port12_i                             : in     std_logic;
    irq_port12_ack_o                         : out    std_logic;
    irq_port13_i                             : in     std_logic;
    irq_port13_ack_o                         : out    std_logic;
    irq_port14_i                             : in     std_logic;
    irq_port14_ack_o                         : out    std_logic;
    irq_port15_i                             : in     std_logic;
    irq_port15_ack_o                         : out    std_logic;
    irq_port16_i                             : in     std_logic;
    irq_port16_ack_o                         : out    std_logic;
    irq_port17_i                             : in     std_logic;
    irq_port17_ack_o                         : out    std_logic;
    regs_i                                   : in     t_pstats_in_registers;
    regs_o                                   : out    t_pstats_out_registers
  );
end pstats_wishbone_slave;

architecture syn of pstats_wishbone_slave is

signal pstats_cr_port_int                       : std_logic_vector(4 downto 0);
signal pstats_cr_addr_int                       : std_logic_vector(4 downto 0);
signal eic_idr_int                              : std_logic_vector(17 downto 0);
signal eic_idr_write_int                        : std_logic      ;
signal eic_ier_int                              : std_logic_vector(17 downto 0);
signal eic_ier_write_int                        : std_logic      ;
signal eic_imr_int                              : std_logic_vector(17 downto 0);
signal eic_isr_clear_int                        : std_logic_vector(17 downto 0);
signal eic_isr_status_int                       : std_logic_vector(17 downto 0);
signal eic_irq_ack_int                          : std_logic_vector(17 downto 0);
signal eic_isr_write_int                        : std_logic      ;
signal irq_inputs_vector_int                    : std_logic_vector(17 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(3 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      regs_o.cr_rd_en_load_o <= '0';
      regs_o.cr_rd_irq_load_o <= '0';
      pstats_cr_port_int <= "00000";
      pstats_cr_addr_int <= "00000";
      eic_idr_write_int <= '0';
      eic_ier_write_int <= '0';
      eic_isr_write_int <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          regs_o.cr_rd_en_load_o <= '0';
          regs_o.cr_rd_irq_load_o <= '0';
          eic_idr_write_int <= '0';
          eic_ier_write_int <= '0';
          eic_isr_write_int <= '0';
          ack_in_progress <= '0';
        else
          regs_o.cr_rd_en_load_o <= '0';
          regs_o.cr_rd_irq_load_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(3 downto 0) is
          when "0000" => 
            if (wb_we_i = '1') then
              regs_o.cr_rd_en_load_o <= '1';
              regs_o.cr_rd_irq_load_o <= '1';
              pstats_cr_port_int <= wrdata_reg(12 downto 8);
              pstats_cr_addr_int <= wrdata_reg(20 downto 16);
            end if;
            rddata_reg(0) <= regs_i.cr_rd_en_i;
            rddata_reg(1) <= regs_i.cr_rd_irq_i;
            rddata_reg(12 downto 8) <= pstats_cr_port_int;
            rddata_reg(20 downto 16) <= pstats_cr_addr_int;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.l1_cnt_val_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.l2_cnt_val_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= regs_i.info_ver_i;
            rddata_reg(15 downto 8) <= regs_i.info_cpw_i;
            rddata_reg(31 downto 16) <= regs_i.info_cpp_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1000" => 
            if (wb_we_i = '1') then
              eic_idr_write_int <= '1';
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1001" => 
            if (wb_we_i = '1') then
              eic_ier_write_int <= '1';
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(17 downto 0) <= eic_imr_int(17 downto 0);
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1011" => 
            if (wb_we_i = '1') then
              eic_isr_write_int <= '1';
            end if;
            rddata_reg(17 downto 0) <= eic_isr_status_int(17 downto 0);
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- Enable transfer of counter content
  regs_o.cr_rd_en_o <= wrdata_reg(0);
-- Enable transfer of per-counter IRQ state
  regs_o.cr_rd_irq_o <= wrdata_reg(1);
-- Port number
  regs_o.cr_port_o <= pstats_cr_port_int;
-- Memory address
  regs_o.cr_addr_o <= pstats_cr_addr_int;
-- 4 counters' values
-- 4 counters' values
-- Version
-- Counters per word
-- Counters per port
-- extra code for reg/fifo/mem: Interrupt disable register
  eic_idr_int(17 downto 0) <= wrdata_reg(17 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
  eic_ier_int(17 downto 0) <= wrdata_reg(17 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
  eic_isr_clear_int(17 downto 0) <= wrdata_reg(17 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
  eic_irq_controller_inst : wbgen2_eic
    generic map (
      g_num_interrupts     => 18,
      g_irq00_mode         => 3,
      g_irq01_mode         => 3,
      g_irq02_mode         => 3,
      g_irq03_mode         => 3,
      g_irq04_mode         => 3,
      g_irq05_mode         => 3,
      g_irq06_mode         => 3,
      g_irq07_mode         => 3,
      g_irq08_mode         => 3,
      g_irq09_mode         => 3,
      g_irq0a_mode         => 3,
      g_irq0b_mode         => 3,
      g_irq0c_mode         => 3,
      g_irq0d_mode         => 3,
      g_irq0e_mode         => 3,
      g_irq0f_mode         => 3,
      g_irq10_mode         => 3,
      g_irq11_mode         => 3,
      g_irq12_mode         => 0,
      g_irq13_mode         => 0,
      g_irq14_mode         => 0,
      g_irq15_mode         => 0,
      g_irq16_mode         => 0,
      g_irq17_mode         => 0,
      g_irq18_mode         => 0,
      g_irq19_mode         => 0,
      g_irq1a_mode         => 0,
      g_irq1b_mode         => 0,
      g_irq1c_mode         => 0,
      g_irq1d_mode         => 0,
      g_irq1e_mode         => 0,
      g_irq1f_mode         => 0
    )
    port map (
      clk_i                => clk_sys_i,
      rst_n_i              => rst_n_i,
      irq_i                => irq_inputs_vector_int,
      irq_ack_o            => eic_irq_ack_int,
      reg_imr_o            => eic_imr_int,
      reg_ier_i            => eic_ier_int,
      reg_ier_wr_stb_i     => eic_ier_write_int,
      reg_idr_i            => eic_idr_int,
      reg_idr_wr_stb_i     => eic_idr_write_int,
      reg_isr_o            => eic_isr_status_int,
      reg_isr_i            => eic_isr_clear_int,
      reg_isr_wr_stb_i     => eic_isr_write_int,
      wb_irq_o             => wb_int_o
    );
  
  irq_inputs_vector_int(0) <= irq_port0_i;
  irq_port0_ack_o <= eic_irq_ack_int(0);
  irq_inputs_vector_int(1) <= irq_port1_i;
  irq_port1_ack_o <= eic_irq_ack_int(1);
  irq_inputs_vector_int(2) <= irq_port2_i;
  irq_port2_ack_o <= eic_irq_ack_int(2);
  irq_inputs_vector_int(3) <= irq_port3_i;
  irq_port3_ack_o <= eic_irq_ack_int(3);
  irq_inputs_vector_int(4) <= irq_port4_i;
  irq_port4_ack_o <= eic_irq_ack_int(4);
  irq_inputs_vector_int(5) <= irq_port5_i;
  irq_port5_ack_o <= eic_irq_ack_int(5);
  irq_inputs_vector_int(6) <= irq_port6_i;
  irq_port6_ack_o <= eic_irq_ack_int(6);
  irq_inputs_vector_int(7) <= irq_port7_i;
  irq_port7_ack_o <= eic_irq_ack_int(7);
  irq_inputs_vector_int(8) <= irq_port8_i;
  irq_port8_ack_o <= eic_irq_ack_int(8);
  irq_inputs_vector_int(9) <= irq_port9_i;
  irq_port9_ack_o <= eic_irq_ack_int(9);
  irq_inputs_vector_int(10) <= irq_port10_i;
  irq_port10_ack_o <= eic_irq_ack_int(10);
  irq_inputs_vector_int(11) <= irq_port11_i;
  irq_port11_ack_o <= eic_irq_ack_int(11);
  irq_inputs_vector_int(12) <= irq_port12_i;
  irq_port12_ack_o <= eic_irq_ack_int(12);
  irq_inputs_vector_int(13) <= irq_port13_i;
  irq_port13_ack_o <= eic_irq_ack_int(13);
  irq_inputs_vector_int(14) <= irq_port14_i;
  irq_port14_ack_o <= eic_irq_ack_int(14);
  irq_inputs_vector_int(15) <= irq_port15_i;
  irq_port15_ack_o <= eic_irq_ack_int(15);
  irq_inputs_vector_int(16) <= irq_port16_i;
  irq_port16_ack_o <= eic_irq_ack_int(16);
  irq_inputs_vector_int(17) <= irq_port17_i;
  irq_port17_ack_o <= eic_irq_ack_int(17);
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
