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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 8a19940a authored by Marek Gumiński's avatar Marek Gumiński
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Changed data length in psu

parent 21de71de
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Showing with 65 additions and 52 deletions
ip_cores/wr-cores-local/modules/fabric/wr_fabric_pkg.vhd
View file @ 8a19940a
......@@ -64,6 +64,15 @@ package wr_fabric_pkg is
sel : std_logic_vector(1 downto 0);
end record;
type t_wrf_source64_out is record
adr : std_logic_vector(1 downto 0);
dat : std_logic_vector(63 downto 0);
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : std_logic_vector(1 downto 0);
end record;
type t_wrf_source_in is record
ack : std_logic;
stall : std_logic;
......@@ -82,10 +91,12 @@ package wr_fabric_pkg is
end record;
subtype t_wrf_sink_in is t_wrf_source_out;
subtype t_wrf_sink64_in is t_wrf_source64_out;
subtype t_wrf_sink_out is t_wrf_source_in;
type t_wrf_source_in_array is array (natural range <>) of t_wrf_source_in;
type t_wrf_source_out_array is array (natural range <>) of t_wrf_source_out;
type t_wrf_source64_out_array is array (natural range <>) of t_wrf_source64_out;
subtype t_wrf_sink_in_array is t_wrf_source_out_array;
subtype t_wrf_sink_out_array is t_wrf_source_in_array;
......@@ -100,6 +111,8 @@ package wr_fabric_pkg is
('0', '0', '0', '0');
constant c_dummy_snk_in : t_wrf_sink_in :=
("XX", "XXXXXXXXXXXXXXXX", '0', '0', '0', "XX");
constant c_dummy_snk64_in : t_wrf_sink64_in :=
("XX", "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX", '0', '0', '0', "XX");
-----------------------------------------------------------------------------
......@@ -133,10 +146,10 @@ package wr_fabric_pkg is
port(
rst_n_i : in std_logic;
clk_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_i : in t_wrf_sink64_in;
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out);
src_o : out t_wrf_source64_out);
end component;
component xwrf_loopback
......
ip_cores/wr-cores-local/modules/fabric/xwrf_reg.vhd
View file @ 8a19940a
......@@ -40,16 +40,16 @@ entity xwrf_reg is
port(
rst_n_i : in std_logic;
clk_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_i : in t_wrf_sink64_in;
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out);
src_o : out t_wrf_source64_out);
end xwrf_reg;
architecture behav of xwrf_reg is
type t_reg_fsm is (PASS, STALL, FLUSH);
signal state : t_reg_fsm;
signal temp : t_wrf_sink_in;
signal temp : t_wrf_sink64_in;
begin
process(clk_i)
......@@ -64,7 +64,7 @@ begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
state <= PASS;
src_o <= c_dummy_snk_in;
src_o <= c_dummy_snk64_in;
else
case state is
when PASS =>
......
modules/wrsw_psu/psu_announce_snooper.vhd
View file @ 8a19940a
......@@ -84,11 +84,11 @@ entity psu_announce_snooper is
rst_n_i : in std_logic;
-- interface with NIC
snk_i : in t_wrf_sink_in;
snk_i : in t_wrf_sink64_in;
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
src_o : out t_wrf_source64_out;
rtu_dst_port_mask_i : in std_logic_vector(g_port_number-1 downto 0);
......@@ -105,10 +105,10 @@ entity psu_announce_snooper is
-- access to the RAM that stores snooped announce frames and information about
-- portID + seqID per port.
wr_ram_ena_o : out std_logic;
wr_ram_data_o : out std_logic_vector(17 downto 0);
wr_ram_data_o : out std_logic_vector(65 downto 0);
wr_ram_addr_o : out std_logic_vector(9 downto 0);
rd_ram_data_i : in std_logic_vector(17 downto 0);
rd_ram_data_i : in std_logic_vector(65 downto 0);
rd_ram_ena_o : out std_logic;
rd_ram_addr_o : out std_logic_vector( 9 downto 0);
......@@ -140,7 +140,7 @@ architecture behavioral of psu_announce_snooper is
WAIT_EOF
);
signal data : std_logic_vector(15 downto 0);
signal data : std_logic_vector(63 downto 0);
signal stb : std_logic;
signal oob_valid : std_logic;
signal data_valid : std_logic;
......@@ -165,7 +165,7 @@ architecture behavioral of psu_announce_snooper is
signal zeros : std_logic_vector(g_port_number-1 downto 0);
signal detected_announce : std_logic;
signal snk_ack_drop : std_logic;
signal seq_id_d : std_logic_vector(15 downto 0);
signal seq_id_d : std_logic_vector(63 downto 0);
......@@ -229,9 +229,9 @@ begin
sourcePortIDmatch <= '1';
elsif(state = WAIT_SOURCE_PORT_ID) then
sourcePortIDmatch <= '1';
elsif(state = SOURCE_CLOCK_ID and data_valid = '1' and rd_ram_data_i(15 downto 0) /= data) then
elsif(state = SOURCE_CLOCK_ID and data_valid = '1' and rd_ram_data_i(63 downto 0) /= data) then
sourcePortIDmatch <= '0';
elsif(state = SOURCE_PORT_NUMBER and data_valid = '1' and rd_ram_data_i(15 downto 0) /= data) then
elsif(state = SOURCE_PORT_NUMBER and data_valid = '1' and rd_ram_data_i(63 downto 0) /= data) then
sourcePortIDmatch <= '0';
elsif(state = WAIT_SOF) then
sourcePortIDmatch <= '0';
......@@ -247,7 +247,7 @@ begin
if(config_i.seqID_duplicate_det = '0') then
duplicate <= '0';
elsif(state = SEQ_ID and data_valid = '1' and std_logic_vector(unsigned(data)+1) = rd_ram_data_i(15 downto 0)) then
elsif(state = SEQ_ID and data_valid = '1' and std_logic_vector(unsigned(data)+1) = rd_ram_data_i(63 downto 0)) then
duplicate <= '1';
elsif(state = WAIT_SOF) then
duplicate <= '0';
......@@ -256,7 +256,7 @@ begin
if(config_i.seqID_wrong_det = '0') then
seqIdWrong <= '0';
elsif(state = SEQ_ID and data_valid = '1') then
if(data = rd_ram_data_i(15 downto 0)) then
if(data = rd_ram_data_i(63 downto 0)) then
seqIdWrong <= '0';
else
seqIdWrong <= '1';
......@@ -317,13 +317,13 @@ begin
when WAIT_ETHERTYPE =>
if(data_valid = '1' and word_cnt = next_offset) then
if(data = x"88F7") then -- PTP raw ethernet frame
if(data(15 downto 0) = x"88F7") then -- PTP raw ethernet frame
state <= WAIT_MSG_TYPE;
next_offset <= next_offset + 1; -- th word
elsif(data = x"8100") then -- VLAN tag
elsif(data(15 downto 0) = x"8100") then -- VLAN tag
state <= HAS_VTAG;
next_offset <= next_offset + 2;
elsif(data = x"0800") then -- IP frame
elsif(data(15 downto 0) = x"0800") then -- IP frame
state <= WAIT_UDP_PROTO;
next_offset <= next_offset + 5;
else
......@@ -335,10 +335,10 @@ begin
if(data_valid = '1' and word_cnt = next_offset) then
if(data = x"88F7") then -- PTP raw ethernet frame
if(data(15 downto 0) = x"88F7") then -- PTP raw ethernet frame
state <= WAIT_MSG_TYPE;
next_offset <= next_offset + 1;
elsif(data = x"0800") then -- IP frame
elsif(data(15 downto 0) = x"0800") then -- IP frame
state <= WAIT_UDP_PROTO;
next_offset <= next_offset + 5;
else
......@@ -360,7 +360,7 @@ begin
when WAIT_PTP_PORT =>
if(data_valid = '1' and word_cnt = next_offset) then
if(data = x"0140") then
if(data(15 downto 0) = x"0140") then
state <= WAIT_MSG_TYPE;
next_offset <= next_offset + 3;
else
......@@ -492,12 +492,12 @@ begin
wr_ram_addr_o <= '1' & "000" & port_index & '0' when (state = SOURCE_PORT_NUMBER) else
'1' & "000" & port_index & '1' when (state = WRITE_SEQ_ID) else
'0' & not sel & std_logic_vector(word_cnt);
wr_ram_data_o(15 downto 0) <= seq_id_d when (state = WRITE_SEQ_ID) else
wr_ram_data_o(63 downto 0) <= seq_id_d when (state = WRITE_SEQ_ID) else
data when (data_valid = '1') else
(others =>'0');
wr_ram_data_o(17) <= '1' when (state = CLOCK_CLASS) else '0';
wr_ram_data_o(16) <= '1' when (data_valid = '1' or state = WRITE_SEQ_ID) else '0';
wr_ram_data_o(64) <= '1' when (state = CLOCK_CLASS) else '0';
wr_ram_data_o(65) <= '1' when (data_valid = '1' or state = WRITE_SEQ_ID) else '0';
wr_ram_ena_o <= '1' when (data_valid = '1' or state = WRITE_SEQ_ID) else '0';
......
modules/wrsw_psu/psu_packet_injection.vhd
View file @ 8a19940a
......@@ -68,9 +68,9 @@ entity psu_packet_injection is
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
src_o : out t_wrf_source64_out;
snk_i : in t_wrf_sink_in;
snk_i : in t_wrf_sink64_in;
snk_o : out t_wrf_sink_out;
rtu_dst_port_mask_o : out std_logic_vector(g_port_number-1 downto 0);
......@@ -93,7 +93,7 @@ entity psu_packet_injection is
inject_port_mask_i : in std_logic_vector(g_port_number-1 downto 0);
inject_pck_prio_i : in std_logic_vector( 2 downto 0);
rd_ram_data_i : in std_logic_vector(17 downto 0)
rd_ram_data_i : in std_logic_vector(65 downto 0)
);
end psu_packet_injection;
......@@ -110,7 +110,7 @@ architecture rtl of psu_packet_injection is
signal within_packet : std_logic;
signal select_inject : std_logic;
signal inj_src : t_wrf_source_out;
signal inj_src : t_wrf_source64_out;
signal inj_snk : t_wrf_sink_out;
signal inj_stb : std_logic;
signal inject_req_latched : std_logic;
......@@ -229,9 +229,9 @@ begin -- rtl
inj_src.sel(1) <= '1';
inj_src.sel(0) <= '1';
inj_src.stb <= '1' when (inj_stb = '1' and validData = '1') else '0';
inj_src.dat <= inj_val when (inj_src.adr = c_WRF_DATA and clockClass = '1') else
def_status_word when (inj_src.adr = c_WRF_STATUS) else
rd_ram_data_i(15 downto 0) ;
inj_src.dat <= inj_val&inj_val&inj_val&inj_val when (inj_src.adr = c_WRF_DATA and clockClass = '1') else
def_status_word&def_status_word&def_status_word&def_status_word when (inj_src.adr = c_WRF_STATUS) else
rd_ram_data_i(63 downto 0);
inject_done <= '1' when (state = EOF and src_i.stall = '0') else '0';
......
modules/wrsw_psu/psu_pkg.vhd
View file @ 8a19940a
......@@ -70,11 +70,11 @@ package psu_pkg is
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_i : in t_wrf_sink64_in;
snk_o : out t_wrf_sink_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
src_o : out t_wrf_source64_out;
rtu_dst_port_mask_i : in std_logic_vector(g_port_number-1 downto 0);
holdover_on_i : in std_logic;
......@@ -83,10 +83,10 @@ package psu_pkg is
detected_port_mask_o : out std_logic_vector(g_port_number-1 downto 0);
wr_ram_ena_o : out std_logic;
wr_ram_data_o : out std_logic_vector(17 downto 0);
wr_ram_data_o : out std_logic_vector(65 downto 0);
wr_ram_addr_o : out std_logic_vector(9 downto 0);
rd_ram_data_i : in std_logic_vector(17 downto 0);
rd_ram_data_i : in std_logic_vector(65 downto 0);
rd_ram_ena_o : out std_logic;
rd_ram_addr_o : out std_logic_vector( 9 downto 0);
config_i : in t_snooper_config);
......@@ -101,8 +101,8 @@ package psu_pkg is
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
snk_i : in t_wrf_sink_in;
src_o : out t_wrf_source64_out;
snk_i : in t_wrf_sink64_in;
snk_o : out t_wrf_sink_out;
rtu_dst_port_mask_o : out std_logic_vector(g_port_number-1 downto 0);
rtu_prio_o : out std_logic_vector(2 downto 0);
......@@ -120,7 +120,7 @@ package psu_pkg is
inject_port_mask_i : in std_logic_vector(g_port_number-1 downto 0);
inject_pck_prio_i : in std_logic_vector( 2 downto 0);
rd_ram_data_i : in std_logic_vector(17 downto 0)
rd_ram_data_i : in std_logic_vector(65 downto 0)
);
end component;
......
modules/wrsw_psu/xwrsw_psu.vhd
View file @ 8a19940a
......@@ -127,7 +127,7 @@ entity xwrsw_psu is
rst_n_i : in std_logic;
-- interface with NIC: tx path
tx_snk_i : in t_wrf_sink_in;
tx_snk_i : in t_wrf_sink64_in;
tx_snk_o : out t_wrf_sink_out;
tx_rtu_dst_port_mask_i : in std_logic_vector(g_port_mask_bits-1 downto 0);
tx_rtu_prio_i : in std_logic_vector(2 downto 0);
......@@ -137,11 +137,11 @@ entity xwrsw_psu is
-- interface with NIC: rx path
rx_src_i : in t_wrf_source_in;
rx_src_o : out t_wrf_source_out;
rx_src_o : out t_wrf_source64_out;
-- interface with RTU/SWcore: tx path
tx_src_i : in t_wrf_source_in;
tx_src_o : out t_wrf_source_out;
tx_src_o : out t_wrf_source64_out;
tx_rtu_dst_port_mask_o : out std_logic_vector(g_port_mask_bits-1 downto 0);
tx_rtu_prio_o : out std_logic_vector(2 downto 0);
tx_rtu_drop_o : out std_logic;
......@@ -149,7 +149,7 @@ entity xwrsw_psu is
tx_rtu_rsp_ack_i : in std_logic;
-- interface with SWcore: rx path
rx_snk_i : in t_wrf_sink_in;
rx_snk_i : in t_wrf_sink64_in;
rx_snk_o : out t_wrf_sink_out;
-- communciation with rt_subsystem
......@@ -181,23 +181,23 @@ architecture behavioral of xwrsw_psu is
signal rx_snoop_ports_mask : std_logic_vector(g_port_number-1 downto 0);
signal tx_wr_ram_addr : std_logic_vector( 9 downto 0);
signal tx_wr_ram_data : std_logic_vector(17 downto 0);
signal tx_wr_ram_data : std_logic_vector(65 downto 0);
signal tx_wr_ram_ena : std_logic;
signal tx_rd_ram_addr : std_logic_vector( 9 downto 0);
signal tx_rd_ram_data : std_logic_vector(17 downto 0);
signal tx_rd_ram_data : std_logic_vector(65 downto 0);
signal tx_snoop_ram_addr : std_logic_vector( 9 downto 0);
signal tx_snoop_ram_data : std_logic_vector(17 downto 0);
signal tx_snoop_ram_data : std_logic_vector(65 downto 0);
signal tx_snoop_ram_ena : std_logic;
signal tx_rd_ram_sel : std_logic;
signal rx_wr_ram_addr : std_logic_vector( 9 downto 0);
signal rx_wr_ram_data : std_logic_vector(17 downto 0);
signal rx_wr_ram_data : std_logic_vector(65 downto 0);
signal rx_wr_ram_ena : std_logic;
signal rx_rd_ram_addr : std_logic_vector( 9 downto 0);
signal rx_rd_ram_data : std_logic_vector(17 downto 0);
signal rx_rd_ram_data : std_logic_vector(65 downto 0);
signal tx_src_in : t_wrf_source_in;
signal tx_src_out : t_wrf_source_out;
signal tx_src_out : t_wrf_source64_out;
signal inject_req : std_logic;
signal inject_ready : std_logic;
......@@ -312,7 +312,7 @@ begin
U_TX_RAM : generic_dpram
generic map (
g_data_width => 18,
g_data_width => 66,
g_size => 1024,
g_dual_clock => false)
port map (
......@@ -329,7 +329,7 @@ begin
tx_rd_ram_addr <= tx_snoop_ram_addr when(tx_snoop_ram_ena ='1') else
s_regs_fromwb.ptd_tx_ram_rd_adr_o;
tx_snoop_ram_data <= tx_rd_ram_data;
s_regs_towb.ptd_tx_ram_rd_dat_i <= tx_rd_ram_data;
s_regs_towb.ptd_tx_ram_rd_dat_i <= tx_rd_ram_data(17 downto 0);
s_regs_towb.ptd_tx_ram_dat_valid_i <= not tx_snoop_ram_ena;
......@@ -373,7 +373,7 @@ begin
U_RX_RAM : generic_dpram
generic map (
g_data_width => 18,
g_data_width => 66,
g_size => 1024,
g_dual_clock => false)
port map (
......
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