Simplifies synthesis of separate blocks.

The ref_clk wasn't connected to from_phys record.
The rdy flag was constant 0.

It caused a warning.

Seems like the clock names has changed and these commands caused critical warnings.
I'm not implementing the design for now so it doesn't matter.

Probably a bug introduced during rebase.

99dc19ae4b9ab761d8c0a4bbce9280b41afe19d4

[PSU] debug read-out now between frame snooping (changed control of debug read) and fixed bug of clockClass match/injection

[PSU] added signal from rt_subsystem to cler bit indicatign announce, writing to RAM seq_id after verifying announce (at the end) and many other modifications

adding difault value of new scb_top_bare.vhd input so that all the old stuff works fine (e.g. simulation)

Vivado couldn't place them in previously specified bank.

Vivado couldn't decide which standard to use.

No changes actually

Just to try implementation....

Pinout is random.
No timing exeptions.

The delay resolution has changed.

Fixed data rate in the transceivers IP core  (1 Gb -> 1.25 Gb)
Disabled RX buffer