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White Rabbit Switch - Gateware
Commit 036cbead authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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update submodules to include preamble shrinkage support

parent 1d500455
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Showing with 167 additions and 115 deletions
Manifest.py
View file @ 036cbead
......@@ -10,6 +10,7 @@ modules = { "local" : [
"modules/wrsw_hwiu",
"modules/wrsw_watchdog",
"platform/virtex6/chipscope",
"platform/xilinx"],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git" ]
"platform/xilinx",
"ip_cores/wr-cores",
"ip_cores/general-cores"],
};
general-cores @ 26e8832c
Subproject commit 9c2a6c16dc41ce2a19131baf73539c1758a5e32d
Subproject commit 26e8832cfff48753681f0ec2be160969454cc4d9
wr-cores @ 4589bf4f
Subproject commit 3c2a6c72fd6e6c1594212b03d75ed2c8863cb8b3
Subproject commit 4589bf4f519f35c7fa5d8fd656bb5f57b2bd185f
modules/wrsw_hwiu/wrsw_hwiu.vhd
View file @ 036cbead
......@@ -64,8 +64,7 @@ entity wrsw_hwiu is
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic);
wb_stall_o : out std_logic);
end wrsw_hwiu;
architecture behav of wrsw_hwiu is
......@@ -123,6 +122,5 @@ begin
wb_dat_o <= wb_out.dat;
wb_ack_o <= wb_out.ack;
wb_stall_o <= wb_out.stall;
wb_int_o <= wb_out.int;
end behav;
modules/wrsw_hwiu/xwrsw_hwiu.vhd
View file @ 036cbead
......@@ -126,7 +126,6 @@ begin
wb_out.err <= '0';
wb_out.rty <= '0';
wb_out.int <= '0';
U_WB_Slave : hwiu_wishbone_slave
port map(
......
modules/wrsw_nic/wrsw_nic.vhd
View file @ 036cbead
......@@ -106,7 +106,7 @@ entity wrsw_nic is
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic
int_o : out std_logic
);
......@@ -135,7 +135,8 @@ architecture rtl of wrsw_nic is
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
wb_o : out t_wishbone_slave_out;
int_o : out std_logic);
end component;
signal snk_out : t_wrf_sink_out;
......@@ -171,7 +172,8 @@ begin
rtu_rsp_valid_o => rtu_rsp_valid_o,
rtu_rsp_ack_i => rtu_rsp_ack_i,
wb_i => wb_in,
wb_o => wb_out);
wb_o => wb_out,
int_o => int_o);
-- WBP Master (TX)
src_dat_o <= src_out.dat;
......@@ -204,6 +206,5 @@ begin
wb_dat_o <= wb_out.dat;
wb_ack_o <= wb_out.ack;
wb_stall_o <= wb_out.stall;
wb_int_o <= wb_out.int;
end rtl;
modules/wrsw_nic/xwrsw_nic.vhd
View file @ 036cbead
......@@ -97,6 +97,7 @@ entity xwrsw_nic is
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
int_o: out std_logic;
-------------------------------------------------------------------------------
-- RMON events
......@@ -363,7 +364,7 @@ begin -- rtl
wb_we_i => wb_in.we,
wb_ack_o => wb_ack_slave,
wb_stall_o=> wb_out.stall,
wb_int_o => wb_out.int,
wb_int_o => int_o,
regs_o => regs_fromwb,
......
modules/wrsw_pstats/xwrsw_pstats.vhd
View file @ 036cbead
......@@ -57,7 +57,8 @@ entity xwrsw_pstats is
events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
wb_o : out t_wishbone_slave_out;
int_o: out std_logic);
end xwrsw_pstats;
architecture wrapper of xwrsw_pstats is
......@@ -130,6 +131,6 @@ begin
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
wb_int_o => wb_out.int);
wb_int_o => int_o);
end wrapper;
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 036cbead
......@@ -60,8 +60,12 @@ entity wrsw_rt_subsystem is
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
rst_periph_ref_n_i : in std_logic;
rst_n_o : out std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
......@@ -142,7 +146,10 @@ architecture rtl of wrsw_rt_subsystem is
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
......@@ -158,36 +165,13 @@ architecture rtl of wrsw_rt_subsystem is
dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic);
end component;
component xwr_pps_gen
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_ref_clock_rate : integer;
g_ext_clock_rate : integer;
g_with_ext_clock_input : boolean);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_ext_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_valid_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic);
end component;
component xwrsw_gen_10mhz
generic (
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
......@@ -284,7 +268,7 @@ begin -- rtl
g_sdb_addr => c_rtbar_sdb_address)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
......@@ -312,7 +296,7 @@ begin -- rtl
g_slave2_granularity => BYTE)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
slave1_i => cnx_master_out(c_SLAVE_DPRAM),
slave1_o => cnx_master_in(c_SLAVE_DPRAM),
slave2_i => cpu_iwb_out,
......@@ -326,7 +310,7 @@ begin -- rtl
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_SLAVE_UART),
slave_o => cnx_master_in(c_SLAVE_UART),
desc_o => open,
......@@ -349,7 +333,10 @@ begin -- rtl
g_ext_clock_rate => 10000000)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_sys_n_i => rst_sys_n_i,
rst_ref_n_i => rst_ref_n_i,
rst_ext_n_i => rst_ext_n_i,
rst_dmtd_n_i => rst_dmtd_n_i,
clk_ref_i => clk_rx_vec,
clk_fb_i(0) => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
......@@ -367,9 +354,10 @@ begin -- rtl
out_locked_o => open,
slave_i => cnx_master_out(c_SLAVE_SOFTPLL),
slave_o => cnx_master_in(c_SLAVE_SOFTPLL),
int_o => cpu_irq_vec(0),
debug_o => spll_dbg_o);
U_PPS_Gen : xwr_pps_gen
U_PPS_Gen : entity work.xwr_pps_gen
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
......@@ -379,14 +367,15 @@ begin -- rtl
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
clk_ext_i => clk_ext_i,
rst_n_i => gpio_out(3),
rst_ref_n_i => rst_periph_ref_n_i,
rst_sys_n_i => gpio_out(3),
slave_i => cnx_master_out(c_SLAVE_PPSGEN),
slave_o => cnx_master_in(c_SLAVE_PPSGEN),
pps_in_i => pps_ext_i,
pps_csync_o => pps_csync,
pps_out_o => pps_ext_o,
pps_valid_o => pps_valid,
link_ok_i => '1',
tm_utc_o => tm_utc_o,
tm_cycles_o => tm_cycles_o,
tm_time_valid_o => tm_time_valid_o);
......@@ -394,7 +383,6 @@ begin -- rtl
pps_csync_o <= pps_csync;
pps_valid_o <= pps_valid;
cpu_irq_vec(0) <= cnx_master_in(2).int;
cpu_irq_vec(31 downto 1) <= (others => '0');
U_SPI_Master : xwb_spi
......@@ -406,7 +394,7 @@ begin -- rtl
g_num_slaves => 1)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_SLAVE_SPI),
slave_o => cnx_master_in(c_SLAVE_SPI),
desc_o => open,
......@@ -423,7 +411,7 @@ begin -- rtl
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_SLAVE_GPIO),
slave_o => cnx_master_in(c_SLAVE_GPIO),
desc_o => open,
......@@ -439,7 +427,7 @@ begin -- rtl
g_period => 625) -- 10us tick period
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_SLAVE_TIMER),
slave_o => cnx_master_in(c_SLAVE_TIMER),
desc_o => open);
......@@ -449,7 +437,7 @@ begin -- rtl
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
clk_i => clk_sys_i,
pps_i => pps_csync,
pps_valid_i => pps_valid,
......@@ -464,7 +452,7 @@ begin -- rtl
sel_clk_sys_o <= gpio_out(0);
pll_reset_n_o <= gpio_out(1);
cpu_reset_n <= not gpio_out(2) and rst_n_i;
cpu_reset_n <= not gpio_out(2) and rst_sys_n_i;
rst_n_o <= gpio_out(3);
U_Main_DAC : gc_serial_dac
......@@ -475,7 +463,7 @@ begin -- rtl
g_sclk_polarity => 0)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
value_i => dac_out_data,
cs_sel_i => "1",
load_i => dac_out_load,
......@@ -492,7 +480,7 @@ begin -- rtl
g_sclk_polarity => 0)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
rst_n_i => rst_sys_n_i,
value_i => dac_dmtd_data,
cs_sel_i => "1",
load_i => dac_dmtd_load,
......
modules/wrsw_rtu/rtu_port_new.vhd
View file @ 036cbead
......@@ -63,6 +63,7 @@ use work.rtu_private_pkg.all;
use work.genram_pkg.all;
use work.wrsw_shared_types_pkg.all;
use work.pack_unpack_pkg.all;
use work.gencores_pkg.all;
entity rtu_port_new is
generic(
......
modules/wrsw_rtu/rtu_private_pkg.vhd
View file @ 036cbead
......@@ -172,8 +172,6 @@ package rtu_private_pkg is
function f_fast_match_mac_lookup(match_config : t_rtu_special_traffic_config;
in_mac : std_logic_vector(47 downto 0)
) return std_logic;
function f_pick (condition : boolean; w_true : std_logic_vector; w_false : std_logic_vector)
return std_logic_vector;
function f_fast_match_response(vlan_entry : t_rtu_vlan_tab_entry;
rq_prio : std_logic_vector;
rq_has_prio : std_logic;
......@@ -600,19 +598,6 @@ package body rtu_private_pkg is
end function f_fast_match_mac_lookup;
function f_pick (
condition : boolean;
w_true : std_logic_vector;
w_false : std_logic_vector) return std_logic_vector is
begin
if(condition) then
return w_true;
else
return w_false;
end if;
end function f_pick;
function f_fast_match_response(vlan_entry : t_rtu_vlan_tab_entry;
rq_prio : std_logic_vector;
rq_has_prio : std_logic;
......
modules/wrsw_rtu/xwrsw_rtu_new.vhd
View file @ 036cbead
......@@ -161,7 +161,8 @@ entity xwrsw_rtu_new is
links_up_i : in std_logic_vector(g_port_mask_bits-1 downto 0);
rmon_events_o : out std_logic_vector(g_num_ports*g_rmon_events_bits_pp-1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
wb_o : out t_wishbone_slave_out;
int_o : out std_logic
);
end xwrsw_rtu_new;
......@@ -619,7 +620,7 @@ begin
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_int_o => wb_out.int,
wb_int_o => int_o,
wb_stall_o => open,
clk_match_i => clk_sys_i,
regs_o => regs_fromwb,
......
modules/wrsw_swcore/xswc_core.vhd
View file @ 036cbead
......@@ -412,7 +412,6 @@ architecture rtl of xswc_core is
wb_out.err <= '0';
wb_out.rty <= '0';
wb_out.int <= '0';
U_WB_SLAVE : swc_wishbone_slave
port map (
......
modules/wrsw_txtsu/xwrsw_txtsu.vhd
View file @ 036cbead
......@@ -85,8 +85,9 @@ entity xwrsw_tx_tsu is
-- Wishbone bus
-------------------------------------------------------------------------------
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
int_o : out std_logic
);
......@@ -226,7 +227,7 @@ begin -- syn
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_int_o => wb_out.int,
wb_int_o => int_o,
txtsu_tsf_wr_req_i => txtsu_tsf_wr_req,
txtsu_tsf_wr_full_o => txtsu_tsf_wr_full,
txtsu_tsf_wr_empty_o => txtsu_tsf_wr_empty,
......
modules/wrsw_watchdog/xwrsw_watchdog.vhd
View file @ 036cbead
......@@ -99,7 +99,6 @@ begin
wb_out.err <= '0';
wb_out.rty <= '0';
wb_out.int <= '0';
U_WB_Slave : wdog_wishbone_slave
port map(
......
top/bare_top/scb_top_bare.vhd
View file @ 036cbead
......@@ -310,11 +310,24 @@ architecture rtl of scb_top_bare is
--TEMP
signal dummy_events : std_logic_vector(c_NUM_PORTS*2-1 downto 0);
-- resynced resets
signal rst_periph_ref_n : std_logic;
signal rst_periph_dmtd_n : std_logic;
signal rst_periph_rxclk_n: std_logic_vector(c_NUM_PORTS-1 downto 0);
signal rst_ref_n : std_logic;
signal rst_ext_n : std_logic;
signal rst_dmtd_n : std_logic;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
signal vic_irqs : std_logic_vector(c_NUM_IRQS-1 downto 0);
signal txtsu_irq : std_logic;
signal nic_irq : std_logic;
signal rtu_irq : std_logic;
signal pstats_irq: std_logic;
type t_trig is array(integer range <>) of std_logic_vector(31 downto 0);
signal control0 : std_logic_vector(35 downto 0);
......@@ -491,6 +504,56 @@ begin
data_i => sys_rst_n_i,
synced_o => rst_n_sys);
U_sync_rst_ref : gc_sync_ffs
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => sys_rst_n_i,
synced_o => rst_ref_n);
U_sync_rst_dmtd : gc_sync_ffs
port map (
clk_i => clk_dmtd_i,
rst_n_i => '1',
data_i => sys_rst_n_i,
synced_o => rst_dmtd_n);
U_sync_rst_ext : gc_sync_ffs
port map (
clk_i => pll_status_i,
rst_n_i => '1',
data_i => sys_rst_n_i,
synced_o => rst_ext_n);
U_sync_rst_periph_ref : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => rst_n_periph,
synced_o => rst_periph_ref_n);
U_sync_rst_periph_dmtd : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_dmtd_i,
rst_n_i => '1',
data_i => rst_n_periph,
synced_o => rst_periph_dmtd_n);
gen_rst_periph_rxclk : for i in 0 to c_NUM_PORTS-1 generate
U_sync_reset_rxclk: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phys_i(i).rx_clk,
rst_n_i => '1',
data_i => rst_n_periph,
synced_o => rst_periph_rxclk_n(i));
end generate;
p_gen_sel_clk_sys : process(sys_rst_n_i, clk_sys)
begin
if sys_rst_n_i = '0' then
......@@ -521,7 +584,11 @@ begin
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
rst_n_i => rst_n_sys,
rst_sys_n_i => rst_n_sys,
rst_ref_n_i => rst_ref_n,
rst_ext_n_i => rst_ext_n,
rst_dmtd_n_i => rst_dmtd_n,
rst_periph_ref_n_i => rst_periph_ref_n,
rst_n_o => rst_n_periph,
wb_i => cnx_master_out(c_SLAVE_RT_SUBSYSTEM),
wb_o => cnx_master_in(c_SLAVE_RT_SUBSYSTEM),
......@@ -621,6 +688,7 @@ begin
rtu_rsp_ack_i => rtu_rsp_ack(c_NUM_PORTS),
wb_i => cnx_master_out(c_SLAVE_NIC),
wb_o => cnx_master_in(c_SLAVE_NIC),
int_o => nic_irq,
rmon_events_o => nic_events);
rtu_rsp(c_NUM_PORTS).hp <= '0';
......@@ -665,19 +733,24 @@ begin
g_with_packet_injection => f_logic2bool(g_inj_per_EP(i)),
g_use_new_rxcrc => true,
g_use_new_txcrc => false,
g_with_stop_traffic => g_with_watchdog)
g_with_stop_traffic => g_with_watchdog,
g_ep_idx => i)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd_i,
rst_n_i => rst_n_periph,
rst_sys_n_i => rst_n_periph,
rst_ref_n_i => rst_periph_ref_n,
rst_dmtd_n_i => rst_periph_dmtd_n,
rst_txclk_n_i => rst_periph_ref_n,
rst_rxclk_n_i => rst_periph_rxclk_n(i),
pps_csync_p1_i => pps_csync,
pps_valid_i => pps_valid,
phy_rst_o => phys_o(i).rst,
phy_loopen_o => phys_o(i).loopen,
phy_enable_o => phys_o(i).enable,
phy_rdy_i => phys_i(i).rdy,
phy_ref_clk_i => phys_i(i).ref_clk,
phy_tx_data_o => ep_dbg_data_array(i), -- phys_o(i).tx_data, --
......@@ -891,7 +964,8 @@ begin
-------------------------------
rmon_events_o => rtu_events,
wb_i => cnx_master_out(c_SLAVE_RTU),
wb_o => cnx_master_in(c_SLAVE_RTU));
wb_o => cnx_master_in(c_SLAVE_RTU),
int_o => rtu_irq);
gen_TRU : if(g_with_TRU = true) generate
U_TRU: xwrsw_tru
......@@ -982,7 +1056,8 @@ begin
timestamps_i => txtsu_timestamps,
timestamps_ack_o => txtsu_timestamps_ack,
wb_i => cnx_master_out(c_SLAVE_TXTSU),
wb_o => cnx_master_in(c_SLAVE_TXTSU));
wb_o => cnx_master_in(c_SLAVE_TXTSU),
int_o => txtsu_irq);
--TRIG2(15 downto 0) <= txtsu_timestamps(0).frame_id;
......@@ -1046,13 +1121,14 @@ begin
events_i => rmon_events,
wb_i => cnx_master_out(c_SLAVE_PSTATS),
wb_o => cnx_master_in(c_SLAVE_PSTATS));
wb_o => cnx_master_in(c_SLAVE_PSTATS),
int_o => pstats_irq);
end generate;
gen_no_PSTATS: if(g_with_PSTATS = false) generate
cnx_master_in(c_SLAVE_PSTATS).ack <= '1';
cnx_master_in(c_SLAVE_PSTATS).int <= '0';
pstats_irq <= '0';
end generate;
gen_events_assemble : for i in 0 to c_NUM_PORTS-1 generate
......@@ -1119,10 +1195,10 @@ begin
-- Interrupt assignment
-----------------------------------------------------------------------------
vic_irqs(0) <= cnx_master_in(c_SLAVE_NIC).int;
vic_irqs(1) <= cnx_master_in(c_SLAVE_TXTSU).int;
vic_irqs(2) <= cnx_master_in(c_SLAVE_RTU).int;
vic_irqs(3) <= cnx_master_in(c_SLAVE_PSTATS).int;
vic_irqs(0) <= nic_irq;
vic_irqs(1) <= txtsu_irq;
vic_irqs(2) <= rtu_irq;
vic_irqs(3) <= pstats_irq;
-------------------------------------------------------------------------------
-- Various constant-driven I/Os
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 036cbead
......@@ -171,7 +171,8 @@ package wrsw_components_pkg is
timestamps_i : in t_txtsu_timestamp_array(g_num_ports-1 downto 0);
timestamps_ack_o : out std_logic_vector(g_num_ports -1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
wb_o : out t_wishbone_slave_out;
int_o : out std_logic);
end component;
component xwrsw_nic
......@@ -197,6 +198,7 @@ package wrsw_components_pkg is
rtu_rsp_ack_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
int_o : out std_logic;
rmon_events_o : out std_logic_vector(g_port_mask_bits*g_rmon_events_pp-1 downto 0));
end component;
......@@ -215,7 +217,11 @@ package wrsw_components_pkg is
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
rst_n_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
rst_periph_ref_n_i : in std_logic;
rst_n_o : out std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
......@@ -361,7 +367,8 @@ package wrsw_components_pkg is
links_up_i : in std_logic_vector(g_port_mask_bits-1 downto 0);
rmon_events_o : out std_logic_vector(g_num_ports*g_rmon_events_bits_pp-1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
wb_o : out t_wishbone_slave_out;
int_o : out std_logic
);
end component;
......@@ -379,7 +386,8 @@ package wrsw_components_pkg is
events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out );
wb_o : out t_wishbone_slave_out;
int_o: out std_logic);
end component;
component xwrsw_hwiu
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 036cbead
......@@ -171,7 +171,8 @@ package wrsw_top_pkg is
timestamps_i : in t_txtsu_timestamp_array(g_num_ports-1 downto 0);
timestamps_ack_o : out std_logic_vector(g_num_ports -1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
wb_o : out t_wishbone_slave_out;
int_o : out std_logic);
end component;
component xwrsw_nic
......@@ -197,6 +198,7 @@ package wrsw_top_pkg is
rtu_rsp_ack_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
int_o : out std_logic;
rmon_events_o : out std_logic_vector(g_port_mask_bits*g_rmon_events_pp-1 downto 0));
end component;
......@@ -216,7 +218,11 @@ package wrsw_top_pkg is
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
rst_n_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
rst_periph_ref_n_i : in std_logic;
rst_n_o : out std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
......@@ -419,7 +425,8 @@ package wrsw_top_pkg is
links_up_i : in std_logic_vector(g_port_mask_bits-1 downto 0);
rmon_events_o : out std_logic_vector(g_num_ports*g_rmon_events_bits_pp-1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
wb_o : out t_wishbone_slave_out;
int_o : out std_logic
);
end component;
......@@ -446,7 +453,8 @@ package wrsw_top_pkg is
events_i : in std_logic_vector(g_nports*g_cnt_pp-1 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out );
wb_o : out t_wishbone_slave_out;
int_o: out std_logic);
end component;
component xwrsw_watchdog
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 036cbead
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