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White Rabbit Switch - Gateware
Commits
095c800f
Commit
095c800f
authored
Jul 10, 2019
by
Grzegorz Daniluk
Browse files
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Plain Diff
rt_subsystem: add external samplers for port that are not calibrated for low phase drift
parent
1b4724a5
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Showing
7 changed files
with
261 additions
and
242 deletions
+261
-242
wrsw_rt_subsystem.vhd
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+25
-3
wrsw_shared_types_pkg.vhd
modules/wrsw_shared_types_pkg.vhd
+3
-0
scb_top_bare.vhd
top/bare_top/scb_top_bare.vhd
+3
-2
wrsw_components_pkg.vhd
top/bare_top/wrsw_components_pkg.vhd
+2
-1
wrsw_top_pkg.vhd
top/bare_top/wrsw_top_pkg.vhd
+6
-3
scb_top_synthesis.ucf
top/scb_18ports/scb_top_synthesis.ucf
+103
-116
scb_top_synthesis.vhd
top/scb_18ports/scb_top_synthesis.vhd
+119
-117
No files found.
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @
095c800f
...
...
@@ -40,6 +40,7 @@ use ieee.std_logic_1164.all;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wrs_sdb_pkg
.
all
;
use
work
.
wrsw_shared_types_pkg
.
all
;
entity
wrsw_rt_subsystem
is
...
...
@@ -48,7 +49,7 @@ entity wrsw_rt_subsystem is
g_num_rx_clocks
:
integer
;
g_num_ext_clks
:
integer
;
g_simulation
:
boolean
;
g_
use_sampled_rx_clocks
:
boolean
);
g_
phy_lpcalib
:
t_bool_array
(
0
to
17
)
);
port
(
clk_ref_i
:
in
std_logic
;
...
...
@@ -238,7 +239,6 @@ architecture rtl of wrsw_rt_subsystem is
begin
-- rtl
clk_rx_vec
(
g_num_rx_clocks
-1
downto
0
)
<=
clk_rx_i
;
clk_rx_sampled_vec
(
g_num_rx_clocks
-1
downto
0
)
<=
clk_rx_sampled_i
;
cnx_slave_in
(
c_MASTER_CPU
)
<=
wb_i
;
wb_o
<=
cnx_slave_out
(
c_MASTER_CPU
);
...
...
@@ -303,6 +303,28 @@ begin -- rtl
uart_txd_o
=>
uart_txd_o
);
-----------------------------------------------------------------------------
-- External sampler for rx clocks coming from GTX-es that are not
-- calibrated for low phase drift
-----------------------------------------------------------------------------
gen_Samplers
:
for
I
in
0
to
g_num_rx_clocks
-1
generate
gen_lp
:
if
g_phy_lpcalib
(
I
)
generate
clk_rx_sampled_vec
(
I
)
<=
clk_rx_sampled_i
(
I
);
end
generate
gen_lp
;
gen_no_lp
:
if
not
g_phy_lpcalib
(
I
)
generate
U_Sampler
:
entity
work
.
dmtd_sampler
generic
map
(
g_divide_input_by_2
=>
false
,
g_reverse
=>
true
)
port
map
(
clk_in_i
=>
clk_rx_vec
(
I
),
clk_dmtd_i
=>
clk_dmtd_i
,
clk_sampled_o
=>
clk_rx_sampled_vec
(
I
));
end
generate
gen_no_lp
;
end
generate
gen_Samplers
;
-----------------------------------------------------------------------------
U_SoftPLL
:
entity
work
.
xwr_softpll_ng
generic
map
(
g_tag_bits
=>
22
,
...
...
@@ -316,7 +338,7 @@ begin -- rtl
g_with_debug_fifo
=>
true
,
g_ref_clock_rate
=>
62500000
,
g_ext_clock_rate
=>
10000000
,
g_use_sampled_ref_clocks
=>
g_use_sampled_rx_clocks
)
g_use_sampled_ref_clocks
=>
true
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_sys_n_i
=>
rst_sys_n_i
,
...
...
modules/wrsw_shared_types_pkg.vhd
View file @
095c800f
...
...
@@ -39,6 +39,9 @@ package wrsw_shared_types_pkg is
constant
c_RTU_MAX_PORTS
:
integer
:
=
32
;
constant
c_SWC_MAX_PORTS
:
integer
:
=
c_RTU_MAX_PORTS
+
1
;
type
t_bool_array
is
array
(
integer
range
<>
)
of
boolean
;
constant
c_BOOL_FALSE_ARRAY
:
t_bool_array
(
0
to
17
)
:
=
(
others
=>
false
);
type
t_rtu_request
is
record
valid
:
std_logic
;
smac
:
std_logic_vector
(
47
downto
0
);
...
...
top/bare_top/scb_top_bare.vhd
View file @
095c800f
...
...
@@ -64,7 +64,8 @@ entity scb_top_bare is
g_with_PSTATS
:
boolean
:
=
true
;
g_with_muxed_CS
:
boolean
:
=
false
;
g_with_watchdog
:
boolean
:
=
false
;
g_inj_per_EP
:
std_logic_vector
(
17
downto
0
)
:
=
(
others
=>
'0'
)
g_inj_per_EP
:
std_logic_vector
(
17
downto
0
)
:
=
(
others
=>
'0'
);
g_phy_lpcalib
:
t_bool_array
(
0
to
17
)
:
=
c_BOOL_FALSE_ARRAY
);
port
(
sys_rst_n_i
:
in
std_logic
;
-- global reset
...
...
@@ -614,7 +615,7 @@ begin
g_num_rx_clocks
=>
c_NUM_PORTS
,
g_num_ext_clks
=>
2
,
g_simulation
=>
g_simulation
,
g_
use_sampled_rx_clocks
=>
true
)
g_
phy_lpcalib
=>
g_phy_lpcalib
)
port
map
(
clk_ref_i
=>
clk_ref_i
,
clk_sys_i
=>
clk_sys
,
...
...
top/bare_top/wrsw_components_pkg.vhd
View file @
095c800f
...
...
@@ -118,7 +118,8 @@ package wrsw_components_pkg is
component
wr_gtx_phy_virtex6
generic
(
g_simulation
:
integer
;
g_use_slave_tx_clock
:
integer
);
g_use_slave_tx_clock
:
integer
;
g_rxclk_bufr
:
boolean
);
port
(
clk_ref_i
:
in
std_logic
;
tx_clk_i
:
in
std_logic
;
...
...
top/bare_top/wrsw_top_pkg.vhd
View file @
095c800f
...
...
@@ -149,7 +149,8 @@ package wrsw_top_pkg is
generic
(
g_simulation
:
integer
;
g_use_slave_tx_clock
:
integer
;
g_use_bufr
:
boolean
:
=
false
;
g_rxclk_bufr
:
boolean
:
=
false
;
g_txclk_bufr
:
boolean
:
=
false
;
g_id
:
integer
);
port
(
clk_ref_i
:
in
std_logic
;
...
...
@@ -246,7 +247,8 @@ package wrsw_top_pkg is
g_num_rx_clocks
:
integer
;
g_num_ext_clks
:
integer
;
g_simulation
:
boolean
;
g_use_sampled_rx_clocks
:
boolean
);
g_phy_lpcalib
:
t_bool_array
(
0
to
17
));
port
(
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
...
...
@@ -338,7 +340,8 @@ package wrsw_top_pkg is
g_with_PSTATS
:
boolean
:
=
true
;
g_with_muxed_CS
:
boolean
:
=
false
;
g_with_watchdog
:
boolean
:
=
false
;
g_inj_per_EP
:
std_logic_vector
(
17
downto
0
)
:
=
(
others
=>
'0'
));
g_inj_per_EP
:
std_logic_vector
(
17
downto
0
)
:
=
(
others
=>
'0'
);
g_phy_lpcalib
:
t_bool_array
(
0
to
17
)
:
=
c_BOOL_FALSE_ARRAY
);
port
(
sys_rst_n_i
:
in
std_logic
;
clk_startup_i
:
in
std_logic
;
...
...
top/scb_18ports/scb_top_synthesis.ucf
View file @
095c800f
This diff is collapsed.
Click to expand it.
top/scb_18ports/scb_top_synthesis.vhd
View file @
095c800f
...
...
@@ -44,6 +44,7 @@ use work.wr_fabric_pkg.all;
use
work
.
endpoint_pkg
.
all
;
use
work
.
wr_txtsu_pkg
.
all
;
use
work
.
wrsw_top_pkg
.
all
;
use
work
.
wrsw_shared_types_pkg
.
all
;
library
UNISIM
;
...
...
@@ -345,7 +346,8 @@ architecture Behavioral of scb_top_synthesis is
g_with_PSTATS
:
boolean
;
g_with_muxed_CS
:
boolean
;
g_with_watchdog
:
boolean
;
g_inj_per_EP
:
std_logic_vector
(
17
downto
0
));
g_inj_per_EP
:
std_logic_vector
(
17
downto
0
);
g_phy_lpcalib
:
t_bool_array
(
0
to
17
)
:
=
c_BOOL_FALSE_ARRAY
);
port
(
sys_rst_n_i
:
in
std_logic
;
clk_startup_i
:
in
std_logic
;
...
...
@@ -438,51 +440,55 @@ architecture Behavioral of scb_top_synthesis is
signal
TRIG2
:
std_logic_vector
(
31
downto
0
);
signal
TRIG3
:
std_logic_vector
(
31
downto
0
);
type
t_bufr_phy_assignment_array
is
array
(
integer
range
<>
)
of
boolean
;
constant
c_phy_use_bufr_for_rx_clock
:
t_bufr_phy_assignment_array
(
0
to
17
)
:
=
(
false
,
-- 0
false
,
false
,
false
,
false
,
false
,
false
,
false
,
-- 7
false
,
false
,
false
,
-- 10
false
,
false
,
false
,
false
,
false
,
true
,
true
);
type
t_phy_conf
is
record
rxclk_bufr
:
boolean
;
txclk_bufr
:
boolean
;
end
record
;
type
t_phy_conf_array
is
array
(
integer
range
<>
)
of
t_phy_conf
;
constant
c_PHY_CONF
:
t_phy_conf_array
(
0
to
17
)
:
=
(
-- rx_bufr, tx_bufr
0
=>
(
false
,
true
),
1
=>
(
false
,
true
),
2
=>
(
false
,
true
),
3
=>
(
false
,
true
),
4
=>
(
false
,
false
),
5
=>
(
false
,
false
),
6
=>
(
false
,
false
),
7
=>
(
false
,
false
),
8
=>
(
false
,
true
),
9
=>
(
false
,
true
),
10
=>
(
false
,
true
),
11
=>
(
false
,
true
),
12
=>
(
false
,
false
),
13
=>
(
false
,
false
),
14
=>
(
false
,
false
),
15
=>
(
false
,
false
),
16
=>
(
true
,
false
),
17
=>
(
true
,
false
)
);
constant
c_
phy_use_bufr_for_tx_clock
:
t_bufr_phy_assignment
_array
(
0
to
17
)
:
=
(
true
,
-- 0
true
,
true
,
true
,
fals
e
,
fals
e
,
fals
e
,
false
,
-- 7
true
,
true
,
true
,
-- 10
true
,
false
,
false
,
false
,
false
,
false
,
false
);
constant
c_
PHY_LPCALIB
:
t_bool
_array
(
0
to
17
)
:
=
(
0
=>
true
,
1
=>
true
,
2
=>
true
,
3
=>
true
,
4
=>
tru
e
,
5
=>
tru
e
,
6
=>
tru
e
,
7
=>
true
,
8
=>
true
,
9
=>
true
,
10
=>
true
,
11
=>
true
,
12
=>
false
,
13
=>
false
,
14
=>
false
,
15
=>
false
,
16
=>
false
,
17
=>
false
);
begin
...
...
@@ -760,77 +766,72 @@ begin
clk_gtx
(
13
downto
10
)
<=
(
others
=>
clk_gtx4_7
);
clk_gtx
(
17
downto
14
)
<=
(
others
=>
clk_gtx0_3
);
--generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr
:
for
i
in
0
to
3
generate
U_PHY
:
entity
work
.
wr_gtx_phy_virtex6_lp
generic
map
(
g_simulation
=>
f_bool2int
(
g_simulation
),
g_use_slave_tx_clock
=>
f_bool2int
(
i
/=
(
i
/
4
)
*
4
),
g_use_bufr_for_rx_clock
=>
c_phy_use_bufr_for_rx_clock
(
i
),
g_use_bufr_for_tx_clock
=>
c_phy_use_bufr_for_tx_clock
(
i
),
g_id
=>
i
)
port
map
(
clk_gtx_i
=>
clk_gtx
(
i
),
clk_ref_i
=>
clk_ref
,
clk_dmtd_i
=>
clk_dmtd
,
tx_data_i
=>
to_phys
(
i
)
.
tx_data
,
tx_k_i
=>
to_phys
(
i
)
.
tx_k
,
tx_disparity_o
=>
from_phys
(
i
)
.
tx_disparity
,
tx_enc_err_o
=>
from_phys
(
i
)
.
tx_enc_err
,
rx_rbclk_o
=>
from_phys
(
i
)
.
rx_clk
,
rx_rbclk_sampled_o
=>
from_phys
(
i
)
.
rx_sampled_clk
,
rx_data_o
=>
from_phys
(
i
)
.
rx_data
,
rx_k_o
=>
from_phys
(
i
)
.
rx_k
,
rx_enc_err_o
=>
from_phys
(
i
)
.
rx_enc_err
,
rx_bitslide_o
=>
from_phys
(
i
)
.
rx_bitslide
,
rst_i
=>
to_phys
(
i
)
.
rst
,
debug_o
=>
from_phys
(
i
)
.
debug
,
debug_i
=>
to_phys
(
i
)
.
debug
,
loopen_i
=>
to_phys
(
i
)
.
loopen
,
pad_txn_o
=>
gtx_txn_o
(
i
),
pad_txp_o
=>
gtx_txp_o
(
i
),
pad_rxn_i
=>
gtx_rxn_i
(
i
),
pad_rxp_i
=>
gtx_rxp_i
(
i
),
rdy_o
=>
from_phys
(
i
)
.
rdy
);
from_phys
(
i
)
.
ref_clk
<=
clk_ref
;
end
generate
gen_phys_bufr
;
gen_phys
:
for
i
in
4
to
c_NUM_PHYS
-1
generate
U_PHY
:
entity
work
.
wr_gtx_phy_virtex6_lp
generic
map
(
g_simulation
=>
f_bool2int
(
g_simulation
),
g_use_slave_tx_clock
=>
f_bool2int
(
i
/=
(
i
/
4
)
*
4
),
g_use_bufr_for_rx_clock
=>
c_phy_use_bufr_for_rx_clock
(
i
),
g_use_bufr_for_tx_clock
=>
c_phy_use_bufr_for_tx_clock
(
i
),
g_id
=>
i
)
port
map
(
clk_gtx_i
=>
clk_gtx
(
i
),
clk_ref_i
=>
clk_ref
,
clk_dmtd_i
=>
clk_dmtd
,
tx_data_i
=>
to_phys
(
i
)
.
tx_data
,
tx_k_i
=>
to_phys
(
i
)
.
tx_k
,
tx_disparity_o
=>
from_phys
(
i
)
.
tx_disparity
,
tx_enc_err_o
=>
from_phys
(
i
)
.
tx_enc_err
,
rx_rbclk_o
=>
from_phys
(
i
)
.
rx_clk
,
rx_rbclk_sampled_o
=>
from_phys
(
i
)
.
rx_sampled_clk
,
rx_data_o
=>
from_phys
(
i
)
.
rx_data
,
rx_k_o
=>
from_phys
(
i
)
.
rx_k
,
rx_enc_err_o
=>
from_phys
(
i
)
.
rx_enc_err
,
rx_bitslide_o
=>
from_phys
(
i
)
.
rx_bitslide
,
rst_i
=>
to_phys
(
i
)
.
rst
,
debug_o
=>
from_phys
(
i
)
.
debug
,
debug_i
=>
to_phys
(
i
)
.
debug
,
loopen_i
=>
to_phys
(
i
)
.
loopen
,
pad_txn_o
=>
gtx_txn_o
(
i
),
pad_txp_o
=>
gtx_txp_o
(
i
),
pad_rxn_i
=>
gtx_rxn_i
(
i
),
pad_rxp_i
=>
gtx_rxp_i
(
i
),
rdy_o
=>
from_phys
(
i
)
.
rdy
);
gen_phys
:
for
i
in
0
to
c_NUM_PHYS
-1
generate
-- Instantiate GTX with low phase drift calibration
gen_lp
:
if
c_PHY_LPCALIB
(
i
)
generate
U_PHY
:
entity
work
.
wr_gtx_phy_virtex6_lp
generic
map
(
g_simulation
=>
f_bool2int
(
g_simulation
),
g_rxclk_bufr
=>
c_PHY_CONF
(
i
)
.
rxclk_bufr
,
g_txclk_bufr
=>
c_PHY_CONF
(
i
)
.
txclk_bufr
,
g_id
=>
i
)
port
map
(
clk_gtx_i
=>
clk_gtx
(
i
),
clk_ref_i
=>
clk_ref
,
clk_dmtd_i
=>
clk_dmtd
,
tx_data_i
=>
to_phys
(
i
)
.
tx_data
,
tx_k_i
=>
to_phys
(
i
)
.
tx_k
,
tx_disparity_o
=>
from_phys
(
i
)
.
tx_disparity
,
tx_enc_err_o
=>
from_phys
(
i
)
.
tx_enc_err
,
rx_rbclk_o
=>
from_phys
(
i
)
.
rx_clk
,
clk_sampled_o
=>
from_phys
(
i
)
.
rx_sampled_clk
,
rx_data_o
=>
from_phys
(
i
)
.
rx_data
,
rx_k_o
=>
from_phys
(
i
)
.
rx_k
,
rx_enc_err_o
=>
from_phys
(
i
)
.
rx_enc_err
,
rx_bitslide_o
=>
from_phys
(
i
)
.
rx_bitslide
,
rst_i
=>
to_phys
(
i
)
.
rst
,
debug_o
=>
from_phys
(
i
)
.
debug
,
debug_i
=>
to_phys
(
i
)
.
debug
,
loopen_i
=>
to_phys
(
i
)
.
loopen
,
pad_txn_o
=>
gtx_txn_o
(
i
),
pad_txp_o
=>
gtx_txp_o
(
i
),
pad_rxn_i
=>
gtx_rxn_i
(
i
),
pad_rxp_i
=>
gtx_rxp_i
(
i
),
rdy_o
=>
from_phys
(
i
)
.
rdy
);
end
generate
gen_lp
;
-- Instantiate regular GTX for all other ports
gen_no_lp
:
if
not
c_PHY_LPCALIB
(
i
)
generate
U_PHY
:
entity
work
.
wr_gtx_phy_virtex6
generic
map
(
g_simulation
=>
f_bool2int
(
g_simulation
),
g_rxclk_bufr
=>
c_PHY_CONF
(
i
)
.
rxclk_bufr
)
port
map
(
clk_gtx_i
=>
clk_gtx
(
i
),
clk_ref_i
=>
clk_ref
,
tx_data_i
=>
to_phys
(
i
)
.
tx_data
,
tx_k_i
=>
to_phys
(
i
)
.
tx_k
,
tx_disparity_o
=>
from_phys
(
i
)
.
tx_disparity
,
tx_enc_err_o
=>
from_phys
(
i
)
.
tx_enc_err
,
rx_rbclk_o
=>
from_phys
(
i
)
.
rx_clk
,
rx_data_o
=>
from_phys
(
i
)
.
rx_data
,
rx_k_o
=>
from_phys
(
i
)
.
rx_k
,
rx_enc_err_o
=>
from_phys
(
i
)
.
rx_enc_err
,
rx_bitslide_o
=>
from_phys
(
i
)
.
rx_bitslide
,
rst_i
=>
to_phys
(
i
)
.
rst
,
loopen_i
=>
to_phys
(
i
)
.
loopen
,
pad_txn_o
=>
gtx_txn_o
(
i
),
pad_txp_o
=>
gtx_txp_o
(
i
),
pad_rxn_i
=>
gtx_rxn_i
(
i
),
pad_rxp_i
=>
gtx_rxp_i
(
i
),
rdy_o
=>
from_phys
(
i
)
.
rdy
);
from_phys
(
i
)
.
rx_sampled_clk
<=
'0'
;
from_phys
(
i
)
.
debug
<=
(
others
=>
'0'
);
end
generate
gen_no_lp
;
from_phys
(
i
)
.
ref_clk
<=
clk_ref
;
end
generate
gen_phys
;
...
...
@@ -860,7 +861,8 @@ begin
g_with_PSTATS
=>
true
,
g_with_muxed_CS
=>
false
,
g_with_watchdog
=>
true
,
g_inj_per_EP
=>
"00"
&
x"0000"
)
g_inj_per_EP
=>
"00"
&
x"0000"
,
g_phy_lpcalib
=>
c_PHY_LPCALIB
)
port
map
(
sys_rst_n_i
=>
sys_rst_n_i
,
clk_startup_i
=>
clk_sys_startup
,
...
...
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