Skip to content

W
White Rabbit Switch - Gateware
Commit 0b1aba5a authored by Mattia Rizzi's avatar Mattia Rizzi Committed by Grzegorz Daniluk
Browse files
Options

Added support for the external board

parent 85dd1047
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 2884 additions and 1374 deletions
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 0b1aba5a
......@@ -54,8 +54,8 @@ entity wrsw_rt_subsystem is
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
......@@ -67,6 +67,11 @@ entity wrsw_rt_subsystem is
rst_periph_ref_n_i : in std_logic;
rst_n_o : out std_logic;
-- WRS Low jitter daughterboard
clk_ext_db_i : in std_logic;
ext_board_detected_i : in std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
......@@ -124,6 +129,14 @@ entity wrsw_rt_subsystem is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- WRS Low jitter daughterboard AD9516
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
-- Debug
spll_dbg_o : out std_logic_vector(5 downto 0)
......@@ -157,6 +170,7 @@ architecture rtl of wrsw_rt_subsystem is
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_ext_db_i : in std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
......@@ -201,8 +215,8 @@ architecture rtl of wrsw_rt_subsystem is
-- 0x10300 - 0x10400: GPIO
-- 0x10400 - 0x10500: Timer
constant c_NUM_GPIO_PINS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 8;
constant c_NUM_GPIO_PINS : integer := 9;
constant c_NUM_WB_SLAVES : integer := 9;
constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1;
......@@ -215,7 +229,7 @@ architecture rtl of wrsw_rt_subsystem is
constant c_SLAVE_TIMER : integer := 5;
constant c_SLAVE_PPSGEN : integer := 6;
constant c_SLAVE_GEN10 : integer := 7;
constant c_SLAVE_SPI_EXT : integer := 8;
signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(1 downto 0);
......@@ -342,9 +356,10 @@ begin -- rtl
clk_fb_i(0) => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
pps_csync_p1_i => pps_csync,
clk_ext_db_i => clk_ext_db_i,
pps_csync_p1_i => pps_csync,
pps_ext_a_i => pps_ext_i,
dac_dmtd_data_o => dac_dmtd_data,
dac_dmtd_load_o => dac_dmtd_load,
......@@ -405,6 +420,25 @@ begin -- rtl
pad_mosi_o => pll_mosi_o,
pad_miso_i => pll_miso_i);
U_SPI_Master_external_board : xwb_spi
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_divider_len => 8,
g_max_char_len => 24,
g_num_slaves => 1)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_SLAVE_SPI_EXT),
slave_o => cnx_master_in(c_SLAVE_SPI_EXT),
desc_o => open,
pad_cs_o(0) => ext_pll_cs_n_o,
pad_sclk_o => ext_pll_sck_o,
pad_mosi_o => ext_pll_mosi_o,
pad_miso_i => ext_pll_miso_i);
U_GPIO : xwb_gpio_port
generic map (
g_interface_mode => PIPELINED,
......@@ -456,6 +490,11 @@ begin -- rtl
pll_reset_n_o <= gpio_out(1);
cpu_reset_n <= not gpio_out(2) and rst_sys_n_i;
rst_n_o <= gpio_out(3);
ext_pll_reset_n_o <= gpio_out(4);
gpio_in(5) <= ext_board_detected_i;
gpio_in(8 downto 6) <= ext_board_osc_freq_i;
U_Main_DAC : gc_serial_dac
generic map (
......
syn/scb_18ports/test_scb.xise
View file @ 0b1aba5a
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/scb_8ports/test_scb.xise
View file @ 0b1aba5a
This source diff could not be displayed because it is too large. You can view the blob instead.
top/bare_top/scb_top_bare.vhd
View file @ 0b1aba5a
......@@ -117,6 +117,12 @@ entity scb_top_bare is
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
-- WRS Low jitter daughterboard (db) external clock
clk_ext_db_i : in std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
ext_board_detected_i : in std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
......@@ -130,6 +136,13 @@ entity scb_top_bare is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
......@@ -583,8 +596,10 @@ begin
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_db_i => clk_ext_db_i,
ext_board_detected_i => ext_board_detected_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
......@@ -628,6 +643,15 @@ begin
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
ext_board_osc_freq_i => ext_board_osc_freq_i,
spll_dbg_o => spll_dbg_o);
U_DELAY_PPS: IODELAYE1
......
top/bare_top/wrs_sdb_pkg.vhd
View file @ 0b1aba5a
......@@ -237,7 +237,7 @@ package wrs_sdb_pkg is
name => "WRSW SWCORE ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(7 downto 0) :=
constant c_rtbar_layout : t_sdb_record_array(8 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
......@@ -245,7 +245,9 @@ package wrs_sdb_pkg is
4 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00010300"), --GPIO
5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"));--GEN 10MHz
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700")); --SPI ext
constant c_rtbar_sdb_address : t_wishbone_address := x"00010800";
constant c_rtbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address);
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 0b1aba5a
......@@ -224,6 +224,7 @@ package wrsw_components_pkg is
rst_dmtd_n_i : in std_logic;
rst_periph_ref_n_i : in std_logic;
rst_n_o : out std_logic;
clk_ext_db_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
dac_helper_sync_n_o : out std_logic;
......@@ -243,13 +244,21 @@ package wrsw_components_pkg is
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
ext_board_osc_freq_i: in std_logic_vector (2 downto 0);
ext_board_detected_i: in std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic);
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic);
end component;
component chipscope_icon
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 0b1aba5a
......@@ -216,6 +216,7 @@ package wrsw_top_pkg is
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_db_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
......@@ -254,6 +255,14 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_board_osc_freq_i: in std_logic_vector (2 downto 0);
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
ext_board_detected_i: in std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
end component;
......@@ -293,7 +302,9 @@ package wrsw_top_pkg is
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_ext_db_i : in std_logic;
ext_board_detected_i: in std_logic;
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ 0b1aba5a
This diff is collapsed.
top/scb_8ports/scb_top_synthesis.vhd
View file @ 0b1aba5a
......@@ -74,8 +74,6 @@ entity scb_top_synthesis is
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
clk_sys_dbg_o: out std_logic;
-------------------------------------------------------------------------------
-- Atmel EBI bus
......@@ -128,6 +126,32 @@ entity scb_top_synthesis is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- WRS Low Jitter board
ext_clk_10mhz_p_i : in std_logic;
ext_clk_10mhz_n_i : in std_logic;
ext_clk_62mhz_p_i : in std_logic;
ext_clk_62mhz_n_i : in std_logic;
ext_pll_status_i : in std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
ext_dac_main_sync_n_o : out std_logic;
ext_dac_main_sclk_o : out std_logic;
ext_dac_main_data_o : out std_logic;
ext_board_loopback_i : in std_logic;
ext_board_loopback_o : out std_logic;
ext_board_clk1_en : out std_logic;
ext_board_clk2_en : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
ext_board_rev_id_i : in std_logic_vector (2 downto 0);
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
......@@ -188,10 +212,7 @@ entity scb_top_synthesis is
sensors_sda_b: inout std_logic;
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
dbg_clk_ext_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0)
mb_fan2_pwm_o : out std_logic
);
end scb_top_synthesis;
......@@ -212,6 +233,7 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_i : in std_logic;
clk_ext_100_o : out std_logic;
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic);
end component;
......@@ -220,8 +242,21 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_100_i : in std_logic;
clk_ext_mul_o : out std_logic;
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic);
end component;
component ext_board_check is
generic (
g_pattern : std_logic_vector (63 downto 0) := x"CAFED00DCAFED00D";
g_clk_divider : integer := 16);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
loopback_i : in std_logic;
loopback_o : out std_logic;
board_detected_o : out std_logic);
end component;
constant c_NUM_PHYS : integer := 8;
......@@ -306,6 +341,13 @@ architecture Behavioral of scb_top_synthesis is
signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic;
signal ext_board_detected : std_logic := '0';
signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
signal ext_clk_62mhz : std_logic;
signal dac_main_sync_n : std_logic;
signal dac_main_sclk : std_logic;
signal dac_main_data : std_logic;
component scb_top_bare
generic (
g_num_ports : integer;
......@@ -324,8 +366,9 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_db_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
......@@ -349,6 +392,14 @@ architecture Behavioral of scb_top_synthesis is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
ext_board_detected_i : in std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
......@@ -395,7 +446,9 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
clk_sys_dbg_o <= clk_sys;
ext_board_clk1_en <= '1';
ext_board_clk2_en <= '1';
ext_pll_sync_n_o <= '1';
--chipscope_icon_1 : chipscope_icon
-- port map (
......@@ -489,7 +542,43 @@ begin
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_ext_clk_62mhz : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => ext_clk_62mhz,
I => ext_clk_62mhz_p_i,
IB => ext_clk_62mhz_n_i);
U_Buf_ext_clk10mhz : IBUFDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => ext_clk_10MHz,
I => ext_clk_10mhz_p_i,
IB => ext_clk_10mhz_n_i);
CLK_10MHZ_ext : BUFR
port map (
CE => '1',
CLR => '0',
I => ext_clk_10MHz,
O => ext_clk_10MHz_bufr);
BUFGMUX_inst : BUFGCTRL
port map (
IGNORE0 => '0',
IGNORE1 => '0',
CE0 => '1',
CE1 => '1',
O => clk_10mhz,
I0 => clk_ext,
I1 => ext_clk_10MHz_bufr,
S1 => ext_board_detected,
S0 => NOT ext_board_detected
);
U_Buf_CLK_DMTD : IBUFGDS
generic map (
......@@ -534,6 +623,39 @@ begin
CLKFBIN => pllout_clk_fb,
CLKIN => clk_25mhz);
-- Detect the external board (WRS Low jitter daughterboard)
ext_board_checker_inst : ext_board_check
generic map (
g_clk_divider => 16,
g_pattern => x"CAFED00DCAFED00D")
port map (
clk_sys_i => clk_sys,
rst_n_i => sys_rst_n_i,
loopback_i => ext_board_loopback_i,
loopback_o => ext_board_loopback_o,
board_detected_o => ext_board_detected
);
-- Redirect DAC output if external board detetected
dac_redirection : process (dac_main_sync_n, dac_main_sclk, dac_main_data)
begin
if (ext_board_detected = '0') then
dac_main_sync_n_o <= dac_main_sync_n;
dac_main_sclk_o <= dac_main_sclk;
dac_main_data_o <= dac_main_data;
ext_dac_main_sync_n_o <= '0';
ext_dac_main_sclk_o <= '0';
ext_dac_main_data_o <= '0';
else
dac_main_sync_n_o <= '0';
dac_main_sclk_o <= '0';
dac_main_data_o <= '0';
ext_dac_main_sync_n_o <= dac_main_sync_n;
ext_dac_main_sclk_o <= dac_main_sclk;
ext_dac_main_data_o <= dac_main_data;
end if;
end process;
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
......@@ -546,6 +668,7 @@ begin
clk_ext_i => clk_ext,
clk_ext_100_o => clk_ext_100,
rst_a_i => ext_pll_reset,
powerdown_i => ext_board_detected,
locked_o => ext_pll_100_locked);
U_Ext_PLL2: ext_pll_100_to_62m
......@@ -553,10 +676,11 @@ begin
clk_ext_100_i => clk_ext_100,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset,
powerdown_i => ext_board_detected,
locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
dbg_clk_ext_o <= clk_ext_mul;
--dbg_clk_ext_o <= clk_ext_mul;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
......@@ -724,11 +848,12 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_ext_db_i => ext_clk_62mhz,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
-- clk_500_o => clk_500_o,
cpu_wb_i => top_master_out,
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
......@@ -738,16 +863,24 @@ begin
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
dac_helper_data_o => dac_helper_data_o,
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => clk_ext,
dac_main_sync_n_o => dac_main_sync_n,
dac_main_sclk_o => dac_main_sclk,
dac_main_data_o => dac_main_data,
pll_status_i => clk_10mhz,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
ext_board_osc_freq_i=> ext_board_osc_freq_i,
ext_board_detected_i=> ext_board_detected,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
......@@ -766,8 +899,7 @@ begin
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in,
mb_fan1_pwm_o => mb_fan1_pwm_o,
mb_fan2_pwm_o => mb_fan2_pwm_o,
spll_dbg_o => spll_dbg_o);
mb_fan2_pwm_o => mb_fan2_pwm_o);
i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment