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White Rabbit Switch - Gateware
Commit 0f99e5cf authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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constraining tx_out clock produced by GTX_LP

parent d49e5993
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top/scb_18ports/scb_top_synthesis.ucf
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......@@ -1523,3 +1523,40 @@ TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/06/19
NET "gen_phys_bufr[0].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys_bufr[0].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_bufr_0__U_PHY_tx_out_clk_buf = PERIOD "gen_phys_bufr[0].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys_bufr[1].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys_bufr[1].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_bufr_1__U_PHY_tx_out_clk_buf = PERIOD "gen_phys_bufr[1].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys_bufr[2].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys_bufr[2].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_bufr_2__U_PHY_tx_out_clk_buf = PERIOD "gen_phys_bufr[2].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys_bufr[3].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys_bufr[3].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_bufr_3__U_PHY_tx_out_clk_buf = PERIOD "gen_phys_bufr[3].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[4].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[4].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_4__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[4].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[5].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[5].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_5__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[5].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[6].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[6].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_6__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[6].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[7].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[7].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_7__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[7].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[8].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[8].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_8__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[8].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[9].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[9].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_9__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[9].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[10].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[10].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_10__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[10].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[11].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[11].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_11__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[11].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[12].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[12].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_12__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[12].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[13].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[13].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_13__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[13].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[14].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[14].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_14__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[14].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[15].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[15].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_15__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[15].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[16].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[16].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_16__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[16].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[17].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[17].U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_17__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[17].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
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