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White Rabbit Switch - Gateware
Commits
13e5ebbf
Commit
13e5ebbf
authored
Jan 08, 2021
by
Maciej Lipinski
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Plain Diff
bug caught in RX PCS
parent
bc2a208e
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4 changed files
with
17472 additions
and
7124 deletions
+17472
-7124
xswc_output_block_new.vhd
modules/wrsw_swcore/xswc_output_block_new.vhd
+1
-1
main.sv
testbench/scb_top/main.sv
+47
-18
scb_top_sim_svwrap.svh
testbench/scb_top/scb_top_sim_svwrap.svh
+19
-11
wave.do
testbench/scb_top/wave.do
+17405
-7094
No files found.
modules/wrsw_swcore/xswc_output_block_new.vhd
View file @
13e5ebbf
...
...
@@ -355,7 +355,7 @@ begin -- behavoural
cycle_frozen
<=
'0'
;
else
cycle_frozen_cnt
<=
cycle_frozen_cnt
+
1
;
if
(
cycle_frozen_cnt
=
to_unsigned
(
765
,
10
))
then
-- waits max frame size... not good
if
(
cycle_frozen_cnt
=
to_unsigned
(
400
,
10
))
then
-- waits max frame size... not good
cycle_frozen
<=
'1'
;
end
if
;
end
if
;
...
...
testbench/scb_top/main.sv
View file @
13e5ebbf
...
...
@@ -309,28 +309,26 @@ module main;
portUnderTest
=
18'b000000000000000001
;
// tx ,rx ,opt
trans_paths
[
0
]
=
'
{
0
,
1
,
1
};
trans_paths
[
1
]
=
'
{
1
,
0
,
1
};
//
trans_paths[1] = '{1 ,0 , 1 };
repeat_number
=
10000
;
tries_number
=
1
;
g_enable_pck_gaps
=
1
;
g_min_pck_gap
=
214
;
g_max_pck_gap
=
214
;
// to make it 250kHz
g_force_payload_size
=
64
-
18
;
// header = 14 bytes | CRC = 4 bytes
g_max_pck_gap
=
214
;
//=[500-(64+8)]/2 to make it 250kHz
g_force_payload_size
=
64
-
22
;
// header = 14 bytes | QTAG = 4 bytes | CRC = 4 bytes
sim_vlan_tab
[
0
]
=
'
{
'
{
32'hFFFFFFFF
,
8'h0
,
3'h0
,
1'b0
,
1'b0
,
1'b0
},
0
,
1'b1
};
// sim_vlan_tab[ 1] = '{'{32'h00000003, 8'h1 , 3'h0, 1'b0, 1'b0, 1'b0}, 1, 1'b1 };
g_do_vlan_config
=
2
;
// snake EP configuration (tagging proper VLANs on ports
g_do_vlan_config
=
0
;
// no VLANs
rx_forward_on_fmatch_full
=
1
;
mac_br
=
1
;
mac_single
=
1
;
g_is_qvlan
=
0
;
g_do_vlan_config
=
0
;
// snake EP configuration (tagging proper VLANs on ports
g_set_untagging
=
2
;
// untagging
g_failure_scenario
=
14
;
g_is_qvlan
=
1
;
//QTAG with VID=0
g_set_untagging
=
3
;
// untagging all
g_failure_scenario
=
15
;
g_ignore_rx_test_check
=
1
;
// ep_failure_type = 'h00; // failure on the link (break on fiber)
ep_failure_type
=
'h11
;
// reset tx EP (on simulation side)
end
//*/
...
...
@@ -1025,7 +1023,7 @@ module main;
$
display
(
""
)
;
$
display
(
">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
)
;
$
display
(
""
)
;
end
end
// if(g_failure_scenario == x)
if
(
g_failure_scenario
==
13
)
// btrain problem - break link with respect to INPUT BLOCK state machine
begin
automatic
int
cnt_ld
=
0
;
...
...
@@ -1053,8 +1051,8 @@ module main;
wait_cycles
(
10
)
;
end
end
if
(
g_failure_scenario
==
14
)
// btrain problem - break link
with respect to rx frame
end
// if(g_failure_scenario == x)
if
(
g_failure_scenario
==
14
)
// btrain problem - break link
on which tx-ing frame (break "on fiber")
begin
automatic
int
cnt_ld
=
0
;
automatic
int
timeout
=
2000
;
...
...
@@ -1082,7 +1080,38 @@ module main;
wait_cycles
(
200
)
;
end
end
// if(g_failure_scenario == x)
if
(
g_failure_scenario
==
15
)
// btrain problem - break link on which tx-ing frame (break by tx EP_sim reset)
begin
automatic
int
cnt_ld
=
0
;
automatic
int
timeout
=
2000
;
automatic
integer
i
;
for
(
cnt_ld
=
1
;
cnt_ld
<
100
;
cnt_ld
++
)
begin
wait_cycles
(
300
)
;
$
display
(
"test with delay %d cycles
\n
"
,
cnt_ld
)
;
for
(
i
=
0
;
i
<
timeout
;
i
=
i
+
1
)
begin
if
(
DUT
.
U_Top
.
U_Wrapped_SCBCore
.
gen_network_stuff
.
gen_endpoints_and_phys
[
0
]
.
U_Endpoint_X
.
phy_rx_data_i
==
16'hFFFF
)
break
;
@
(
posedge
clk_sys
)
;
end
wait_cycles
(
cnt_ld
)
;
ep_ctrl
[
0
]
=
'b0
;
$
display
(
""
)
;
$
display
(
">>>>>>>>>>>>>>>>>>>>>>>>>>>>> put in reset EP_0<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
)
;
$
display
(
""
)
;
wait_cycles
(
500
)
;
ep_ctrl
[
0
]
=
'b1
;
$
display
(
""
)
;
$
display
(
">>>>>>>>>>>>>>>>>>>>>>>>>>>>> Stop reset and initialize<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
)
;
$
display
(
""
)
;
wait_cycles
(
300
)
;
end
end
// if(g_failure_scenario == x)
end
join_none
;
//
...
...
testbench/scb_top/scb_top_sim_svwrap.svh
View file @
13e5ebbf
...
...
@@ -140,7 +140,7 @@ module scb_top_sim_svwrap
.
clk_ref_i
(
clk_ref_phys
[
i
])
,
.
clk_sys_i
(
clk_sys_i
)
,
.
clk_dmtd_i
(
clk_ref_i
)
,
.
rst_n_i
(
rst_n_i
)
,
.
rst_n_i
(
(
ep_ctrl_i
[
i
]
==
0
&&
ep_failure_type
==
'h11
)
?
1'b0
:
rst_n_i
)
,
.
pps_csync_p1_i
(
1'b0
)
,
.
phy_rst_o
(
phys_out
[
i
]
.
rst
)
,
...
...
@@ -241,8 +241,13 @@ module scb_top_sim_svwrap
from_port
[
i
]
=
new
(
U_ep_snk
.
get_accessor
())
;
to_port
[
i
]
=
new
(
U_ep_src
.
get_accessor
())
;
while
(
1
)
begin
@
(
ep_ctrl_i
[
i
]
==
0
&&
ep_failure_type
==
'h11
)
;
@
(
posedge
clk_sys_i
)
;
@
(
posedge
ep_ctrl_i
[
i
])
repeat
(
50
)
@
(
posedge
clk_sys_i
)
;
ep_drv
.
init
(
0
)
;
end
end
end
// for (i=0; i<g_num_ports; i++)
endgenerate
...
...
@@ -256,20 +261,24 @@ module scb_top_sim_svwrap
///////////////// nasty hack by Maciej /////////////////
// causing sync error in the Switch
// assign td[18 * j + 15 : 18 * j] = ep_ctrl_i[j] ? phys_out[j].tx_data : 'h00BC;
// assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k : 2'b01;
assign
td
[
18
*
j
+
15
:
18
*
j
]
=
ep_ctrl_i
[
j
]
?
phys_out
[
j
]
.
tx_data
:
tx_data_invalid
[
j
]
;
assign
td
[
18
*
j
+
17
:
18
*
j
+
16
]
=
ep_ctrl_i
[
j
]
?
phys_out
[
j
]
.
tx_k
:
tx_k_invalid
[
j
]
;
// assign td[18 * j + 15 : 18 * j] = ep_ctrl_i[j] ? phys_out[j].tx_data : tx_data_invalid[j];
// assign td[18 * j + 17 : 18 * j + 16] = ep_ctrl_i[j] ? phys_out[j].tx_k : tx_k_invalid[j];
// link works when
// ep_ctrl_i = 1 -> this means we want it to work
// ep_failure_type > 10 -> for ep_failure_type greater/equal 10... filure is done differently, so the link should work
assign
td
[
18
*
j
+
15
:
18
*
j
]
=
(
ep_ctrl_i
[
j
]
==
1
||
ep_failure_type
>
'h10
)
?
phys_out
[
j
]
.
tx_data
:
tx_data_invalid
[
j
]
;
assign
td
[
18
*
j
+
17
:
18
*
j
+
16
]
=
(
ep_ctrl_i
[
j
]
==
1
||
ep_failure_type
>
'h10
)
?
phys_out
[
j
]
.
tx_k
:
tx_k_invalid
[
j
]
;
// causing transmission error in the driving simulation
assign
phys_in
[
j
]
.
tx_enc_err
=
~
ep_ctrl_i
[
j
]
;
assign
phys_in
[
j
]
.
tx_enc_err
=
(
ep_ctrl_i
[
j
]
==
1
||
ep_failure_type
>
'h10
)
?
1'b0
:
1'b1
;
//
~ep_ctrl_i[j];
///////////////////////////////////////////////////////
assign
phys_in
[
j
]
.
ref_clk
=
clk_ref_phys
[
j
]
;
assign
phys_in
[
j
]
.
rx_data
=
rd
[
18
*
j
+
15
:
18
*
j
]
;
assign
phys_in
[
j
]
.
rx_k
=
rd
[
18
*
j
+
17
:
18
*
j
+
16
]
;
assign
phys_in
[
j
]
.
rx_clk
=
clk_ref_i
;
// assign phys_in[j].tx_enc_err = 0;
assign
phys_in
[
j
]
.
rx_enc_err
=
0
;
...
...
@@ -284,7 +293,6 @@ module scb_top_sim_svwrap
phys_out
[
j
]
.
tx_data
)
;
end
always
@
(
posedge
clk_sys_i
)
begin
integer
jj
;
if
(
ep_ctrl_i
[
j
]
==
1
)
begin
...
...
testbench/scb_top/wave.do
View file @
13e5ebbf
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