low phase drift calibration only for 12 ports

Possible through the combination of global and regional clocks. Cannot have it for all ports because we don't have enough global/regional clock nets in virtex-6.

low phase drift calibration only for 12 ports
Possible through the combination of global and regional clocks. Cannot have it for all ports because we don't have enough global/regional clock nets in virtex-6.
1b4724a5 · Grzegorz Daniluk · 640c7bb4 · 1b4724a5 · 1b4724a5
Commit 1b4724a5 authored Jul 10, 2019 by Grzegorz Daniluk
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scb_top_synthesis.ucf top/scb_18ports/scb_top_synthesis.ucf +1 -13

scb_top_synthesis.vhd top/scb_18ports/scb_top_synthesis.vhd +51 -2

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--- a/top/scb_18ports/scb_top_synthesis.ucf
+++ b/top/scb_18ports/scb_top_synthesis.ucf
@@ -1523,7 +1523,7 @@ TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_
 #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
 TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
 TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
-#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/06/19
+#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/07/04
 NET "gen_phys_bufr[0].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys_bufr[0].U_PHY/tx_out_clk_buf;
 TIMESPEC TS_gen_phys_bufr_0__U_PHY_tx_out_clk_buf = PERIOD "gen_phys_bufr[0].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
 NET "gen_phys_bufr[1].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys_bufr[1].U_PHY/tx_out_clk_buf;
@@ -1548,15 +1548,3 @@ NET "gen_phys[10].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[10].U_PHY/tx_out_clk_
 TIMESPEC TS_gen_phys_10__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[10].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
 NET "gen_phys[11].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[11].U_PHY/tx_out_clk_buf;
 TIMESPEC TS_gen_phys_11__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[11].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
-NET "gen_phys[12].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[12].U_PHY/tx_out_clk_buf;
-TIMESPEC TS_gen_phys_12__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[12].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
-NET "gen_phys[13].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[13].U_PHY/tx_out_clk_buf;
-TIMESPEC TS_gen_phys_13__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[13].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
-NET "gen_phys[14].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[14].U_PHY/tx_out_clk_buf;
-TIMESPEC TS_gen_phys_14__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[14].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
-NET "gen_phys[15].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[15].U_PHY/tx_out_clk_buf;
-TIMESPEC TS_gen_phys_15__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[15].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
-NET "gen_phys[16].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[16].U_PHY/tx_out_clk_buf;
-TIMESPEC TS_gen_phys_16__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[16].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
-NET "gen_phys[17].U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[17].U_PHY/tx_out_clk_buf;
-TIMESPEC TS_gen_phys_17__U_PHY_tx_out_clk_buf = PERIOD "gen_phys[17].U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
@@ -437,6 +437,53 @@ architecture Behavioral of scb_top_synthesis is
  signal TRIG1   : std_logic_vector(31 downto 0);
  signal TRIG2   : std_logic_vector(31 downto 0);
  signal TRIG3   : std_logic_vector(31 downto 0);
+
+  type t_bufr_phy_assignment_array is array(integer range <>) of boolean;
+
+  constant c_phy_use_bufr_for_rx_clock : t_bufr_phy_assignment_array(0 to 17) :=
+    (
+      false, -- 0
+      false,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false, -- 7
+      false,
+      false,
+      false, -- 10
+      false,
+      false,
+      false,
+      false,
+      false,
+      true,
+      true
+      );
+
+  constant c_phy_use_bufr_for_tx_clock : t_bufr_phy_assignment_array(0 to 17) :=
+    (
+      true, -- 0
+      true,
+      true,
+      true,
+      false,
+      false,
+      false,
+      false, -- 7
+      true,
+      true,
+      true, -- 10
+      true,
+      false,
+      false,
+      false,
+      false,
+      false,
+      false
+      );
+
 begin

  --chipscope_icon_1 : chipscope_icon
@@ -720,7 +767,8 @@ begin
      generic map (
        g_simulation         => f_bool2int(g_simulation),
        g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
-        g_use_bufr           => true,
+        g_use_bufr_for_rx_clock => c_phy_use_bufr_for_rx_clock(i),
+        g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(i),
        g_id                 => i)
      port map (
        clk_gtx_i   => clk_gtx(i),
@@ -756,7 +804,8 @@ begin
      generic map (
        g_simulation         => f_bool2int(g_simulation),
        g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
-        g_use_bufr           => false,
+        g_use_bufr_for_rx_clock => c_phy_use_bufr_for_rx_clock(i),
+        g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(i),
        g_id                 => i)
      port map (
        clk_gtx_i   => clk_gtx(i),