wrsw_nic/nic_tx_fsm: native support of pipelined WB fabric

Instead of old fabtic converted to Pipelined WB using ep_rx_wb_master module from endpoint_private_pkg

wrsw_nic/nic_tx_fsm: native support of pipelined WB fabric
Instead of old fabtic converted to Pipelined WB using ep_rx_wb_master module from endpoint_private_pkg
23e65dd4 · Grzegorz Daniluk · 16e02069 · 23e65dd4 · 23e65dd4 · 23e65dd4
Commit 23e65dd4 authored Oct 23, 2013 by Grzegorz Daniluk
Expand all Hide whitespace changes
Inline Side-by-side

Showing with 99 additions and 122 deletions

nic_tx_fsm.vhd modules/wrsw_nic/nic_tx_fsm.vhd +92 -121

wrsw_nic.vhd modules/wrsw_nic/wrsw_nic.vhd +3 -0

xwrsw_nic.vhd modules/wrsw_nic/xwrsw_nic.vhd +4 -1

No files found.
--- a/modules/wrsw_nic/nic_tx_fsm.vhd
+++ b/modules/wrsw_nic/nic_tx_fsm.vhd
--- a/modules/wrsw_nic/wrsw_nic.vhd
+++ b/modules/wrsw_nic/wrsw_nic.vhd
@@ -11,6 +11,7 @@ entity wrsw_nic is
    (
      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_src_cyc_on_stall    : boolean := false;
      g_port_mask_bits      : integer := 32); --should be num_ports+1
  port (
    clk_sys_i : in std_logic;
@@ -77,6 +78,7 @@ architecture rtl of wrsw_nic is
    generic (
      g_interface_mode      : t_wishbone_interface_mode;
      g_address_granularity : t_wishbone_address_granularity;
+      g_src_cyc_on_stall    : boolean := false;
      g_port_mask_bits      : integer := 32);
    port (
      clk_sys_i           : in  std_logic;
@@ -110,6 +112,7 @@ begin
    generic map (
      g_interface_mode      => g_interface_mode,
      g_address_granularity => g_address_granularity,
+      g_src_cyc_on_stall    => g_src_cyc_on_stall,
      g_port_mask_bits      => g_port_mask_bits)
    port map (
      clk_sys_i           => clk_sys_i,

--- a/modules/wrsw_nic/xwrsw_nic.vhd
+++ b/modules/wrsw_nic/xwrsw_nic.vhd
@@ -17,6 +17,7 @@ entity xwrsw_nic is
    (
      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_src_cyc_on_stall    : boolean := false;
      g_port_mask_bits      : integer := 32); --should be num_ports+1
  port (
    clk_sys_i : in std_logic;
@@ -163,7 +164,8 @@ architecture rtl of xwrsw_nic is

  component nic_tx_fsm
    generic(
-      g_port_mask_bits  : integer := 32);
+      g_port_mask_bits  : integer := 32;
+      g_cyc_on_stall    : boolean := false);
    port (
      clk_sys_i               : in  std_logic;
      rst_n_i                 : in  std_logic;
@@ -495,6 +497,7 @@ begin  -- rtl

  U_TX_FSM : nic_tx_fsm
    generic map(
+      g_cyc_on_stall    => g_src_cyc_on_stall,
      g_port_mask_bits  => g_port_mask_bits)
    port map (
      clk_sys_i => clk_sys_i,