Commit 31787035 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

add bit to control WRS 1-PPS in termination

parent 246f32a1
Subproject commit 94c94685dfc78fe1c2e81ba0467dc7b90b609c84
Subproject commit f73f8239488db55089b83fd5a111cb550f03a5c1
......@@ -98,8 +98,9 @@ entity wrsw_rt_subsystem is
-- TSCs are in sync with the master time counter and the timestamps are correct).
pps_valid_o : out std_logic;
pps_ext_i : in std_logic; -- external PPS input (from the front panel)
pps_ext_o : out std_logic; -- external PPS output (to the front panel)
pps_ext_i : in std_logic; -- external PPS input (from the front panel)
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_ext_o : out std_logic; -- external PPS output (to the front panel)
sel_clk_sys_o : out std_logic; -- system clock selection: 0 = startup
-- clock, 1 = PLL clock
......@@ -372,6 +373,7 @@ begin -- rtl
slave_i => cnx_master_out(c_SLAVE_PPSGEN),
slave_o => cnx_master_in(c_SLAVE_PPSGEN),
pps_in_i => pps_ext_i,
ppsin_term_o => ppsin_term_o,
pps_csync_o => pps_csync,
pps_out_o => pps_ext_o,
pps_valid_o => pps_valid,
......
......@@ -104,8 +104,9 @@ entity scb_top_bare is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -607,6 +608,7 @@ begin
pps_csync_o => pps_csync,
pps_valid_o => pps_valid,
pps_ext_i => pps_i,
ppsin_term_o=> ppsin_term_o,
pps_ext_o => pps_o_predelay,
sel_clk_sys_o => sel_clk_sys,
......
......@@ -153,6 +153,7 @@ package wrsw_components_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
......
......@@ -153,6 +153,7 @@ package wrsw_top_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
......@@ -237,6 +238,7 @@ package wrsw_top_pkg is
pps_csync_o : out std_logic;
pps_valid_o : out std_logic;
pps_ext_i : in std_logic;
ppsin_term_o : out std_logic;
pps_ext_o : out std_logic;
sel_clk_sys_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
......
......@@ -85,6 +85,8 @@ NET "cpu_data_b<0>" LOC="A33";
NET "pps_i" LOC="J25";
NET "ppsin_term_o" LOC="AL34";
NET "ppsin_term_o" IOSTANDARD="LVCMOS25";
NET "pps_o" LOC="U23";
NET "dac_helper_sync_n_o" LOC="AD17";
......
......@@ -100,8 +100,9 @@ entity scb_top_synthesis is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -324,6 +325,7 @@ architecture Behavioral of scb_top_synthesis is
cpu_wb_o : out t_wishbone_slave_out;
cpu_irq_n_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic;
pps_o : out std_logic;
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
......@@ -716,6 +718,7 @@ begin
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
pps_i => pps_i,
ppsin_term_o => ppsin_term_o,
pps_o => pps_o,
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
......
......@@ -94,6 +94,8 @@ NET "cpu_data_b<0>" LOC="A33";
NET "pps_i" LOC="J25";
NET "ppsin_term_o" LOC="AL34";
NET "ppsin_term_o" IOSTANDARD="LVCMOS25";
NET "pps_o" LOC="U23";
NET "dac_helper_sync_n_o" LOC="AD17";
......
......@@ -103,8 +103,9 @@ entity scb_top_synthesis is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -333,6 +334,7 @@ architecture Behavioral of scb_top_synthesis is
cpu_wb_o : out t_wishbone_slave_out;
cpu_irq_n_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic;
pps_o : out std_logic;
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
......@@ -731,6 +733,7 @@ begin
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
pps_i => pps_i,
ppsin_term_o => ppsin_term_o,
pps_o => pps_o,
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
......
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