testbench: adding testbench for NIC b/w throttling

5f6ac509 · Grzegorz Daniluk · e28c46f2 · 5f6ac509 · 5f6ac509 · 5f6ac509
Commit 5f6ac509 authored Aug 12, 2016 by Grzegorz Daniluk
6 changed files
--- a/sim/regs/nic_regs.vh
+++ b/sim/regs/nic_regs.vh
@@ -3,6 +3,8 @@
 `define NIC_CR_RX_EN 32'h00000001
 `define NIC_CR_TX_EN_OFFSET 1
 `define NIC_CR_TX_EN 32'h00000002
+`define NIC_CR_RXTHR_EN_OFFSET 2
+`define NIC_CR_RXTHR_EN 32'h00000004
 `define NIC_CR_SW_RST_OFFSET 31
 `define NIC_CR_SW_RST 32'h80000000
 `define ADDR_NIC_SR                    9'h4
@@ -18,6 +20,8 @@
 `define NIC_SR_CUR_TX_DESC 32'h00000700
 `define NIC_SR_CUR_RX_DESC_OFFSET 16
 `define NIC_SR_CUR_RX_DESC 32'h00070000
+`define ADDR_NIC_RXBW                  9'h8
+`define ADDR_NIC_MAXRXBW               9'hc
 `define ADDR_NIC_EIC_IDR               9'h20
 `define NIC_EIC_IDR_RCOMP_OFFSET 0
 `define NIC_EIC_IDR_RCOMP 32'h00000001

--- a/testbench/nic_bw_throttling/Makefile
+++ b/testbench/nic_bw_throttling/Makefile
--- a/testbench/nic_bw_throttling/Manifest.py
+++ b/testbench/nic_bw_throttling/Manifest.py
+target = "xilinx"
+action = "simulation"
+syn_device = "XC6VLX130T"
+fetchto = "../../ip_cores"
+vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
+
+files = [ "main.sv" ]
+
+modules = { "local" : ["../../top/bare_top",
+                       "../../ip_cores/general-cores",
+                       "../../ip_cores/wr-cores"] }
+					
+
--- a/testbench/nic_bw_throttling/main.sv
+++ b/testbench/nic_bw_throttling/main.sv
--- a/testbench/nic_bw_throttling/run.do
+++ b/testbench/nic_bw_throttling/run.do
+#vlog -sv main.sv +incdir+"." +incdir+../../sim
+#-- make -f Makefile
+#vsim -L unisim -t 10fs work.main -voptargs="+acc"
+
+make -f Makefile
+vsim -L secureip -L unisim -L xilinxcorelib -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+radix -hexadecimal
+run 200ms
+wave zoomfull
+radix -hexadecimal
--- a/testbench/nic_bw_throttling/wave.do
+++ b/testbench/nic_bw_throttling/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/clk_sys
+add wave -noupdate /main/rst_n
+add wave -noupdate -expand -group SNK -expand /main/DUT/U_DUT/snk_i
+add wave -noupdate -expand -group SNK -expand /main/DUT/U_DUT/snk_o
+add wave -noupdate -expand -group SRC -expand /main/DUT/U_DUT/src_o
+add wave -noupdate -expand -group SRC -expand /main/DUT/U_DUT/src_i
+add wave -noupdate /main/DUT/U_DUT/bw_bps_o
+add wave -noupdate /main/DUT/U_DUT/bw_bps_cnt
+add wave -noupdate /main/DUT/U_DUT/bwcur_kbps
+add wave -noupdate /main/DUT/U_DUT/pps_p_i
+add wave -noupdate /main/DUT/U_DUT/pps_valid_i
+add wave -noupdate -height 16 /main/DUT/U_DUT/state_fwd
+add wave -noupdate /main/DUT/U_DUT/wrf_reg
+add wave -noupdate /main/DUT/U_DUT/drop_frame
+add wave -noupdate /main/DUT/U_DUT/rnd_reg
+add wave -noupdate /main/DUT/U_DUT/drop_thr
+add wave -noupdate /main/DUT/U_DUT/bwmin_kbps
+add wave -noupdate /main/DUT/U_DUT/new_limit_i
+add wave -noupdate /main/DUT/U_DUT/bwmax_kbps_i
+add wave -noupdate /main/DUT/U_DUT/thr_step_kbps
+add wave -noupdate /main/DUT/U_DUT/last_thr_kbps
+add wave -noupdate /main/DUT/U_DUT/dbg_frame_dropped
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {4015874000000 fs} 1}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits us
+update
+WaveRestoreZoom {4015779439820 fs} {4016029859720 fs}