Commit 622083de authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

modules/wrsw_nic: remove VLAN untagging, daemons running on ARM must be VLAN aware

parent 3046adc4
......@@ -49,15 +49,12 @@ use work.nic_descriptors_pkg.all;
use work.wr_fabric_pkg.all;
use work.nic_wbgen2_pkg.all;
use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
entity nic_rx_fsm is
generic(
g_untagging : boolean := false
);
port (clk_sys_i : in std_logic;
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
......@@ -148,8 +145,8 @@ architecture behavioral of NIC_RX_FSM is
signal increase_addr : std_logic;
signal fab_vlan_in, fab_in : t_ep_internal_fabric;
signal fab_dreq, fab_vlan_dreq : std_logic;
signal fab_in : t_ep_internal_fabric;
signal fab_dreq : std_logic;
begin
......@@ -161,30 +158,8 @@ begin
rst_n_i => rst_n_i,
snk_i => snk_i,
snk_o => snk_o,
fab_o => fab_vlan_in,
dreq_i => fab_vlan_dreq);
gen_with_vlan: if g_untagging = true generate
U_Vlan : ep_tx_vlan_unit
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
snk_fab_i => fab_vlan_in,
snk_dreq_o => fab_vlan_dreq,
src_fab_o => fab_in,
src_dreq_i => fab_dreq,
inject_mem_addr_i => (others=>'0'),
inject_mem_data_o => open,
uram_offset_wr_i => regs_i.vcr1_offset_wr_o,
uram_offset_i => regs_i.vcr1_offset_o,
uram_data_i => regs_i.vcr1_data_o);
end generate;
gen_no_vlan: if g_untagging = false generate
fab_in <= fab_vlan_in;
fab_vlan_dreq <= fab_dreq;
end generate;
fab_o => fab_in,
dreq_i => fab_dreq);
-- stupid VHDL type conversions
buf_addr_o <= std_logic_vector(rx_buf_addr);
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Thu Feb 13 10:33:54 2014
-- Created : Fri Jul 3 16:18:39 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
......@@ -50,14 +50,6 @@ package nic_wbgen2_pkg is
sr_tx_done_load_o : std_logic;
sr_tx_error_o : std_logic;
sr_tx_error_load_o : std_logic;
vcr0_qmode_o : std_logic_vector(1 downto 0);
vcr0_fix_prio_o : std_logic;
vcr0_prio_val_o : std_logic_vector(2 downto 0);
vcr0_pvid_o : std_logic_vector(11 downto 0);
vcr1_offset_o : std_logic_vector(9 downto 0);
vcr1_offset_wr_o : std_logic;
vcr1_data_o : std_logic_vector(17 downto 0);
vcr1_data_wr_o : std_logic;
end record;
constant c_nic_out_registers_init_value: t_nic_out_registers := (
......@@ -69,15 +61,7 @@ package nic_wbgen2_pkg is
sr_tx_done_o => '0',
sr_tx_done_load_o => '0',
sr_tx_error_o => '0',
sr_tx_error_load_o => '0',
vcr0_qmode_o => (others => '0'),
vcr0_fix_prio_o => '0',
vcr0_prio_val_o => (others => '0'),
vcr0_pvid_o => (others => '0'),
vcr1_offset_o => (others => '0'),
vcr1_offset_wr_o => '0',
vcr1_data_o => (others => '0'),
vcr1_data_wr_o => '0'
sr_tx_error_load_o => '0'
);
function "or" (left, right: t_nic_in_registers) return t_nic_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Thu Feb 13 10:33:54 2014
-- Created : Fri Jul 3 16:18:39 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
......@@ -71,10 +71,6 @@ signal nic_cr_rx_en_int : std_logic ;
signal nic_cr_tx_en_int : std_logic ;
signal nic_cr_sw_rst_dly0 : std_logic ;
signal nic_cr_sw_rst_int : std_logic ;
signal nic_vcr0_qmode_int : std_logic_vector(1 downto 0);
signal nic_vcr0_fix_prio_int : std_logic ;
signal nic_vcr0_prio_val_int : std_logic_vector(2 downto 0);
signal nic_vcr0_pvid_int : std_logic_vector(11 downto 0);
signal nic_dtx_rddata_int : std_logic_vector(31 downto 0);
signal nic_dtx_rd_int : std_logic ;
signal nic_dtx_wr_int : std_logic ;
......@@ -124,12 +120,6 @@ begin
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
nic_vcr0_qmode_int <= "00";
nic_vcr0_fix_prio_int <= '0';
nic_vcr0_prio_val_int <= "000";
nic_vcr0_pvid_int <= "000000000000";
regs_o.vcr1_offset_wr_o <= '0';
regs_o.vcr1_data_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -143,8 +133,6 @@ begin
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
regs_o.vcr1_offset_wr_o <= '0';
regs_o.vcr1_data_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -153,8 +141,6 @@ begin
regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0';
regs_o.vcr1_offset_wr_o <= '0';
regs_o.vcr1_data_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -237,72 +223,6 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
nic_vcr0_qmode_int <= wrdata_reg(1 downto 0);
nic_vcr0_fix_prio_int <= wrdata_reg(2);
nic_vcr0_prio_val_int <= wrdata_reg(6 downto 4);
nic_vcr0_pvid_int <= wrdata_reg(27 downto 16);
end if;
rddata_reg(1 downto 0) <= nic_vcr0_qmode_int;
rddata_reg(2) <= nic_vcr0_fix_prio_int;
rddata_reg(6 downto 4) <= nic_vcr0_prio_val_int;
rddata_reg(27 downto 16) <= nic_vcr0_pvid_int;
rddata_reg(3) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
regs_o.vcr1_offset_wr_o <= '1';
regs_o.vcr1_data_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
......@@ -540,20 +460,6 @@ begin
regs_o.sr_tx_error_o <= wrdata_reg(3);
-- Current TX descriptor
-- Current RX descriptor
-- RX 802.1q port mode
regs_o.vcr0_qmode_o <= nic_vcr0_qmode_int;
-- Force 802.1q priority
regs_o.vcr0_fix_prio_o <= nic_vcr0_fix_prio_int;
-- Port-assigned 802.1q priority
regs_o.vcr0_prio_val_o <= nic_vcr0_prio_val_int;
-- Port-assigned VID
regs_o.vcr0_pvid_o <= nic_vcr0_pvid_int;
-- VLAN Untagged Set/Injection Buffer offset
-- pass-through field: VLAN Untagged Set/Injection Buffer offset in register: VLAN Control Register 1
regs_o.vcr1_offset_o <= wrdata_reg(9 downto 0);
-- VLAN Untagged Set/Injection Buffer value
-- pass-through field: VLAN Untagged Set/Injection Buffer value in register: VLAN Control Register 1
regs_o.vcr1_data_o <= wrdata_reg(27 downto 10);
-- extra code for reg/fifo/mem: TX descriptors mem
-- RAM block instantiation for memory: TX descriptors mem
nic_dtx_raminst : wbgen2_dpssram
......
......@@ -177,92 +177,6 @@ top = peripheral {
trigger = LEVEL_1;
};
reg {
name = "VLAN Control Register 0";
prefix = "VCR0";
field {
name = "RX 802.1q port mode";
description = "00: ACCESS port - tags untagged received packets with VID from RX_VID field. Drops all tagged packets not belonging to RX_VID VLAN\
01: TRUNK port - passes only tagged VLAN packets. Drops all untagged packets.\
10: VLAN disabled on port - passes the packets as is.\
11: unqualified port - passes all traffic regardless of VLAN configuration";
type = SLV;
size = 2;
align = 2;
prefix = "Qmode";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Force 802.1q priority";
description = "1: ignores the 802.1x priority (if 802.1q header is present) and sets it to fixed value\
0: uses priority from 802.1q header";
prefix = "FIX_PRIO";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Port-assigned 802.1q priority";
description = "Packet priority value for retagging. When FIX_PRIO is 1, the endpoint uses this value as the packet priority. Otherwise, priority value is taken from 802.1q header if it's present. If there is no 802.1q header, the priority is assumed to be PRIO_VAL.";
prefix = "PRIO_VAL";
type = SLV;
size = 3;
align = 4;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Port-assigned VID";
description = "VLAN id value for tagging incoming packets if the port is in ACCESS mode. For TRUNK/unqualified the value of VID is ignored.";
prefix = "PVID";
type = SLV;
align = 16;
size = 12;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "VLAN Control Register 1";
description = "Provides access to the egress VLAN untagged set and packet injection template buffer. In order to write to the buffer, set the DATA and OFFSET fields to the desired buffer location/value.\
The buffer layout goes as follows:\
- the lower part (offsets 0 to 255) contains the VLAN untagged set bitmap. Each bit represents a single VLAN, where VID = OFFSET * 16 + bit position. For bits set to 1, VLAN headers containing corrensponding VID value are untagged.\
- the higher part (offsets 512 to 1024) contains the packet injection template buffer. The buffer can store up to 8 packet templates of up to 128 bytes of size. Bits [15:0] of each entry contain the data value to be sent, bit 16 indicates the last word to transfer and bit 17 indicates that the current word shall be replaced by the user value (inject_user_value_i).";
prefix = "VCR1";
field {
name = "VLAN Untagged Set/Injection Buffer offset";
description = "Buffer address to be written";
prefix = "OFFSET";
type = PASS_THROUGH;
size = 10;
};
field {
name = "VLAN Untagged Set/Injection Buffer value";
description = "Buffer value to be written";
prefix = "DATA";
type = PASS_THROUGH;
size = 18;
};
};
ram {
name = "TX descriptors mem";
prefix = "dtx";
......
......@@ -49,8 +49,7 @@ entity wrsw_nic is
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32; --should be num_ports+1
g_rx_untagging : boolean := false);
g_port_mask_bits : integer := 32); --should be num_ports+1
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -117,8 +116,7 @@ architecture rtl of wrsw_nic is
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32;
g_rx_untagging : boolean := false);
g_port_mask_bits : integer := 32);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -152,8 +150,7 @@ begin
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_src_cyc_on_stall => g_src_cyc_on_stall,
g_port_mask_bits => g_port_mask_bits,
g_rx_untagging => g_rx_untagging)
g_port_mask_bits => g_port_mask_bits)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......
......@@ -62,8 +62,7 @@ entity xwrsw_nic is
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32; --should be num_ports+1
g_rx_untagging : boolean := false);
g_port_mask_bits : integer := 32); --should be num_ports+1
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -130,8 +129,6 @@ architecture rtl of xwrsw_nic is
end component;
component nic_rx_fsm
generic(
g_untagging : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -479,8 +476,6 @@ begin -- rtl
U_RX_FSM : nic_rx_fsm
generic map(
g_untagging => g_rx_untagging)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
......
......@@ -18,20 +18,6 @@
`define NIC_SR_CUR_TX_DESC 32'h00000700
`define NIC_SR_CUR_RX_DESC_OFFSET 16
`define NIC_SR_CUR_RX_DESC 32'h00070000
`define ADDR_NIC_VCR0 9'h8
`define NIC_VCR0_QMODE_OFFSET 0
`define NIC_VCR0_QMODE 32'h00000003
`define NIC_VCR0_FIX_PRIO_OFFSET 2
`define NIC_VCR0_FIX_PRIO 32'h00000004
`define NIC_VCR0_PRIO_VAL_OFFSET 4
`define NIC_VCR0_PRIO_VAL 32'h00000070
`define NIC_VCR0_PVID_OFFSET 16
`define NIC_VCR0_PVID 32'h0fff0000
`define ADDR_NIC_VCR1 9'hc
`define NIC_VCR1_OFFSET_OFFSET 0
`define NIC_VCR1_OFFSET 32'h000003ff
`define NIC_VCR1_DATA_OFFSET 10
`define NIC_VCR1_DATA 32'h0ffffc00
`define ADDR_NIC_EIC_IDR 9'h20
`define NIC_EIC_IDR_RCOMP_OFFSET 0
`define NIC_EIC_IDR_RCOMP 32'h00000001
......
......@@ -413,22 +413,6 @@ class CSimDrv_NIC;
endtask // automatic
task vlan_egress_untag(int vid, int untag);
uint64_t wval=0;
if(untag>0)
untag_tab[(vid>>4)] = untag_tab[(vid>>4)] | (1<<('h000F & vid));
else
untag_tab[(vid>>4)] = untag_tab[(vid>>4)] & ! (1<<('h000F & vid));
wval = (untag_tab[(vid>>4)] << 10) | ('h000003FF & (vid>>4));
$display("[vlan_egress_untag], write offset: %d, data: 0x%x (val=0x%x)",
(vid>>4),untag_tab[(vid>>4)], wval);
writel(`ADDR_NIC_VCR1, wval);
endtask
// vlan_egress_untag
task automatic nic_irq_handler();
......
......@@ -590,8 +590,7 @@ begin
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_port_mask_bits => c_NUM_PORTS+1,
g_rx_untagging => false)
g_port_mask_bits => c_NUM_PORTS+1)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
......
......@@ -179,8 +179,7 @@ package wrsw_components_pkg is
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32; --should be num_ports+1
g_rx_untagging : boolean := false);
g_port_mask_bits : integer := 32); --should be num_ports+1
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......
......@@ -179,8 +179,7 @@ package wrsw_top_pkg is
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32; --should be num_ports+1
g_rx_untagging : boolean := false);
g_port_mask_bits : integer := 32); --should be num_ports+1
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......
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