top: manual control of TX/RX clock buffers for PHYs through generics

640c7bb4 · Tomasz Wlostowski · Grzegorz Daniluk · 0f99e5cf · 640c7bb4
Commit 640c7bb4 authored Jul 03, 2019 by Tomasz Wlostowski Committed by Grzegorz Daniluk Aug 30, 2019
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Showing with 22 additions and 4 deletions

scb_top_synthesis.vhd top/scb_8ports/scb_top_synthesis.vhd +22 -4

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--- a/top/scb_8ports/scb_top_synthesis.vhd
+++ b/top/scb_8ports/scb_top_synthesis.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
 -- Company    : CERN BE-CO-HT
 -- Created    : 2012-03-07
-- Last update: 2018-08-09
+-- Last update: 2019-07-03
 -- Platform   : FPGA-generic
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -440,6 +440,21 @@ architecture Behavioral of scb_top_synthesis is

  signal phy_rx_clk_vec: std_logic_vector(7 downto 0);

+  type t_bufr_phy_assignment_array is array(integer range <>) of boolean;
+
+  constant c_phy_use_bufr_for_tx_clock : t_bufr_phy_assignment_array(0 to 7) :=
+    (
+      true,
+      true,
+      true,
+      true,
+      false,
+      false,
+      true,
+      true
+      );
+
+
 begin

  U_Clk_Buf_GTX0_3 : IBUFDS_GTXE1
@@ -691,7 +706,8 @@ begin
      generic map (
        g_simulation         => f_bool2int(g_simulation),
        g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
-        g_use_bufr           => false,
+        g_use_bufr_for_rx_clock           => false,
+        g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(i),
        g_id => i)
      port map (
        clk_gtx_i => clk_gtx(i),
@@ -728,7 +744,8 @@ begin
      generic map (
        g_simulation         => f_bool2int(g_simulation),
        g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
-        g_use_bufr           => false,
+        g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(i),
+        g_use_bufr_for_rx_clock           => false,
        g_id => i)
      port map (
        clk_gtx_i => clk_gtx(i),
@@ -762,7 +779,8 @@ begin
      generic map (
        g_simulation         => f_bool2int(g_simulation),
        g_use_slave_tx_clock => 0,
-        g_use_bufr           => false,
+        g_use_bufr_for_rx_clock           => false,
+        g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(7),
        g_id => c_NUM_PHYS-1)
      port map (
        clk_gtx_i => clk_gtx0_3,