Skip to content

W
White Rabbit Switch - Gateware
Commit 6b0def70 authored by li hongming's avatar li hongming
Browse files
Options

Change the DDMTD source from ext VCXO to cascaded PLL.

parent b5af21d7
Hide whitespace changes
Inline Side-by-side
Showing with 152 additions and 24 deletions
top/scb_18ports/scb_top_synthesis.ucf
View file @ 6b0def70
......@@ -7,8 +7,8 @@ NET "fpga_clk_25mhz_n_i" LOC=K23;
NET "fpga_clk_ref_p_i" LOC=J9;
NET "fpga_clk_ref_n_i" LOC=H9;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
# NET "fpga_clk_dmtd_p_i" LOC=L23;
# NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "clk_ext_i" LOC=K13;
NET "clk_aux_p_o" LOC=B20;
......@@ -299,7 +299,7 @@ NET "clk_25mhz" TNM_NET = fpga_clk_25mhz_i;
TIMESPEC TS_fpga_clk_25mhz_i = PERIOD "fpga_clk_25mhz_i" 40 ns HIGH 50%;
NET "clk_dmtd" TNM_NET = fpga_clk_dmtd_i;
TIMESPEC TS_fpga_clk_dmtd_i = PERIOD "fpga_clk_dmtd_i" 16 ns HIGH 50%;
# TIMESPEC TS_fpga_clk_dmtd_i = PERIOD "fpga_clk_dmtd_i" 16 ns HIGH 50%;
NET "clk_ref" TNM_NET = fpga_clk_ref_i;
TIMESPEC TS_fpga_clk_ref_i = PERIOD "fpga_clk_ref_i" 16 ns HIGH 50%;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ 6b0def70
......@@ -68,8 +68,8 @@ entity scb_top_synthesis is
fpga_clk_ref_n_i : in std_logic;
-- 125+ MHz DMTD offset clock (from the CDCM62001 PLL output DMTDCLK_MAIN)
fpga_clk_dmtd_p_i : in std_logic;
fpga_clk_dmtd_n_i : in std_logic;
-- fpga_clk_dmtd_p_i : in std_logic;
-- fpga_clk_dmtd_n_i : in std_logic;
-- External 10MHz input
clk_ext_i : in std_logic;
......@@ -317,6 +317,9 @@ architecture Behavioral of scb_top_synthesis is
signal clk_ext_mul_locked : std_logic;
signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic;
signal pllout_clk_fb_chain1, pllout_clk_fb_chain2 : std_logic;
signal pllout_clk_1, pllout_clk_2 : std_logic;
signal pllout_clk_chain1 : std_logic;
component scb_top_bare
generic (
......@@ -506,14 +509,76 @@ begin
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_CLK_DMTD : IBUFGDS
cmp_chain1_clk_pll : pll_base
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
bandwidth => "optimized",
clk_feedback => "clkfbout",
compensation => "internal",
divclk_divide => 5,
clkfbout_mult => 64,
clkfbout_phase => 0.000,
clkout0_divide => 9, -- 62.5*64/5/9
clkout0_phase => 0.000,
clkout0_duty_cycle => 0.500,
clkin_period => 16.0,
ref_jitter => 0.016)
port map (
clkfbout => pllout_clk_fb_chain1,
clkout0 => pllout_clk_1,
clkout1 => open,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
locked => open,
rst => '0',
clkfbin => pllout_clk_fb_chain1,
clkin => clk_ref);
cmp_clk_dmtd1_buf : bufg
port map (
o => pllout_clk_chain1,
i => pllout_clk_1);
cmp_chain2_clk_pll : pll_base
generic map (
bandwidth => "optimized",
clk_feedback => "clkfbout",
compensation => "internal",
divclk_divide => 7,
clkfbout_mult => 64,
clkfbout_phase => 0.000,
clkout0_divide => 13, -- 62.5*64/5/9/7/13
clkout0_phase => 0.000,
clkout0_duty_cycle => 0.500,
clkin_period => 11.25,
ref_jitter => 0.016)
port map (
clkfbout => pllout_clk_fb_chain2,
clkout0 => pllout_clk_2,
clkout1 => open,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
locked => open,
rst => '0',
clkfbin => pllout_clk_fb_chain2,
clkin => pllout_clk_chain1);
U_Buf_CLK_DMTD: BUFG
port map (
O => clk_dmtd,
I => fpga_clk_dmtd_p_i,
IB => fpga_clk_dmtd_n_i);
I => pllout_clk_2,
O => clk_dmtd);
-- U_Buf_CLK_DMTD : IBUFGDS
-- generic map (
-- DIFF_TERM => true,
-- IOSTANDARD => "LVDS_25")
-- port map (
-- O => clk_dmtd,
-- I => fpga_clk_dmtd_p_i,
-- IB => fpga_clk_dmtd_n_i);
U_swcore_pll: swcore_pll port map ( clk_sys_i => clk_ref, clk_aux_o => clk_aux);
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ 6b0def70
......@@ -7,8 +7,8 @@ NET "fpga_clk_25mhz_n_i" LOC=K23;
NET "fpga_clk_ref_p_i" LOC=J9;
NET "fpga_clk_ref_n_i" LOC=H9;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
# NET "fpga_clk_dmtd_p_i" LOC=L23;
# NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "clk_ext_i" LOC=K13;
NET "clk_aux_p_o" LOC=B20;
......@@ -296,7 +296,7 @@ NET "clk_25mhz" TNM_NET = fpga_clk_25mhz_i;
TIMESPEC TS_fpga_clk_25mhz_i = PERIOD "fpga_clk_25mhz_i" 40 ns HIGH 50%;
NET "clk_dmtd" TNM_NET = fpga_clk_dmtd_i;
TIMESPEC TS_fpga_clk_dmtd_i = PERIOD "fpga_clk_dmtd_i" 16 ns HIGH 50%;
# TIMESPEC TS_fpga_clk_dmtd_i = PERIOD "fpga_clk_dmtd_i" 16 ns HIGH 50%;
NET "clk_ref" TNM_NET = fpga_clk_ref_i;
TIMESPEC TS_fpga_clk_ref_i = PERIOD "fpga_clk_ref_i" 16 ns HIGH 50%;
......
top/scb_8ports/scb_top_synthesis.vhd
View file @ 6b0def70
......@@ -68,8 +68,8 @@ entity scb_top_synthesis is
fpga_clk_ref_n_i : in std_logic;
-- 125+ MHz DMTD offset clock (from the CDCM62001 PLL output DMTDCLK_MAIN)
fpga_clk_dmtd_p_i : in std_logic;
fpga_clk_dmtd_n_i : in std_logic;
-- fpga_clk_dmtd_p_i : in std_logic;
-- fpga_clk_dmtd_n_i : in std_logic;
-- External 10MHz input
clk_ext_i : in std_logic;
......@@ -322,6 +322,9 @@ architecture Behavioral of scb_top_synthesis is
signal clk_ext_mul_locked : std_logic;
signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic;
signal pllout_clk_fb_chain1, pllout_clk_fb_chain2 : std_logic;
signal pllout_clk_1, pllout_clk_2 : std_logic;
signal pllout_clk_chain1 : std_logic;
component scb_top_bare
generic (
......@@ -512,16 +515,76 @@ begin
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_CLK_DMTD : IBUFGDS
cmp_chain1_clk_pll : pll_base
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
bandwidth => "optimized",
clk_feedback => "clkfbout",
compensation => "internal",
divclk_divide => 5,
clkfbout_mult => 64,
clkfbout_phase => 0.000,
clkout0_divide => 9, -- 62.5*64/5/9
clkout0_phase => 0.000,
clkout0_duty_cycle => 0.500,
clkin_period => 16.0,
ref_jitter => 0.016)
port map (
clkfbout => pllout_clk_fb_chain1,
clkout0 => pllout_clk_1,
clkout1 => open,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
locked => open,
rst => '0',
clkfbin => pllout_clk_fb_chain1,
clkin => clk_ref);
cmp_clk_dmtd1_buf : bufg
port map (
o => pllout_clk_chain1,
i => pllout_clk_1);
cmp_chain2_clk_pll : pll_base
generic map (
bandwidth => "optimized",
clk_feedback => "clkfbout",
compensation => "internal",
divclk_divide => 7,
clkfbout_mult => 64,
clkfbout_phase => 0.000,
clkout0_divide => 13, -- 62.5*64/5/9/7/13
clkout0_phase => 0.000,
clkout0_duty_cycle => 0.500,
clkin_period => 11.25,
ref_jitter => 0.016)
port map (
clkfbout => pllout_clk_fb_chain2,
clkout0 => pllout_clk_2,
clkout1 => open,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
locked => open,
rst => '0',
clkfbin => pllout_clk_fb_chain2,
clkin => pllout_clk_chain1);
U_Buf_CLK_DMTD: BUFG
port map (
O => clk_dmtd,
I => fpga_clk_dmtd_p_i,
IB => fpga_clk_dmtd_n_i);
I => pllout_clk_2,
O => clk_dmtd);
-- U_Buf_CLK_DMTD : IBUFGDS
-- generic map (
-- DIFF_TERM => true,
-- IOSTANDARD => "LVDS_25")
-- port map (
-- O => clk_dmtd,
-- I => fpga_clk_dmtd_p_i,
-- IB => fpga_clk_dmtd_n_i);
U_swcore_pll: swcore_pll port map ( clk_sys_i => clk_ref, clk_aux_o => clk_aux);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment