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White Rabbit Switch - Gateware
Commit 72a35829 authored by li hongming's avatar li hongming
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Merge remote-tracking branch 'origin/hm-wrsfl-lowjitter' into hm-wrslj-pts 

 PTS for WRS-LJ which is normal WRS with external AD9516 for 10MHz input.
parents 7c945d5a c9e54723
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.gitignore
View file @ 72a35829
......@@ -13,3 +13,4 @@ fifo_generator_v6_1
build_wb.sh
doc/
synthesis_descriptor.vhd
*.en
Manifest.py
View file @ 72a35829
......@@ -7,8 +7,8 @@ modules = { "local" : [
"modules/wrsw_tru",
"modules/wrsw_tatsu",
"modules/wrsw_pstats",
"modules/wrsw_hwiu",
"modules/wrsw_watchdog",
"modules/wrsw_hwiu",
"modules/wrsw_watchdog",
"platform/virtex6/chipscope",
"platform/xilinx"],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git" ]
......
wr-cores @ 78c35cb0
Subproject commit 6f6b4404cf41821460c5b355ac0467cbae9afa30
Subproject commit 78c35cb0f0c396df415f1d35595c5593bbb717cc
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 72a35829
......@@ -58,7 +58,7 @@ entity wrsw_rt_subsystem is
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
-- clk_500_o : out std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
......@@ -94,8 +94,9 @@ entity wrsw_rt_subsystem is
-- TSCs are in sync with the master time counter and the timestamps are correct).
pps_valid_o : out std_logic;
pps_ext_i : in std_logic; -- external PPS input (from the front panel)
pps_ext_o : out std_logic; -- external PPS output (to the front panel)
pps_ext_i : in std_logic; -- external PPS input (from the front panel)
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_ext_o : out std_logic; -- external PPS output (to the front panel)
sel_clk_sys_o : out std_logic; -- system clock selection: 0 = startup
-- clock, 1 = PLL clock
......@@ -120,8 +121,16 @@ entity wrsw_rt_subsystem is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- WRS Low jitter AD9516
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic
-- Debug
spll_dbg_o : out std_logic_vector(5 downto 0)
-- spll_dbg_o : out std_logic_vector(5 downto 0)
);
end wrsw_rt_subsystem;
......@@ -161,7 +170,7 @@ architecture rtl of wrsw_rt_subsystem is
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
debug_o : out std_logic_vector(5 downto 0);
-- debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic);
end component;
......@@ -180,6 +189,7 @@ architecture rtl of wrsw_rt_subsystem is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
pps_valid_o : out std_logic;
......@@ -199,7 +209,7 @@ architecture rtl of wrsw_rt_subsystem is
pps_valid_i : in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
-- clk_500_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0);
ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic;
......@@ -216,8 +226,8 @@ architecture rtl of wrsw_rt_subsystem is
-- 0x10300 - 0x10400: GPIO
-- 0x10400 - 0x10500: Timer
constant c_NUM_GPIO_PINS : integer := 4;
constant c_NUM_WB_SLAVES : integer := 8;
constant c_NUM_GPIO_PINS : integer := 5;
constant c_NUM_WB_SLAVES : integer := 9;
constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1;
......@@ -230,7 +240,7 @@ architecture rtl of wrsw_rt_subsystem is
constant c_SLAVE_TIMER : integer := 5;
constant c_SLAVE_PPSGEN : integer := 6;
constant c_SLAVE_GEN10 : integer := 7;
constant c_SLAVE_SPI_EXT : integer := 8;
signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(1 downto 0);
......@@ -354,9 +364,9 @@ begin -- rtl
clk_fb_i(0) => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
pps_csync_p1_i => pps_csync,
pps_csync_p1_i => pps_csync,
pps_ext_a_i => pps_ext_i,
dac_dmtd_data_o => dac_dmtd_data,
dac_dmtd_load_o => dac_dmtd_load,
......@@ -366,8 +376,9 @@ begin -- rtl
out_enable_i => "0",
out_locked_o => open,
slave_i => cnx_master_out(c_SLAVE_SOFTPLL),
slave_o => cnx_master_in(c_SLAVE_SOFTPLL),
debug_o => spll_dbg_o);
slave_o => cnx_master_in(c_SLAVE_SOFTPLL)
-- debug_o => spll_dbg_o
);
U_PPS_Gen : xwr_pps_gen
generic map (
......@@ -384,6 +395,7 @@ begin -- rtl
slave_i => cnx_master_out(c_SLAVE_PPSGEN),
slave_o => cnx_master_in(c_SLAVE_PPSGEN),
pps_in_i => pps_ext_i,
ppsin_term_o => ppsin_term_o,
pps_csync_o => pps_csync,
pps_out_o => pps_ext_o,
pps_valid_o => pps_valid,
......@@ -414,6 +426,25 @@ begin -- rtl
pad_sclk_o => pll_sck_o,
pad_mosi_o => pll_mosi_o,
pad_miso_i => pll_miso_i);
U_SPI_Master_external_board : xwb_spi
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_divider_len => 8,
g_max_char_len => 24,
g_num_slaves => 1)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cnx_master_out(c_SLAVE_SPI_EXT),
slave_o => cnx_master_in(c_SLAVE_SPI_EXT),
desc_o => open,
pad_cs_o(0) => ext_pll_cs_n_o,
pad_sclk_o => ext_pll_sck_o,
pad_mosi_o => ext_pll_mosi_o,
pad_miso_i => ext_pll_miso_i);
U_GPIO : xwb_gpio_port
generic map (
......@@ -455,7 +486,7 @@ begin -- rtl
pps_valid_i => pps_valid,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
-- clk_500_o => clk_500_o,
ppsdel_tap_i => ppsdel_tap_i,
ppsdel_tap_o => ppsdel_tap_o,
ppsdel_tap_wr_o => ppsdel_tap_wr_o,
......@@ -466,6 +497,8 @@ begin -- rtl
pll_reset_n_o <= gpio_out(1);
cpu_reset_n <= not gpio_out(2) and rst_n_i;
rst_n_o <= gpio_out(3);
ext_pll_reset_n_o <= gpio_out(4);
ext_pll_sync_n_o <= '1';
U_Main_DAC : gc_serial_dac
generic map (
......
syn/pts_scb/pts_scb.xise
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syn/scb_18ports/test_scb.xise
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syn/scb_8ports/test_scb.xise
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top/bare_top/scb_top_bare.vhd
View file @ 72a35829
......@@ -81,9 +81,12 @@ entity scb_top_bare is
-- Programmable aux clock (from the AD9516 PLL output QDRII_200CLK). Used
-- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
-- External 10MHz clock input
clk_ext_i : in std_logic;
-- External 62.5MHz clock input (from 10MHz)
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
clk_aux_n_o : out std_logic; -- default it's 10MHz, but is configurable
......@@ -104,8 +107,9 @@ entity scb_top_bare is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -120,8 +124,7 @@ entity scb_top_bare is
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -129,6 +132,14 @@ entity scb_top_bare is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- external AD9516 to mul 10MHz to 62.5MHz
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
......@@ -515,8 +526,8 @@ begin
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
......@@ -537,6 +548,7 @@ begin
pps_csync_o => pps_csync,
pps_valid_o => pps_valid,
pps_ext_i => pps_i,
ppsin_term_o=> ppsin_term_o,
pps_ext_o => pps_o_predelay,
sel_clk_sys_o => sel_clk_sys,
......@@ -556,6 +568,13 @@ begin
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
spll_dbg_o => spll_dbg_o);
U_DELAY_PPS: IODELAYE1
......
top/bare_top/wrs_sdb_pkg.vhd
View file @ 72a35829
......@@ -237,7 +237,7 @@ package wrs_sdb_pkg is
name => "WRSW SWCORE ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(7 downto 0) :=
constant c_rtbar_layout : t_sdb_record_array(8 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
......@@ -245,7 +245,9 @@ package wrs_sdb_pkg is
4 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00010300"), --GPIO
5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"));--GEN 10MHz
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700")); --SPI ext
constant c_rtbar_sdb_address : t_wishbone_address := x"00010800";
constant c_rtbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address);
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 72a35829
......@@ -153,6 +153,7 @@ package wrsw_components_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
......@@ -242,7 +243,13 @@ package wrsw_components_pkg is
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic);
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic);
end component;
component chipscope_icon
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 72a35829
......@@ -153,6 +153,7 @@ package wrsw_top_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
......@@ -231,6 +232,7 @@ package wrsw_top_pkg is
pps_csync_o : out std_logic;
pps_valid_o : out std_logic;
pps_ext_i : in std_logic;
ppsin_term_o : out std_logic;
pps_ext_o : out std_logic;
sel_clk_sys_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
......@@ -246,6 +248,12 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
end component;
......@@ -284,8 +292,9 @@ package wrsw_top_pkg is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......@@ -298,13 +307,19 @@ package wrsw_top_pkg is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
......
top/pts_scb/pts_scb_top.ucf
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top/pts_scb/pts_scb_top.vhd
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top/pts_scb/pts_scb_top_bare.vhd
View file @ 72a35829
......@@ -82,14 +82,17 @@ entity pts_scb_top_bare is
-- Programmable aux clock (from the AD9516 PLL output QDRII_200CLK). Used
-- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
-- External 10MHz clock input
clk_ext_i : in std_logic;
-- External 62.5MHz clock input (from 10MHz)
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
clk_aux_n_o : out std_logic; -- default it's 10MHz, but is configurable
clk_500_o : out std_logic;
-- clk_500_o : out std_logic;
-- Muxed system clock
clk_sys_o : out std_logic;
......@@ -105,8 +108,9 @@ entity pts_scb_top_bare is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -121,8 +125,7 @@ entity pts_scb_top_bare is
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -130,6 +133,14 @@ entity pts_scb_top_bare is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- external AD9516 to mul 10MHz to 62.5MHz
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
......@@ -179,10 +190,10 @@ entity pts_scb_top_bare is
-- Mini-backplane PWM fans
---------------------------------------------------------------------------
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
-- mb_fan1_pwm_o : out std_logic;
-- mb_fan2_pwm_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0);
-- spll_dbg_o : out std_logic_vector(5 downto 0);
---------------------------------------------------------------------------
-- PTS
......@@ -651,12 +662,12 @@ begin
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
-- clk_500_o => clk_500_o,
rst_n_i => rst_n_sys,
rst_n_o => rst_n_periph,
wb_i => cnx_master_out(c_SLAVE_RT_SUBSYSTEM),
......@@ -673,6 +684,7 @@ begin
pps_csync_o => pps_csync,
pps_valid_o => pps_valid,
pps_ext_i => pps_i,
ppsin_term_o=> ppsin_term_o,
pps_ext_o => pps_out,
sel_clk_sys_o => sel_clk_sys,
......@@ -692,7 +704,15 @@ begin
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => open, -- pll_sync_n_o, -- not used within wrsw_rt_subsystem
pll_reset_n_o => pll_reset_n_o,
spll_dbg_o => spll_dbg_o);
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o
-- spll_dbg_o => spll_dbg_o
);
U_DELAY_PPS: IODELAYE1
generic map (
......@@ -789,12 +809,12 @@ begin
g_tx_force_gap_length => 0,
g_tx_runt_padding => false,
g_pcs_16bit => true,
g_rx_buffer_size => 1024,
g_rx_buffer_size => 1000,
g_with_rx_buffer => true,
g_with_flow_control => false,-- useless: flow control commented out
g_with_timestamper => true,
g_with_dpi_classifier => true,
g_with_vlans => true,
g_with_vlans => false,
g_with_rtu => true,
g_with_leds => true,
g_with_dmtd => false,
......@@ -940,12 +960,12 @@ begin
g_address_granularity => BYTE,
g_prio_num => 8,
g_output_queue_num => 8,
g_max_pck_size => 10 * 1024,
g_max_pck_size => 9 * 1024,
g_max_oob_size => 3,
g_num_ports => g_num_ports+1,
g_pck_pg_free_fifo_size => 512,
g_pck_pg_free_fifo_size => 256,
g_input_block_cannot_accept_data => "drop_pck",
g_output_block_per_queue_fifo_size=> 64,
g_output_block_per_queue_fifo_size=> 32,
g_wb_data_width => 16,
g_wb_addr_width => 2,
g_wb_sel_width => 2,
......@@ -1120,31 +1140,25 @@ begin
wb_i => cnx_master_out(c_SLAVE_TXTSU),
wb_o => cnx_master_in(c_SLAVE_TXTSU));
--TRIG2(15 downto 0) <= txtsu_timestamps(0).frame_id;
--TRIG2(21 downto 16) <= txtsu_timestamps(0).port_id;
--TRIG2(22) <= txtsu_timestamps(0).valid;
U_GPIO : xwb_gpio_port
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_pins => c_NUM_GPIO_PINS,
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_periph,
slave_i => cnx_master_out(c_SLAVE_GPIO),
slave_o => cnx_master_in(c_SLAVE_GPIO),
gpio_b => dummy,
gpio_out_o => gpio_out,
gpio_in_i => gpio_in);
uart_sel_o <= gpio_out(0);
gpio_o(0) <= gpio_out(0);
gpio_in(0) <= gpio_i(0);
-- U_GPIO : xwb_gpio_port
-- generic map (
-- g_interface_mode => PIPELINED,
-- g_address_granularity => BYTE,
-- g_num_pins => c_NUM_GPIO_PINS,
-- g_with_builtin_tristates => false)
-- port map (
-- clk_sys_i => clk_sys,
-- rst_n_i => rst_n_periph,
-- slave_i => cnx_master_out(c_SLAVE_GPIO),
-- slave_o => cnx_master_in(c_SLAVE_GPIO),
-- gpio_b => dummy,
-- gpio_out_o => gpio_out,
-- gpio_in_i => gpio_in
-- );
-- uart_sel_o <= gpio_out(0);
-- gpio_o(0) <= gpio_out(0);
-- gpio_in(0) <= gpio_i(0);
U_MiniBackplane_I2C : xwb_i2c_master
generic map (
......@@ -1234,22 +1248,22 @@ begin
-- PWM Controlle for mini-backplane fan drive
-----------------------------------------------------------------------------
U_PWM_Controller : xwb_simple_pwm
generic map (
g_num_channels => 2,
g_regs_size => 8,
g_default_period => 255,
g_default_presc => 30,
g_default_val => 255,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_periph,
slave_i => cnx_master_out(c_SLAVE_PWM),
slave_o => cnx_master_in(c_SLAVE_PWM),
pwm_o(0) => mb_fan1_pwm_o,
pwm_o(1) => mb_fan2_pwm_o);
-- U_PWM_Controller : xwb_simple_pwm
-- generic map (
-- g_num_channels => 2,
-- g_regs_size => 8,
-- g_default_period => 255,
-- g_default_presc => 30,
-- g_default_val => 255,
-- g_interface_mode => PIPELINED,
-- g_address_granularity => BYTE)
-- port map (
-- clk_sys_i => clk_sys,
-- rst_n_i => rst_n_periph,
-- slave_i => cnx_master_out(c_SLAVE_PWM),
-- slave_o => cnx_master_in(c_SLAVE_PWM),
-- pwm_o(0) => mb_fan1_pwm_o,
-- pwm_o(1) => mb_fan2_pwm_o);
-----------------------------------------------------------------------------
-- Interrupt assignment
......
top/pts_scb/wrs_sdb_pkg.vhd
View file @ 72a35829
......@@ -302,7 +302,7 @@ package wrs_sdb_pkg is
name => "WRSW SANDBOX ")));
-- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(7 downto 0) :=
constant c_rtbar_layout : t_sdb_record_array(8 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
......@@ -310,7 +310,9 @@ package wrs_sdb_pkg is
4 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00010300"), --GPIO
5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"));--GEN 10MHz
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700")); --SPI ext
constant c_rtbar_sdb_address : t_wishbone_address := x"00010800";
constant c_rtbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address);
......
top/pts_scb/wrsw_components_pkg.vhd
View file @ 72a35829
......@@ -153,6 +153,7 @@ package wrsw_components_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
......@@ -242,7 +243,13 @@ package wrsw_components_pkg is
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic);
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic);
end component;
component chipscope_icon
......
top/pts_scb/wrsw_top_pkg.vhd
View file @ 72a35829
......@@ -153,6 +153,7 @@ package wrsw_top_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pps_in_i : in std_logic;
ppsin_term_o : out std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
......@@ -215,7 +216,7 @@ package wrsw_top_pkg is
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
-- clk_500_o : out std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
wb_i : in t_wishbone_slave_in;
......@@ -231,6 +232,7 @@ package wrsw_top_pkg is
pps_csync_o : out std_logic;
pps_valid_o : out std_logic;
pps_ext_i : in std_logic;
ppsin_term_o : out std_logic;
pps_ext_o : out std_logic;
sel_clk_sys_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0');
......@@ -246,7 +248,14 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic
-- spll_dbg_o : out std_logic_vector(5 downto 0)
);
end component;
component chipscope_icon
......@@ -284,8 +293,9 @@ package wrsw_top_pkg is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
......@@ -298,13 +308,19 @@ package wrsw_top_pkg is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic;
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
......
top/scb_15ports/scb_top_synthesis.ucf
View file @ 72a35829
......@@ -13,6 +13,8 @@ NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "clk_ext_i" LOC=K13;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
......@@ -99,7 +101,7 @@ NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13";
# NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "uart_txd_o" LOC="E11";
......
top/scb_15ports/scb_top_synthesis.vhd
View file @ 72a35829
......@@ -74,6 +74,9 @@ entity scb_top_synthesis is
-- (from the AD9516 PLL output QDRII_200CLK)
fpga_clk_aux_p_i : in std_logic;
fpga_clk_aux_n_i : in std_logic;
-- External 10MHz input
clk_ext_i : in std_logic;
-------------------------------------------------------------------------------
-- Atmel EBI bus
......@@ -118,7 +121,7 @@ entity scb_top_synthesis is
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -291,7 +294,7 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -605,6 +608,7 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_i => clk_ext_i,
cpu_wb_i => top_master_out,
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
......@@ -616,7 +620,7 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => pll_status_i,
-- pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 72a35829
This source diff could not be displayed because it is too large. You can view the blob instead.
top/scb_18ports/scb_top_synthesis.vhd
View file @ 72a35829
......@@ -3,7 +3,7 @@
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : scb_top_synthesis.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk, Hongming
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-03-20
......@@ -53,6 +53,7 @@ use UNISIM.vcomponents.all;
entity scb_top_synthesis is
generic(
g_cpu_addr_width : integer := 19;
g_with_ext_AD9516: boolean := true;
g_simulation : boolean := false
);
port (
......@@ -70,9 +71,14 @@ entity scb_top_synthesis is
fpga_clk_dmtd_p_i : in std_logic;
fpga_clk_dmtd_n_i : in std_logic;
-- External 10MHz input
clk_ext_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
-- clk_sys_dbg_o: out std_logic;
-------------------------------------------------------------------------------
-- Atmel EBI bus
......@@ -100,8 +106,9 @@ entity scb_top_synthesis is
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic; -- 50Ohm termination enable for 1-PPS in
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
......@@ -117,7 +124,6 @@ entity scb_top_synthesis is
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -127,7 +133,21 @@ entity scb_top_synthesis is
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- WRS Low Jitter board
-------------------------------------------------------------------------------
ext_clk_62mhz_p_i : in std_logic:='0';
ext_clk_62mhz_n_i : in std_logic:='0';
ext_pll_status_i : in std_logic:='0';
ext_pll_lock_i : in std_logic:='0';
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
-------------------------------------------------------------------------------
-- Clock fanout control
-------------------------------------------------------------------------------
......@@ -175,10 +195,10 @@ entity scb_top_synthesis is
mbl_sda_b : inout std_logic_vector(1 downto 0);
sensors_scl_b: inout std_logic;
sensors_sda_b: inout std_logic;
sensors_sda_b: inout std_logic
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic
-- mb_fan1_pwm_o : out std_logic;
-- mb_fan2_pwm_o : out std_logic
);
......@@ -291,12 +311,14 @@ architecture Behavioral of scb_top_synthesis is
attribute buffer_type of clk_aux : signal is "BUFG";
attribute buffer_type of clk_sys : signal is "BUFG";
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic;
signal clk_ext_100 : std_logic;
signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic;
signal ext_clk_62mhz, ext_clk_62mhz_bufr : std_logic;
component scb_top_bare
generic (
g_num_ports : integer;
......@@ -315,15 +337,18 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in;
cpu_wb_o : out t_wishbone_slave_out;
cpu_irq_n_o : out std_logic;
pps_i : in std_logic;
ppsin_term_o : out std_logic;
pps_o : out std_logic;
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
......@@ -331,13 +356,18 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
ext_pll_mosi_o : out std_logic;
ext_pll_miso_i : in std_logic:='0';
ext_pll_sck_o : out std_logic;
ext_pll_cs_n_o : out std_logic;
ext_pll_sync_n_o : out std_logic;
ext_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
clk_en_o : out std_logic;
......@@ -521,12 +551,36 @@ begin
CLKIN => clk_25mhz);
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
I => pll_status_i,
O => clk_ext);
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
I => clk_ext_i,
O => clk_ext);
gen_with_ext_AD9516 : if (g_with_ext_AD9516) generate
U_Buf_ext_clk_62mhz : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => ext_clk_62mhz,
I => ext_clk_62mhz_p_i,
IB => ext_clk_62mhz_n_i);
U_Buf_ext_clk_62mhz_bufr : BUFR
port map (
CE => '1',
CLR => '0',
I => ext_clk_62mhz,
O => ext_clk_62mhz_bufr);
clk_ext_mul <= ext_clk_62mhz_bufr;
clk_ext_mul_locked <= ext_pll_lock_i; -- Fixme, connect to ext_pll_status
end generate gen_with_ext_AD9516;
gen_without_ext_AD9516 : if (not g_with_ext_AD9516) generate
U_Ext_PLL1: ext_pll_10_to_100
port map(
clk_ext_i => clk_ext,
......@@ -543,15 +597,16 @@ begin
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
end generate gen_without_ext_AD9516;
------------------------------------------------
cmp_wb_cpu_bridge : wb_cpu_bridge
......@@ -708,14 +763,17 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul,
clk_ext_i => clk_ext,
clk_ext_mul_i => clk_ext_mul,
clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
cpu_wb_i => top_master_out,
cpu_wb_o => top_master_in,
cpu_irq_n_o => cpu_irq_n_o,
pps_i => pps_i,
ppsin_term_o => ppsin_term_o,
pps_o => pps_o,
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
......@@ -723,13 +781,18 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => clk_ext,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
ext_pll_mosi_o => ext_pll_mosi_o,
ext_pll_miso_i => ext_pll_miso_i,
ext_pll_sck_o => ext_pll_sck_o,
ext_pll_cs_n_o => ext_pll_cs_n_o,
ext_pll_sync_n_o => ext_pll_sync_n_o,
ext_pll_reset_n_o => ext_pll_reset_n_o,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
......@@ -747,8 +810,8 @@ begin
i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in,
mb_fan1_pwm_o => mb_fan1_pwm_o,
mb_fan2_pwm_o => mb_fan2_pwm_o,
-- mb_fan1_pwm_o => mb_fan1_pwm_o,
-- mb_fan2_pwm_o => mb_fan2_pwm_o,
spll_dbg_o => open);
i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ 72a35829
This diff is collapsed.
top/scb_8ports/scb_top_synthesis.vhd
View file @ 72a35829
This diff is collapsed.
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