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White Rabbit Switch - Gateware
Commit 78d3f242 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrsw_ext_board: fix formatting, no technical change

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modules/wrsw_ext_board/Manifest.py
View file @ 78d3f242
files = [ "ext_board_check.vhd"]; files = [ "ext_board_check.vhd" ];
modules/wrsw_ext_board/ext_board_check.vhd
View file @ 78d3f242
...@@ -5,8 +5,6 @@ ...@@ -5,8 +5,6 @@
-- File : ext_board_check.vhd -- File : ext_board_check.vhd
-- Author : Mattia Rzzi -- Author : Mattia Rzzi
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2012-03-07
-- Last update: 2014-03-20
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -44,84 +42,86 @@ use work.wr_fabric_pkg.all; ...@@ -44,84 +42,86 @@ use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all; use work.endpoint_pkg.all;
use work.wrsw_top_pkg.all; use work.wrsw_top_pkg.all;
library UNISIM; library UNISIM;
use UNISIM.vcomponents.all; use UNISIM.vcomponents.all;
entity ext_board_check is entity ext_board_check is
generic ( generic (
g_pattern : std_logic_vector (63 downto 0) := x"CAFED00DCAFED00D"; g_pattern : std_logic_vector(63 downto 0) := x"CAFED00DCAFED00D";
g_clk_divider : integer := 16 g_clk_divider : integer := 16);
);
port ( port (
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
loopback_i : in std_logic; loopback_i : in std_logic;
loopback_o : out std_logic; loopback_o : out std_logic;
board_detected_o : out std_logic board_detected_o : out std_logic
); );
end ext_board_check; end ext_board_check;
architecture Behavioral of ext_board_check is architecture Behavioral of ext_board_check is
signal clk_divider : integer range 0 to g_clk_divider-1;
signal clk_en : std_logic;
signal bit_position : integer range 0 to g_pattern'length-1;
type fsm_states is (init, write_bit, read_bit, done);
signal fsm_state : fsm_states := init;
signal error_detected : std_logic;
begin
signal clk_divider : integer range 0 to g_clk_divider-1;
signal clk_en : std_logic;
signal bit_position : integer range 0 to g_pattern'length-1;
signal error_detected : std_logic;
clock_divider_inst : process (clk_sys_i) type fsm_states is (INIT, WRITE_BIT, READ_BIT, DONE);
begin signal fsm_state : fsm_states := INIT;
if rising_edge (clk_sys_i) then
clk_divider <= clk_divider + 1;
if (clk_divider = g_clk_divider - 1) then
clk_divider <= 0;
clk_en <= '1';
else
clk_en <= '0';
end if;
end if;
end process;
FSM_INST : process (clk_sys_i)
begin begin
if rst_n_i = '0' then
board_detected_o <= '0'; clock_divider_inst : process (clk_sys_i)
fsm_state <= init; begin
elsif rising_edge(clk_sys_i) then if rising_edge (clk_sys_i) then
case fsm_state is clk_divider <= clk_divider + 1;
when init => if (clk_divider = g_clk_divider - 1) then
board_detected_o <= '0'; clk_divider <= 0;
bit_position <= 0; clk_en <= '1';
fsm_state <= write_bit; else
error_detected <= '0'; clk_en <= '0';
when write_bit => end if;
loopback_o <= g_pattern(bit_position); end if;
if (clk_en = '1') then end process;
fsm_state <= read_bit;
end if; FSM_INST : process (clk_sys_i)
when read_bit => begin
if (g_pattern(bit_position) = loopback_i) then if rst_n_i = '0' then
if (bit_position = g_pattern'length-1) then board_detected_o <= '0';
fsm_state <= done; fsm_state <= INIT;
else elsif rising_edge(clk_sys_i) then
bit_position <= bit_position + 1; case fsm_state is
fsm_state <= write_bit; when INIT =>
end if; board_detected_o <= '0';
else bit_position <= 0;
error_detected <= '1'; fsm_state <= WRITE_BIT;
fsm_state <= done; error_detected <= '0';
end if;
when done => when WRITE_BIT =>
board_detected_o <= not error_detected; loopback_o <= g_pattern(bit_position);
when others => fsm_state <= init; if (clk_en = '1') then
end case; fsm_state <= READ_BIT;
end if; end if;
end process;
when READ_BIT =>
if (g_pattern(bit_position) = loopback_i) then
if (bit_position = g_pattern'length-1) then
fsm_state <= DONE;
else
bit_position <= bit_position + 1;
fsm_state <= WRITE_BIT;
end if;
else
error_detected <= '1';
fsm_state <= DONE;
end if;
when DONE =>
board_detected_o <= not error_detected;
when others =>
fsm_state <= INIT;
end case;
end if;
end process;
end Behavioral; end Behavioral;
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