swcore[new mpm]: adding PLL to provide clock for the core of the MPM

79ad9173 · Maciej Lipinski · d23cfc82 · 79ad9173 · 79ad9173
Commit 79ad9173 authored Feb 23, 2012 by Maciej Lipinski
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Manifest.py platform/xilinx/Manifest.py +1 -0

pll200MhZ.vhd platform/xilinx/pll200MhZ.vhd +202 -0

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--- a/platform/xilinx/Manifest.py
+++ b/platform/xilinx/Manifest.py
+files = ["pll200MhZ.vhd"];
--- a/platform/xilinx/pll200MhZ.vhd
+++ b/platform/xilinx/pll200MhZ.vhd
+-- file: clk_wiz_v3_1.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+-- Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1   200.000      0.000      50.0      128.566    117.286
+--
+------------------------------------------------------------------------------
+-- Input Clock   Input Freq (MHz)   Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary            62.5            0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity pll200MhZ is
+port
+ (-- Clock in ports
+  CLK_IN1           : in     std_logic;
+  -- Clock out ports
+  CLK_OUT1          : out    std_logic
+ );
+end pll200MhZ;
+
+architecture xilinx of pll200MhZ is
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "pll200MhZ,pll200MhZ,{component_name=pll200MhZ,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=16.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfbout_buf     : std_logic;
+  signal clkfboutb_unused : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout0b_unused  : std_logic;
+  signal clkout1_unused   : std_logic;
+  signal clkout1b_unused  : std_logic;
+  signal clkout2_unused   : std_logic;
+  signal clkout2b_unused  : std_logic;
+  signal clkout3_unused   : std_logic;
+  signal clkout3b_unused  : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  signal clkout6_unused   : std_logic;
+  -- Dynamic programming unused signals
+  signal do_unused        : std_logic_vector(15 downto 0);
+  signal drdy_unused      : std_logic;
+  -- Dynamic phase shift unused signals
+  signal psdone_unused    : std_logic;
+  -- Unused status signals
+  signal locked_unused    : std_logic;
+  signal clkfbstopped_unused : std_logic;
+  signal clkinstopped_unused : std_logic;
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : IBUFG
+  port map
+   (O => clkin1,
+    I => CLK_IN1);
+
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the MMCM primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+
+  mmcm_adv_inst : MMCM_ADV
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLKOUT4_CASCADE      => FALSE,
+    CLOCK_HOLD           => FALSE,
+    COMPENSATION         => "ZHOLD",
+    STARTUP_WAIT         => FALSE,
+    DIVCLK_DIVIDE        => 1,
+    CLKFBOUT_MULT_F      => 16.000,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKFBOUT_USE_FINE_PS => FALSE,
+    CLKOUT0_DIVIDE_F     => 5.000,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT0_USE_FINE_PS  => FALSE,
+    CLKIN1_PERIOD        => 16.000,
+    REF_JITTER1          => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKFBOUTB           => clkfboutb_unused,
+    CLKOUT0             => clkout0,
+    CLKOUT0B            => clkout0b_unused,
+    CLKOUT1             => clkout1_unused,
+    CLKOUT1B            => clkout1b_unused,
+    CLKOUT2             => clkout2_unused,
+    CLKOUT2B            => clkout2b_unused,
+    CLKOUT3             => clkout3_unused,
+    CLKOUT3B            => clkout3b_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    CLKOUT6             => clkout6_unused,
+    -- Input clock control
+    CLKFBIN             => clkfbout_buf,
+    CLKIN1              => clkin1,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => do_unused,
+    DRDY                => drdy_unused,
+    DWE                 => '0',
+    -- Ports for dynamic phase shift
+    PSCLK               => '0',
+    PSEN                => '0',
+    PSINCDEC            => '0',
+    PSDONE              => psdone_unused,
+    -- Other control and status signals
+    LOCKED              => locked_unused,
+    CLKINSTOPPED        => clkinstopped_unused,
+    CLKFBSTOPPED        => clkfbstopped_unused,
+    PWRDWN              => '0',
+    RST                 => '0');
+
+  -- Output buffering
+  -------------------------------------
+  clkf_buf : BUFG
+  port map
+   (O => clkfbout_buf,
+    I => clkfbout);
+
+
+  clkout1_buf : BUFG
+  port map
+   (O   => CLK_OUT1,
+    I   => clkout0);
+
+
+
+end xilinx;