Commit 7d9971a2 authored by Mattia Rizzi's avatar Mattia Rizzi Committed by Grzegorz Daniluk

Modified constraints for low-jitter daughterboard

parent 31d7252e
......@@ -16,6 +16,28 @@ NET "clk_aux_n_o" LOC=C19;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
NET "ext_clk_10mhz_p_i" LOC = AF30;
NET "ext_clk_10mhz_n_i" LOC = AG30;
INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0;
INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
NET "ext_clk_62mhz_p_i" LOC = AN33;
NET "ext_clk_62mhz_n_i" LOC = AN34;
NET "ext_board_rev_id_i[0]" LOC = AE29;
NET "ext_board_rev_id_i[1]" LOC = AE28;
NET "ext_board_rev_id_i[2]" LOC = AM32;
NET "ext_board_osc_freq_i[0]" LOC = AN32;
NET "ext_board_osc_freq_i[1]" LOC = AP33;
NET "ext_board_osc_freq_i[2]" LOC = AP32;
NET "ext_board_clk1_en" LOC = AL31;
NET "ext_board_clk2_en" LOC = AK31;
NET "ext_board_loopback_i" LOC = AM31;
NET "ext_board_loopback_o" LOC = AL30;
#EBI BUS
#NET "cpu_clk_i" LOC="";
......@@ -96,6 +118,9 @@ NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "ext_dac_main_sync_n_o" LOC = AH32;
NET "ext_dac_main_sclk_o" LOC = AK32;
NET "ext_dac_main_data_o" LOC = AK33;
NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16";
......@@ -105,6 +130,14 @@ NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "ext_pll_cs_n_o" LOC = AD27;
NET "ext_pll_sck_o" LOC = AD26;
NET "ext_pll_mosi_o" LOC = AE27;
NET "ext_pll_miso_i" LOC = AF28;
NET "ext_pll_reset_n_o" LOC = AF29;
NET "ext_pll_status_i" LOC = AD25;
NET "ext_pll_sync_n_o" LOC = AJ34;
NET "uart_txd_o" LOC="E11";
NET "uart_rxd_i" LOC="D11";
......@@ -301,6 +334,16 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "ext_clk_62mhz_p_i" TNM_NET = "ext_clk_62mhz_p_i";
TIMESPEC TS_ext_clk_62mhz_p_i = PERIOD "ext_clk_62mhz_p_i" 16 ns HIGH 50 %;
NET "ext_clk_62mhz_n_i" TNM_NET = "ext_clk_62mhz_n_i";
TIMESPEC TS_ext_clk_62mhz_n_i = PERIOD "ext_clk_62mhz_n_i" 16 ns HIGH 50 %;
NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i";
TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i";
TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
NET "from_phys[0]_rx_clk" TNM="phy_rx_clocks";
NET "from_phys[1]_rx_clk" TNM="phy_rx_clocks";
......@@ -344,6 +387,21 @@ TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d1" LOC = SLICE_X1Y22;
#CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24;
#CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24;
#CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21;
#CONFIG PROHIBIT = SLICE_X0Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
AREA_GROUP "pblock_ext_dmtd_2" GROUP=CLOSED;
AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
#INST "cmp_wb_cpu_bridge/gen_sync_chains_nosim.sync_ffs_wr/sync0" TNM = Ignore_sync_ffs;
......@@ -628,6 +686,9 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
......
......@@ -18,6 +18,29 @@ NET "clk_sys_dbg_o" LOC=AL33;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
NET "ext_clk_10mhz_p_i" LOC = AF30;
NET "ext_clk_10mhz_n_i" LOC = AG30;
INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0;
INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
NET "ext_clk_62mhz_p_i" LOC = AN33;
NET "ext_clk_62mhz_n_i" LOC = AN34;
NET "ext_board_rev_id_i[0]" LOC = AE29;
NET "ext_board_rev_id_i[1]" LOC = AE28;
NET "ext_board_rev_id_i[2]" LOC = AM32;
NET "ext_board_osc_freq_i[0]" LOC = AN32;
NET "ext_board_osc_freq_i[1]" LOC = AP33;
NET "ext_board_osc_freq_i[2]" LOC = AP32;
NET "ext_board_clk1_en" LOC = AL31;
NET "ext_board_clk2_en" LOC = AK31;
NET "ext_board_loopback_i" LOC = AM31;
NET "ext_board_loopback_o" LOC = AL30;
#NET "dbg_clk_ext_o" LOC=AM33;
#NET "spll_dbg_o<0>" LOC=AL33;
#NET "spll_dbg_o<1>" LOC=AE29;
......@@ -105,6 +128,9 @@ NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "ext_dac_main_sync_n_o" LOC = AH32;
NET "ext_dac_main_sclk_o" LOC = AK32;
NET "ext_dac_main_data_o" LOC = AK33;
NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16";
......@@ -114,6 +140,14 @@ NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "ext_pll_cs_n_o" LOC = AD27;
NET "ext_pll_sck_o" LOC = AD26;
NET "ext_pll_mosi_o" LOC = AE27;
NET "ext_pll_miso_i" LOC = AF28;
NET "ext_pll_reset_n_o" LOC = AF29;
NET "ext_pll_status_i" LOC = AD25;
NET "ext_pll_sync_n_o" LOC = AJ34;
NET "uart_txd_o" LOC="E11";
NET "uart_rxd_i" LOC="D11";
......@@ -298,6 +332,16 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "ext_clk_62mhz_p_i" TNM_NET = "ext_clk_62mhz_p_i";
TIMESPEC TS_ext_clk_62mhz_p_i = PERIOD "ext_clk_62mhz_p_i" 16 ns HIGH 50 %;
NET "ext_clk_62mhz_n_i" TNM_NET = "ext_clk_62mhz_n_i";
TIMESPEC TS_ext_clk_62mhz_n_i = PERIOD "ext_clk_62mhz_n_i" 16 ns HIGH 50 %;
NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i";
TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i";
TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
#NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
......@@ -366,6 +410,21 @@ TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d1" LOC = SLICE_X1Y22;
#CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24;
#CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24;
#CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21;
#CONFIG PROHIBIT = SLICE_X0Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
AREA_GROUP "pblock_ext_dmtd_2" GROUP=CLOSED;
AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
......
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