@@ -96,6 +118,9 @@ NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "ext_dac_main_sync_n_o" LOC = AH32;
NET "ext_dac_main_sclk_o" LOC = AK32;
NET "ext_dac_main_data_o" LOC = AK33;
NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16";
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@@ -105,6 +130,14 @@ NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "ext_pll_cs_n_o" LOC = AD27;
NET "ext_pll_sck_o" LOC = AD26;
NET "ext_pll_mosi_o" LOC = AE27;
NET "ext_pll_miso_i" LOC = AF28;
NET "ext_pll_reset_n_o" LOC = AF29;
NET "ext_pll_status_i" LOC = AD25;
NET "ext_pll_sync_n_o" LOC = AJ34;
NET "uart_txd_o" LOC="E11";
NET "uart_rxd_i" LOC="D11";
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@@ -301,6 +334,16 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "ext_clk_62mhz_p_i" TNM_NET = "ext_clk_62mhz_p_i";
TIMESPEC TS_ext_clk_62mhz_p_i = PERIOD "ext_clk_62mhz_p_i" 16 ns HIGH 50 %;
NET "ext_clk_62mhz_n_i" TNM_NET = "ext_clk_62mhz_n_i";
TIMESPEC TS_ext_clk_62mhz_n_i = PERIOD "ext_clk_62mhz_n_i" 16 ns HIGH 50 %;
NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i";
TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i";
TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
NET "from_phys[0]_rx_clk" TNM="phy_rx_clocks";
NET "from_phys[1]_rx_clk" TNM="phy_rx_clocks";
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@@ -344,6 +387,21 @@ TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d1" LOC = SLICE_X1Y22;
@@ -366,6 +410,21 @@ TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d1" LOC = SLICE_X1Y22;