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White Rabbit Switch - Gateware
Commit 868072d9 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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fix low-jitter constraints after rebase

parent 8c21725c
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Showing with 8 additions and 8 deletions
top/scb_18ports/scb_top_synthesis.ucf
View file @ 868072d9
......@@ -389,14 +389,14 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d1" LOC = SLICE_X1Y22;
#CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24;
#CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24;
#CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21;
#CONFIG PROHIBIT = SLICE_X0Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ 868072d9
......@@ -361,14 +361,14 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d1" LOC = SLICE_X1Y22;
#CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24;
#CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24;
#CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21;
#CONFIG PROHIBIT = SLICE_X0Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
......
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