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White Rabbit Switch - Gateware
Commit 8c21725c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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low phase drift calibration: cleanup 8-port version

parent fe0ba167
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Showing with 170 additions and 230 deletions
top/scb_8ports/scb_top_synthesis.ucf
View file @ 8c21725c
......@@ -47,6 +47,7 @@ NET "ljd_pll_locked_i" LOC = AH33;
#NET "spll_dbg_o<3>" LOC=AM32;
#NET "spll_dbg_o<4>" LOC=AN32;
#NET "spll_dbg_o<5>" LOC=AP33;
#EBI BUS
#NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34";
......@@ -153,15 +154,17 @@ NET "clk_en_o" LOC="AD16";
NET "clk_sel_o" LOC="AK17";
### GTX PORTS - reversed to match MB port ordering ###
NET "gtx0_3_clk_n_i" LOC="AK5";
NET "gtx0_3_clk_p_i" LOC="AK6";
NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx0_3_clk_n_i" LOC="AK5";
#NET "gtx0_3_clk_p_i" LOC="AK6";
#NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_n_i" LOC="AD5";
#NET "gtx4_7_clk_p_i" LOC="AD6";
#NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx8_11_clk_n_i" LOC="V5";
NET "gtx8_11_clk_p_i" LOC="V6";
......@@ -181,51 +184,71 @@ NET "gtx16_19_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx_rxp_i[7]" LOC="AP5"; # gtx0
NET "gtx_rxn_i[7]" LOC="AP6";
NET "gtx_txp_o[7]" LOC="AP1";
NET "gtx_txn_o[7]" LOC="AP2";
#NET "gtx_rxp_i[0]" LOC="AP5"; # gtx0
#NET "gtx_rxn_i[0]" LOC="AP6";
#NET "gtx_txp_o[0]" LOC="AP1";
#NET "gtx_txn_o[0]" LOC="AP2";
#NET "gtx_rxp_i[1]" LOC="AM5"; # gtx1
#NET "gtx_rxn_i[1]" LOC="AM6";
#NET "gtx_txp_o[1]" LOC="AN3";
#NET "gtx_txn_o[1]" LOC="AN4";
#NET "gtx_rxp_i[2]" LOC="AL3"; # gtx2
#NET "gtx_rxn_i[2]" LOC="AL4";
#NET "gtx_txp_o[2]" LOC="AM1";
#NET "gtx_txn_o[2]" LOC="AM2";
#NET "gtx_rxp_i[3]" LOC="AJ3";
#NET "gtx_rxn_i[3]" LOC="AJ4";
#NET "gtx_txp_o[3]" LOC="AK1";
#NET "gtx_txn_o[3]" LOC="AK2";
#NET "gtx_rxp_i[4]" LOC="AG3";
#NET "gtx_rxn_i[4]" LOC="AG4";
#NET "gtx_txp_o[4]" LOC="AH1";
#NET "gtx_txn_o[4]" LOC="AH2";
#NET "gtx_rxp_i[5]" LOC="AF5";
#NET "gtx_rxn_i[5]" LOC="AF6";
#NET "gtx_txp_o[5]" LOC="AF1";
#NET "gtx_txn_o[5]" LOC="AF2";
#NET "gtx_rxp_i[6]" LOC="AE3";
#NET "gtx_rxn_i[6]" LOC="AE4";
#NET "gtx_txp_o[6]" LOC="AD1";
#NET "gtx_txn_o[6]" LOC="AD2";
#NET "gtx_rxp_i[7]" LOC="AC3";
#NET "gtx_rxn_i[7]" LOC="AC4";
#NET "gtx_txp_o[7]" LOC="AB1";
#NET "gtx_txn_o[7]" LOC="AB2";
#NET "gtx_rxp_i[8]" LOC="AA3";
#NET "gtx_rxn_i[8]" LOC="AA4";
#NET "gtx_txp_o[8]" LOC="Y1";
#NET "gtx_txn_o[8]" LOC="Y2";
#NET "gtx_rxp_i[9]" LOC="W3";
#NET "gtx_rxn_i[9]" LOC="W4";
#NET "gtx_txp_o[9]" LOC="V1";
#NET "gtx_txn_o[9]" LOC="V2";
#NET "gtx_rxp_i[7]" LOC="U3";
#NET "gtx_rxn_i[7]" LOC="U4";
#NET "gtx_txp_o[7]" LOC="T1";
#NET "gtx_txn_o[7]" LOC="T2";
NET "gtx_rxp_i[7]" LOC="U3";
NET "gtx_rxn_i[7]" LOC="U4";
NET "gtx_txp_o[7]" LOC="T1";
NET "gtx_txn_o[7]" LOC="T2";
NET "gtx_rxp_i[6]" LOC="R3";
NET "gtx_rxn_i[6]" LOC="R4";
......@@ -316,49 +339,6 @@ TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i";
TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
#NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_1__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[1].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[2].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[4].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[4].U_PHY/tx_out_clk_bufin;
#TIMESPEC TS_gen_phys_4__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[4].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[5].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[6].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[6].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_6__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[6].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[7].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_7__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[8].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[8].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[8].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[8].U_PHY/tx_out_clk_bufin;
#TIMESPEC TS_gen_phys_8__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[8].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[9].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[9].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_9__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[9].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[10].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[10].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_10__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[10].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[11].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[11].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_11__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[11].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[12].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[12].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_12__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[12].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[13].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[13].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_13__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[13].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[14].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[14].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_14__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[14].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[15].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[15].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_15__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[15].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[16].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[16].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_16__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[16].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[16].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[16].U_PHY/tx_out_clk_bufin;
#TIMESPEC TS_gen_phys_16__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[16].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[17].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[17].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i;
#TIMESPEC TS_gtx0_3_clk_n_i = PERIOD "gtx0_3_clk_n_i" 8 ns HIGH 50%;
#NET "gtx0_3_clk_p_i" TNM_NET = gtx0_3_clk_p_i;
......@@ -399,39 +379,36 @@ AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
PIN "gen_phys_bufr[0].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys_bufr[1].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys_bufr[2].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys_bufr[3].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys[4].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys[5].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "gen_phys[6].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "U_LastPHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "dbg_samp_rx_p_i" LOC="AM33";
#NET "dbg_samp_rx_n_i" LOC="AL33";
#NET "dbg_samp_tx_p_i" LOC="AE28";
#NET "dbg_samp_tx_n_i" LOC="AE29";
#NET "dbg_dmtd_tx_clean_o" LOC="AN32";
#NET "dbg_dmtd_rx_clean_o" LOC="AM32";
#NET "dbg_dmtd_tx_raw_o" LOC="AP32";
#NET "dbg_dmtd_rx_raw_o" LOC="AP33";
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2018/06/22
#NET "gen_phys[4].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys[4].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys[5].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys[5].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys[6].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys[6].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys_bufr[0].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys_bufr[0].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys_bufr[1].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys_bufr[1].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys_bufr[2].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys_bufr[2].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys_bufr[3].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys_bufr[3].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "U_LastPHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "U_LastPHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/07/12
NET "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_0__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_0__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_1__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_1__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_2__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[2].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[2].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_2__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[2].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_3__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[3].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[3].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_3__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[3].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_4__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_4__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_5__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_5__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_6__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_6__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_7__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_7__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
top/scb_8ports/scb_top_synthesis.vhd
View file @ 8c21725c
......@@ -44,7 +44,7 @@ use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_txtsu_pkg.all;
use work.wrsw_top_pkg.all;
use work.wrsw_shared_types_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -173,11 +173,11 @@ entity scb_top_synthesis is
-- GTX ports
---------------------------------------------------------------------------
gtx0_3_clk_n_i : in std_logic;
gtx0_3_clk_p_i : in std_logic;
--gtx0_3_clk_n_i : in std_logic;
--gtx0_3_clk_p_i : in std_logic;
-- gtx4_7_clk_n_i : in std_logic;
-- gtx4_7_clk_p_i : in std_logic;
--gtx4_7_clk_n_i : in std_logic;
--gtx4_7_clk_p_i : in std_logic;
gtx8_11_clk_n_i : in std_logic;
gtx8_11_clk_p_i : in std_logic;
......@@ -345,7 +345,8 @@ architecture Behavioral of scb_top_synthesis is
g_with_PSTATS : boolean;
g_with_muxed_CS : boolean;
g_with_watchdog : boolean;
g_inj_per_EP : std_logic_vector(17 downto 0));
g_inj_per_EP : std_logic_vector(17 downto 0);
g_phy_lpcalib : t_bool_array(0 to 17) := c_BOOL_FALSE_ARRAY);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
......@@ -438,35 +439,39 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
signal phy_rx_clk_vec: std_logic_vector(7 downto 0);
type t_bufr_phy_assignment_array is array(integer range <>) of boolean;
constant c_phy_use_bufr_for_tx_clock : t_bufr_phy_assignment_array(0 to 7) :=
(
true,
true,
true,
true,
false,
false,
true,
true
);
type t_phy_conf is record
rxclk_bufr : boolean;
txclk_bufr : boolean;
end record;
type t_phy_conf_array is array(integer range <>) of t_phy_conf;
constant c_PHY_CONF : t_phy_conf_array(0 to 7) :=
( -- rx_bufr, tx_bufr
0 => (false , true ),
1 => (false , true ),
2 => (false , true ),
3 => (false , true ),
4 => (false , false ),
5 => (false , false ),
6 => (false , false ),
7 => (false , false )
);
constant c_PHY_LPCALIB : t_bool_array(0 to 17) :=
(
0 => true,
1 => true,
2 => true,
3 => true,
4 => true,
5 => true,
6 => true,
7 => true,
others => false
);
begin
U_Clk_Buf_GTX0_3 : IBUFDS_GTXE1
port map
(
O => clk_gtx0_3,
ODIV2 => open,
CEB => '0',
I => gtx0_3_clk_p_i,
IB => gtx0_3_clk_n_i
);
U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1
port map
(
......@@ -700,116 +705,74 @@ begin
--clk_gtx(14 downto 12) <= (others => clk_gtx12_15);
--clk_gtx(17 downto 16) <= (others => clk_gtx16_19);
--generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr : for i in 0 to 3 generate
U_PHY : entity work.wr_gtx_phy_virtex6_lp
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr_for_rx_clock => false,
g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(i),
g_id => i)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_rbclk_sampled_o =>from_phys(i).rx_sampled_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
debug_o => from_phys(i).debug,
debug_i => to_phys(i).debug,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys_bufr;
gen_phys : for i in 4 to c_NUM_PHYS-2 generate
U_PHY : entity work.wr_gtx_phy_virtex6_lp
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(i),
g_use_bufr_for_rx_clock => false,
g_id => i)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_rbclk_sampled_o =>from_phys(i).rx_sampled_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen,
debug_o => from_phys(i).debug,
debug_i => to_phys(i).debug,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
gen_phys : for i in 0 to c_NUM_PHYS-1 generate
-- Instantiate GTX with low phase drift calibration
gen_lp: if c_PHY_LPCALIB(i) generate
U_PHY : entity work.wr_gtx_phy_virtex6_lp
generic map (
g_simulation => f_bool2int(g_simulation),
g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr,
g_txclk_bufr => c_PHY_CONF(i).txclk_bufr,
g_id => i)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
clk_sampled_o =>from_phys(i).rx_sampled_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
lpc_stat_o => from_phys(i).lpc_stat,
lpc_ctrl_i => to_phys(i).lpc_ctrl,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
end generate gen_lp;
-- Instantiate regular GTX for all other ports
gen_no_lp: if not c_PHY_LPCALIB(i) generate
U_PHY : entity work.wr_gtx_phy_virtex6
generic map (
g_simulation => f_bool2int(g_simulation),
g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
end generate gen_no_lp;
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys;
U_LastPHY : entity work.wr_gtx_phy_virtex6_lp
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => 0,
g_use_bufr_for_rx_clock => false,
g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(7),
g_id => c_NUM_PHYS-1)
port map (
clk_gtx_i => clk_gtx0_3,
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(c_NUM_PHYS-1).tx_data,
tx_k_i => to_phys(c_NUM_PHYS-1).tx_k,
tx_disparity_o => from_phys(c_NUM_PHYS-1).tx_disparity,
tx_enc_err_o => from_phys(c_NUM_PHYS-1).tx_enc_err,
rx_rbclk_o => from_phys(c_NUM_PHYS-1).rx_clk,
rx_rbclk_sampled_o =>from_phys(c_NUM_PHYS-1).rx_sampled_clk,
rx_data_o => from_phys(c_NUM_PHYS-1).rx_data,
rx_k_o => from_phys(c_NUM_PHYS-1).rx_k,
rx_enc_err_o => from_phys(c_NUM_PHYS-1).rx_enc_err,
rx_bitslide_o => from_phys(c_NUM_PHYS-1).rx_bitslide,
rst_i => to_phys(c_NUM_PHYS-1).rst,
loopen_i => to_phys(c_NUM_PHYS-1).loopen,
debug_o => from_phys(c_NUM_PHYS-1).debug,
debug_i => to_phys(c_NUM_PHYS-1).debug,
pad_txn_o => gtx_txn_o(7),
pad_txp_o => gtx_txp_o(7),
pad_rxn_i => gtx_rxn_i(7),
pad_rxp_i => gtx_rxp_i(7),
rdy_o => from_phys(c_NUM_PHYS-1).rdy
);
from_phys(c_NUM_PHYS-1).ref_clk <= clk_ref;
gen_terminate_unused_phys : for i in c_NUM_PORTS to c_NUM_PHYS-1 generate
to_phys(i).tx_data <= (others => '0');
to_phys(i).tx_k <= (others => '0');
......@@ -835,8 +798,8 @@ begin
g_with_PSTATS => true,
g_with_muxed_CS => false,
g_with_watchdog => true,
g_inj_per_EP => "00" & x"0000"
)
g_inj_per_EP => "00" & x"0000",
g_phy_lpcalib => c_PHY_LPCALIB)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup,
......
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