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White Rabbit Switch - Gateware
Commit 8c21725c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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low phase drift calibration: cleanup 8-port version

parent fe0ba167
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top/scb_8ports/scb_top_synthesis.ucf
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top/scb_8ports/scb_top_synthesis.vhd
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...@@ -44,7 +44,7 @@ use work.wr_fabric_pkg.all; ...@@ -44,7 +44,7 @@ use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all; use work.endpoint_pkg.all;
use work.wr_txtsu_pkg.all; use work.wr_txtsu_pkg.all;
use work.wrsw_top_pkg.all; use work.wrsw_top_pkg.all;
use work.wrsw_shared_types_pkg.all;
library UNISIM; library UNISIM;
use UNISIM.vcomponents.all; use UNISIM.vcomponents.all;
...@@ -173,11 +173,11 @@ entity scb_top_synthesis is ...@@ -173,11 +173,11 @@ entity scb_top_synthesis is
-- GTX ports -- GTX ports
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
gtx0_3_clk_n_i : in std_logic; --gtx0_3_clk_n_i : in std_logic;
gtx0_3_clk_p_i : in std_logic; --gtx0_3_clk_p_i : in std_logic;
-- gtx4_7_clk_n_i : in std_logic; --gtx4_7_clk_n_i : in std_logic;
-- gtx4_7_clk_p_i : in std_logic; --gtx4_7_clk_p_i : in std_logic;
gtx8_11_clk_n_i : in std_logic; gtx8_11_clk_n_i : in std_logic;
gtx8_11_clk_p_i : in std_logic; gtx8_11_clk_p_i : in std_logic;
...@@ -345,7 +345,8 @@ architecture Behavioral of scb_top_synthesis is ...@@ -345,7 +345,8 @@ architecture Behavioral of scb_top_synthesis is
g_with_PSTATS : boolean; g_with_PSTATS : boolean;
g_with_muxed_CS : boolean; g_with_muxed_CS : boolean;
g_with_watchdog : boolean; g_with_watchdog : boolean;
g_inj_per_EP : std_logic_vector(17 downto 0)); g_inj_per_EP : std_logic_vector(17 downto 0);
g_phy_lpcalib : t_bool_array(0 to 17) := c_BOOL_FALSE_ARRAY);
port ( port (
sys_rst_n_i : in std_logic; sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic; clk_startup_i : in std_logic;
...@@ -438,35 +439,39 @@ architecture Behavioral of scb_top_synthesis is ...@@ -438,35 +439,39 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG2 : std_logic_vector(31 downto 0); signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0); signal TRIG3 : std_logic_vector(31 downto 0);
signal phy_rx_clk_vec: std_logic_vector(7 downto 0); type t_phy_conf is record
rxclk_bufr : boolean;
type t_bufr_phy_assignment_array is array(integer range <>) of boolean; txclk_bufr : boolean;
end record;
type t_phy_conf_array is array(integer range <>) of t_phy_conf;
constant c_PHY_CONF : t_phy_conf_array(0 to 7) :=
( -- rx_bufr, tx_bufr
0 => (false , true ),
1 => (false , true ),
2 => (false , true ),
3 => (false , true ),
4 => (false , false ),
5 => (false , false ),
6 => (false , false ),
7 => (false , false )
);
constant c_phy_use_bufr_for_tx_clock : t_bufr_phy_assignment_array(0 to 7) := constant c_PHY_LPCALIB : t_bool_array(0 to 17) :=
( (
true, 0 => true,
true, 1 => true,
true, 2 => true,
true, 3 => true,
false, 4 => true,
false, 5 => true,
true, 6 => true,
true 7 => true,
others => false
); );
begin begin
U_Clk_Buf_GTX0_3 : IBUFDS_GTXE1
port map
(
O => clk_gtx0_3,
ODIV2 => open,
CEB => '0',
I => gtx0_3_clk_p_i,
IB => gtx0_3_clk_n_i
);
U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1 U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1
port map port map
( (
...@@ -700,14 +705,15 @@ begin ...@@ -700,14 +705,15 @@ begin
--clk_gtx(14 downto 12) <= (others => clk_gtx12_15); --clk_gtx(14 downto 12) <= (others => clk_gtx12_15);
--clk_gtx(17 downto 16) <= (others => clk_gtx16_19); --clk_gtx(17 downto 16) <= (others => clk_gtx16_19);
--generate first 4 GTXes with BUFR to reduce the number of global clocks --generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr : for i in 0 to 3 generate gen_phys : for i in 0 to c_NUM_PHYS-1 generate
-- Instantiate GTX with low phase drift calibration
gen_lp: if c_PHY_LPCALIB(i) generate
U_PHY : entity work.wr_gtx_phy_virtex6_lp U_PHY : entity work.wr_gtx_phy_virtex6_lp
generic map ( generic map (
g_simulation => f_bool2int(g_simulation), g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4), g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr,
g_use_bufr_for_rx_clock => false, g_txclk_bufr => c_PHY_CONF(i).txclk_bufr,
g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(i),
g_id => i) g_id => i)
port map ( port map (
clk_gtx_i => clk_gtx(i), clk_gtx_i => clk_gtx(i),
...@@ -719,14 +725,14 @@ begin ...@@ -719,14 +725,14 @@ begin
tx_disparity_o => from_phys(i).tx_disparity, tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err, tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk, rx_rbclk_o => from_phys(i).rx_clk,
rx_rbclk_sampled_o =>from_phys(i).rx_sampled_clk, clk_sampled_o =>from_phys(i).rx_sampled_clk,
rx_data_o => from_phys(i).rx_data, rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k, rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err, rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide, rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst, rst_i => to_phys(i).rst,
debug_o => from_phys(i).debug, lpc_stat_o => from_phys(i).lpc_stat,
debug_i => to_phys(i).debug, lpc_ctrl_i => to_phys(i).lpc_ctrl,
loopen_i => to_phys(i).loopen, loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i), pad_txn_o => gtx_txn_o(i),
...@@ -734,82 +740,39 @@ begin ...@@ -734,82 +740,39 @@ begin
pad_rxn_i => gtx_rxn_i(i), pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i), pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy); rdy_o => from_phys(i).rdy);
end generate gen_lp;
from_phys(i).ref_clk <= clk_ref; -- Instantiate regular GTX for all other ports
end generate gen_phys_bufr; gen_no_lp: if not c_PHY_LPCALIB(i) generate
U_PHY : entity work.wr_gtx_phy_virtex6
gen_phys : for i in 4 to c_NUM_PHYS-2 generate
U_PHY : entity work.wr_gtx_phy_virtex6_lp
generic map ( generic map (
g_simulation => f_bool2int(g_simulation), g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4), g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr)
g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(i),
g_use_bufr_for_rx_clock => false,
g_id => i)
port map ( port map (
clk_gtx_i => clk_gtx(i), clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref, clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(i).tx_data, tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k, tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity, tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err, tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk, rx_rbclk_o => from_phys(i).rx_clk,
rx_rbclk_sampled_o =>from_phys(i).rx_sampled_clk,
rx_data_o => from_phys(i).rx_data, rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k, rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err, rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide, rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst, rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen, loopen_i => to_phys(i).loopen,
debug_o => from_phys(i).debug,
debug_i => to_phys(i).debug,
pad_txn_o => gtx_txn_o(i), pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i), pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i), pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i), pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy); rdy_o => from_phys(i).rdy);
end generate gen_no_lp;
from_phys(i).ref_clk <= clk_ref; from_phys(i).ref_clk <= clk_ref;
end generate gen_phys; end generate gen_phys;
U_LastPHY : entity work.wr_gtx_phy_virtex6_lp
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => 0,
g_use_bufr_for_rx_clock => false,
g_use_bufr_for_tx_clock => c_phy_use_bufr_for_tx_clock(7),
g_id => c_NUM_PHYS-1)
port map (
clk_gtx_i => clk_gtx0_3,
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(c_NUM_PHYS-1).tx_data,
tx_k_i => to_phys(c_NUM_PHYS-1).tx_k,
tx_disparity_o => from_phys(c_NUM_PHYS-1).tx_disparity,
tx_enc_err_o => from_phys(c_NUM_PHYS-1).tx_enc_err,
rx_rbclk_o => from_phys(c_NUM_PHYS-1).rx_clk,
rx_rbclk_sampled_o =>from_phys(c_NUM_PHYS-1).rx_sampled_clk,
rx_data_o => from_phys(c_NUM_PHYS-1).rx_data,
rx_k_o => from_phys(c_NUM_PHYS-1).rx_k,
rx_enc_err_o => from_phys(c_NUM_PHYS-1).rx_enc_err,
rx_bitslide_o => from_phys(c_NUM_PHYS-1).rx_bitslide,
rst_i => to_phys(c_NUM_PHYS-1).rst,
loopen_i => to_phys(c_NUM_PHYS-1).loopen,
debug_o => from_phys(c_NUM_PHYS-1).debug,
debug_i => to_phys(c_NUM_PHYS-1).debug,
pad_txn_o => gtx_txn_o(7),
pad_txp_o => gtx_txp_o(7),
pad_rxn_i => gtx_rxn_i(7),
pad_rxp_i => gtx_rxp_i(7),
rdy_o => from_phys(c_NUM_PHYS-1).rdy
);
from_phys(c_NUM_PHYS-1).ref_clk <= clk_ref;
gen_terminate_unused_phys : for i in c_NUM_PORTS to c_NUM_PHYS-1 generate gen_terminate_unused_phys : for i in c_NUM_PORTS to c_NUM_PHYS-1 generate
to_phys(i).tx_data <= (others => '0'); to_phys(i).tx_data <= (others => '0');
to_phys(i).tx_k <= (others => '0'); to_phys(i).tx_k <= (others => '0');
...@@ -835,8 +798,8 @@ begin ...@@ -835,8 +798,8 @@ begin
g_with_PSTATS => true, g_with_PSTATS => true,
g_with_muxed_CS => false, g_with_muxed_CS => false,
g_with_watchdog => true, g_with_watchdog => true,
g_inj_per_EP => "00" & x"0000" g_inj_per_EP => "00" & x"0000",
) g_phy_lpcalib => c_PHY_LPCALIB)
port map ( port map (
sys_rst_n_i => sys_rst_n_i, sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup, clk_startup_i => clk_sys_startup,
......
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