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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
Commits
97e035f9
Commit
97e035f9
authored
Mar 16, 2012
by
Tomasz Wlostowski
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modules/wrsw_nic: support for invalid timestamp indication
parent
f2de0510
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2 changed files
with
15 additions
and
10 deletions
+15
-10
nic_descriptors_pkg.vhd
modules/wrsw_nic/nic_descriptors_pkg.vhd
+6
-2
nic_rx_fsm.vhd
modules/wrsw_nic/nic_rx_fsm.vhd
+9
-8
No files found.
modules/wrsw_nic/nic_descriptors_pkg.vhd
View file @
97e035f9
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Company : CERN BE-Co-HT
-- Created : 2010-11-24
-- Created : 2010-11-24
-- Last update: 201
0-12-01
-- Last update: 201
2-03-16
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL
-- Standard : VHDL
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -49,6 +49,9 @@ package nic_descriptors_pkg is
...
@@ -49,6 +49,9 @@ package nic_descriptors_pkg is
error
:
std_logic
;
-- RX error indication
error
:
std_logic
;
-- RX error indication
port_id
:
std_logic_vector
(
5
downto
0
);
-- Packet source port ID
port_id
:
std_logic_vector
(
5
downto
0
);
-- Packet source port ID
got_ts
:
std_logic
;
-- Got a timestamp?
got_ts
:
std_logic
;
-- Got a timestamp?
ts_incorrect
:
std_logic
;
-- 1: Timestamp may be incorrect (generated
-- during time base adjustment)
ts_r
:
std_logic_vector
(
27
downto
0
);
-- Rising edge timestamp
ts_r
:
std_logic_vector
(
27
downto
0
);
-- Rising edge timestamp
ts_f
:
std_logic_vector
(
3
downto
0
);
-- Falling edge timestamp
ts_f
:
std_logic_vector
(
3
downto
0
);
-- Falling edge timestamp
len
:
std_logic_vector
(
c_nic_buf_size_log2
-1
downto
0
);
-- Length of the allocated buffer
len
:
std_logic_vector
(
c_nic_buf_size_log2
-1
downto
0
);
-- Length of the allocated buffer
...
@@ -105,7 +108,7 @@ package body NIC_descriptors_pkg is
...
@@ -105,7 +108,7 @@ package body NIC_descriptors_pkg is
variable
tmp
:
std_logic_vector
(
31
downto
0
);
variable
tmp
:
std_logic_vector
(
31
downto
0
);
begin
begin
case
regnum
is
case
regnum
is
when
1
=>
tmp
:
=
"0000000000000000
0"
&
desc
.
got_ts
&
desc
.
port_id
&
"000000"
&
desc
.
error
&
desc
.
empty
;
when
1
=>
tmp
:
=
"0000000000000000
"
&
desc
.
ts_incorrect
&
desc
.
got_ts
&
desc
.
port_id
&
"000000"
&
desc
.
error
&
desc
.
empty
;
when
2
=>
tmp
:
=
desc
.
ts_f
&
desc
.
ts_r
;
when
2
=>
tmp
:
=
desc
.
ts_f
&
desc
.
ts_r
;
when
3
=>
tmp
:
=
f_resize_slv
(
desc
.
len
,
16
)
&
f_resize_slv
(
desc
.
offset
,
16
);
when
3
=>
tmp
:
=
f_resize_slv
(
desc
.
len
,
16
)
&
f_resize_slv
(
desc
.
offset
,
16
);
when
others
=>
null
;
when
others
=>
null
;
...
@@ -148,6 +151,7 @@ package body NIC_descriptors_pkg is
...
@@ -148,6 +151,7 @@ package body NIC_descriptors_pkg is
desc
.
error
:
=
mem_input
(
1
);
desc
.
error
:
=
mem_input
(
1
);
desc
.
port_id
:
=
mem_input
(
13
downto
8
);
desc
.
port_id
:
=
mem_input
(
13
downto
8
);
desc
.
got_ts
:
=
mem_input
(
14
);
desc
.
got_ts
:
=
mem_input
(
14
);
desc
.
ts_incorrect
:
=
mem_input
(
15
);
when
2
=>
when
2
=>
desc
.
ts_f
:
=
mem_input
(
31
downto
28
);
desc
.
ts_f
:
=
mem_input
(
31
downto
28
);
...
...
modules/wrsw_nic/nic_rx_fsm.vhd
View file @
97e035f9
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Company : CERN BE-Co-HT
-- Created : 2010-11-24
-- Created : 2010-11-24
-- Last update: 2012-0
1-24
-- Last update: 2012-0
3-16
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL
-- Standard : VHDL
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -48,7 +48,7 @@ entity nic_rx_fsm is
...
@@ -48,7 +48,7 @@ entity nic_rx_fsm is
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Wishbone regs
-- Wishbone regs
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
bna_i
:
in
std_logic
;
bna_i
:
in
std_logic
;
regs_i
:
in
t_nic_out_registers
;
regs_i
:
in
t_nic_out_registers
;
regs_o
:
out
t_nic_in_registers
;
regs_o
:
out
t_nic_in_registers
;
...
@@ -369,6 +369,7 @@ begin
...
@@ -369,6 +369,7 @@ begin
if
(
oob_sreg
(
0
)
=
'1'
)
then
-- 1st OOB word
if
(
oob_sreg
(
0
)
=
'1'
)
then
-- 1st OOB word
cur_rx_desc
.
port_id
<=
'0'
&
fab_in
.
data
(
4
downto
0
);
cur_rx_desc
.
port_id
<=
'0'
&
fab_in
.
data
(
4
downto
0
);
cur_rx_desc
.
ts_incorrect
<=
fab_in
.
data
(
11
);
end
if
;
end
if
;
if
(
oob_sreg
(
1
)
=
'1'
)
then
-- 2nd OOB word
if
(
oob_sreg
(
1
)
=
'1'
)
then
-- 2nd OOB word
...
@@ -385,7 +386,7 @@ begin
...
@@ -385,7 +386,7 @@ begin
-- we've got 2 valid word of the payload in rx_buf_data, write them to the
-- we've got 2 valid word of the payload in rx_buf_data, write them to the
-- memory
-- memory
if
(
rx_rdreg_toggle
=
'1'
and
fab_in
.
dvalid
=
'1'
and
(
wrf_is_oob
=
'1'
or
wrf_is_payload
=
'1'
)
and
wrf_terminate
=
'0'
)
then
if
(
rx_rdreg_toggle
=
'1'
and
fab_in
.
dvalid
=
'1'
and
(
wrf_is_oob
=
'1'
or
wrf_is_payload
=
'1'
)
and
wrf_terminate
=
'0'
)
then
increase_addr
<=
'1'
;
increase_addr
<=
'1'
;
buf_wr_o
<=
'1'
;
buf_wr_o
<=
'1'
;
...
...
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